Patent Application
20060268583
The invention relates to a preferably integrated circuit configuration provided for the actuation of power switches disposed in bridge circuit topology as well as an associated method. Such bridge configurations of power switches are known as semi-, H-(two-phase) or as three-phase bridge circuits, the single phase semibridge representing the basic module of such electronic power circuits. In a semibridge circuit, two power switches, a first, so-called TOP switch, and a second, so-called BOT switch, are connected in series. As a rule, such a semibridge is connected to a direct current link. The center tapping is typically connected to a load.
When the power switches are implemented as a power semiconductor component or as a multiplicity of identical series- or parallel-connected power semiconductor components, an actuation circuit is necessary for the actuation of the power switches. Within prior art such actuation circuits are comprised of several subcircuits or function blocks. The actuation signal from a superordinate control is processed in a first subcircuit of the primary side, and, via further components, supplied to the driver circuits, the secondary sides and lastly to the control input of the particular power switch. In semibridge configurations with higher link voltages, for example greater than 50 V, the primary side, in potential/electrical terms, is isolated from the secondary side for the processing of the control signals, since the power switches, at least the TOP switch of the semibridge, during operation are not at a constant potential and consequently the isolation in terms of voltage is unavoidable. This isolation according to prior art takes place for example by means of isolating transformers, optocouplers, for example optical wave guides. This electrical isolation is at least carried out for the TOP switch, but at higher powers also for the BOT switch due to a possible breaking of the ground reference potential during the switching.
Known are also integrated circuit configurations for power switches of the voltage classes up to 600 V or 1200 V, which forgo the use of external electrical isolation. In these monolithically integrated circuits, according to prior art, so-called level shifters are utilized, at least for the TOP switch. These electronic components and techniques for isolation consequently overcome the potential difference of the primary side with respect to the secondary side.
In this described form of a monolithically integrated circuit configuration for actuating power switches no possibility exists, at least in the simplest configuration for the secondary side of the TOP switch, for error feedback to the primary side.
The invention has as its aim to introduce a preferably monolithically integrated circuit configuration for power semiconductor switches in bridge configuration, as well as an associated method, which permits the error feedback from the secondary side to the primary side by means of simple and integratable means.
According to the invention this aim is attained through the measures of the characterizing clause of claims 1 and 4. Preferred embodiments are described in the dependent claims.
The inventive concept builds on a known circuit configuration for actuating power semiconductor switches in bridge topology comprised of a primary-side section (primary side) and one secondary-side section (secondary side) each. The bridge circuit comprises a first switch, the TOP switch, and a second switch, the BOT switch. These are connected according to prior art to a DC link. The center tapping between the TOP and the BOT switch forms the AC output of the bridge circuit. The circuit configuration for the actuation comprises on its primary side at least one signal processing means and at least one level shifter for the potential-free actuation of at least one secondary side. This secondary side, in turn, comprises at least one signal processing means as well as at least one driver stage for the particular switch.
The invention introduces a preferably monolithically integrated circuit configuration for actuating power semiconductor switches, wherein for the conveyance of the error status from the secondary side to the primary side a diode is disposed between the primary side and the secondary side. The anode-side terminal of the diode is disposed at the primary side and the cathode-side terminal at the secondary side of the driver circuit. The circuit configuration furthermore comprises on the primary side a filtering means and a current acquisition means for the error status detection as well as on the secondary side a circuit for the error status implementation. These two circuit sections are connected to the diode.
The associated method for the error conveyance from the secondary side to the primary side in a circuit configuration of the above described type comprises on the primary side a current acquisition means as well as preferably a voltage regulation, which applies to the diode a defined voltage equal to or lower than the primary-side operating voltage.
In the presence of trouble-free operation the error status implementation of the secondary side assigned to a TOP switch sets level “high” at the cathode of the diode; during faulty operation this error status implementation has the level “low”. As long as the secondary side has a high positive offset voltage relative to the primary side (TOP switch open), no current flow can take place (diode blocked). With the TOP switch closed and the BOT switch open, or through a high-ohmic resistor parallel to the BOT switch, the secondary-side circuit for the error status implementation is pulled to ground reference potential. In this case an implemented error status on the secondary side is detected by the primary side thereby that a current flow is possible through the diode, which is now conducting.
The inventive concepts will be explained in further detail in conjunction with the embodiment examples of
In the actuation of power semiconductor components (50, 52), such as for example IGBTs (Insulated Gate Bipolar Transistor) in a circuit configuration in bridge topology, isolation of the potential is necessary due to the voltage difference between the superordinate control (10), for example in the form of a microcontroller (10), and the primary side (20) of the circuit configuration on the one hand, and the secondary side (30, 32) of the circuit configuration and the power semiconductor component (50, 52) on the other hand. According to prior art, various feasibilities for potential isolation are known, for example transformers, optocouplers, optical wave guides or electronic components with appropriate electrical strength.
In the monolithic integration of primary side and secondary side, level shifters are frequently utilized for the transmission of control signals from the primary side to the secondary side. With said components for the potential isolation, switch-on and switch-off signals can be transmitted from the primary side (low voltage side) to the secondary side (high voltage side). Essential for the trouble-free operation of an electronic power system is the primary-side information about operating states of the secondary side, for example information about the concrete switched states of the TOP and of the BOT switch or various error conditions.
Such status polling according to a signal transmission from the secondary to the primary side in the case of hybrid solutions is possible by means of transformers, bidirectional optocouplers or bidirectional optical wave guides. For monolithically integrated solutions, complementary level shifters, preferably utilizing pMOS high-voltage transistors, are known. Of disadvantage in all of said solutions is that an additional signal path with additional costs and/or additional technology expenditures has to be realized.
The secondary side (32) assigned to the BOT switch is connected to the primary side (20) without potential isolation. In the embodiment of the circuit configuration according to the invention and the associated method a circuit section of the primary side (20) monitors whether or not a current flows through the diode (60). As long as the secondary side (30) has a high positive offset voltage relative to the primary side (20), no non-transient current flow through the diode (60) can take place. Consequently, in normal operation during the switched-on phases of the TOP switch (50) no status signals can be transmitted from the secondary (20) to the primary side (30). The same applies to error conditions during which the secondary side (30) remains at high offset potential. However, if primary (20) and secondary side (30) are at an approximately equal reference potential, as is the case in the actuation mode TOP switch (50) in position “off” and BOT switch (52) in position “on”, current can flow through the diode (60). In normal operation there is cyclical passage through this state.
In integrated, or also hybrid, systems with their own secondary-side energy supply, for example via bootstrap diodes, this operating state is even compulsory and can therefore be utilized. Here the potential at the cathode-side terminal of the diode (60) is critical. If it is at the operating voltage (Vd) of the secondary side (30), no static current flow occurs at the anode-side terminal due to the dimensioning of the voltage regulation. This state signals the error-free function of the secondary side (30) for example a correctly switched-off TOP switch (50). On the other hand, if the gate driver disposed on the secondary side detects an error during the phase of a switched-on TOP switch (50), this status is locally stored and the secondary-side terminal of the diode (60) is connected to ground reference potential (Gd). In the course of the next succeeding switched-on phase of the BOT switch (52) current flows through the diode (60) and signals the detected error status of the secondary side (30) to the error acquisition means on the primary side, which means is formed as a current acquisition circuit (22), preferably with succeeding voltage regulation (24).
The resetting of the secondary-side error store can take place via the next TOP switch-on pulse, since it is only generated when the system ignores the error or interprets it as having been corrected. Voltage regulation on the primary side (20) serves for optimizing the signal-to-noise ratio between transient recharge currents and forward currents of the diode (60) due to temporary negative offset voltages with respect to the reliable signal conveyance.
In the simplest case the anode of the diode (60) is directly at the potential of the primary-side operating voltage. The acquisition of the current flow can be carried out via resistor voltage drops, coupling-out of current components or other known principles. Important is a filtering means, adapted in analogy to the level shifter, of the occurring transient recharge currents of the diode due to its coupling capacitance between secondary side (30) and primary side (20).
In addition, windowing (time phase control) of the active monitoring phases of the primary-side error acquisition onto those actuation patterns which permit a feasibility of sufficient duration for current interpretation. The structural simplicity of the circuit configuration, as well as forgoing actively switched high-voltage components, allows a robust implementation. In contrast, it has been found to be of disadvantage that the read-out phases are limited in time. Consequently, the method is not completely universal but rather only suitable for the error back transfer during the switched-out phases of the TOP switch (50). On the other hand, a feedback is consequently integratable into the system at very low expenditures.
The proposed method is generally applicable with the cyclic passing through the switched states of a bridge circuit. In the exemplary application case of an operating voltage monitoring of the secondary side (30), it must be ensured by means of the dimensioning of the capacitive blocking that, after the voltage value falls below the operating voltage threshold, it still retains an adequate value until the next switching phase. Through said circuit configuration and the associated method the error status placed locally into intermediate storage is transmitted from the secondary side to the primary side and a renewed switching-on of the TOP switch (50) in the presence of an error is consequently avoided.
Under switching conditions in which both switches are switched off, the reference potential is not defined, but rather floats, such that no reliable conveyance back can take place. To ensure the error transmission in such cases also, by means of a high-ohmic resistor (70) the AC current tapping of the bridge circuit is high-ohmically connected to ground reference potential thereby that the BOT switch is high-ohmically bridged. In the dimensioning of the resistor the cross current in regular operation must be considered. On the one hand, this current should be minimal, but, on the other hand, adequate to discharge the coupling capacitance of the entire bridge output.
| Number | Date | Country | Kind |
|---|---|---|---|
| DE102005023653.7 | May 2005 | DE | national |
