BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit device including a thin-film transistor (hereinafter abbreviated to a TFT). The present invention also relates to an active-matrix display apparatus having a circuit device including a TFT.
2. Description of the Related Art
In recent years, attention is being given to a light-emitting display apparatus using a light-emitting element as a next-generation display apparatus. In particular, a display apparatus using an organic electroluminescent (EL) element, which is a current-controlled light-emitting element whose emission luminance is controlled by a current, i.e., a so-called organic EL display apparatus, is known. One type of organic EL display apparatus is an active matrix display apparatus, which uses TFTs in a display region and a peripheral circuit and controls emission of light of organic EL elements by use of the TFTs. One known driving method used in the active-matrix display apparatus is a current programming technique of setting a current whose magnitude corresponds to image data in a pixel circuit disposed in a pixel and causing an organic EL element to emit light. The current corresponding to image data is output from a column control circuit. One example of the column control circuit is proposed in U.S. Pat. No. 7,126,565.
FIG. 12 illustrates the configuration of a column control circuit described in the above patent document. The column control circuit illustrated in FIG. 12 includes two voltage-to-current converters GMa and GMb. In operation, generally, while one of the two voltage-to-current converters GMa and GMb outputs current data, the other one samples an image signal and sets the current data. In this drawing, references M1 to M4, M6 to M10, and M12 represent n-type TFTs, references M5 and M11 represent p-type TFTs, references C1 to C4 represent capacitors, reference GND represents a first power source, and reference VCC represents a second power source. Reference Video represents an image signal, references SPa and SPb represent sampling signals, and references P1 to P6 represent control signals. The relationship between the gate sizes (width: W, length: L) in the transistors and that between the capacitances are that M1=M7, M2=M8, M3=M9, M4=M10, M5=M11, M6=M12, C1=C3, and C2=C4.
In FIG. 12, a case is described in which the channel characteristic of each TFT is specified, for example, the channel characteristic of M1 is the n type, and that of M5 is the p type. However, this is merely an example. If the relationship between the potential of the first power source GND and that of the second power source VCC is changed or the channel characteristics of the TFTs are inverted, the configuration may be changed as needed in response to the change or inversion.
For the sake of convenience of explanation in this specification, the gate electrode, source electrode, and drain electrode of a TFT are represented by the abbreviations /G, /S, and /D, respectively, and a signal and a signal line used for supplying the signal are represented without being distinguished.
FIG. 13 is a timing diagram for describing an operation of the column control circuit illustrated in FIG. 12. FIG. 13 illustrates an operation occurring in three horizontal scanning periods for an image signal, in other words, an operation corresponding to three columns (three horizontal scanning periods) for an organic EL display apparatus. Time t1 to time t7 (time t7 to time t13) corresponds to one horizontal scanning period.
The operation will be described below with reference to FIG. 13 while the attention is focused on the voltage-to-current converter GMa. The operation (1) to (6) described below is performed in sequence.
- (1) Preliminary Charging (time t1 to time t2)
M3/G is charged by M5.
- (2) Threshold Voltage Vth Resetting (time t2 to time t3)
M3/G is self-discharged such that the voltage approaches its threshold voltage Vth.
- (3) Waiting for Sampling (time t4 to time t5)
The circuit waits in a state where the voltage of M3/G is adjacent to its threshold voltage Vth until a sampling signal SPa is input. At this time, the current of M3/D is substantially zero.
- (4) Sampling (time t5 to time t6)
The sampling signal SPa for a corresponding column is generated, and the voltage of M3/G maintained adjacent to its threshold voltage Vth is changed by a transition voltage ΔV1 by an image signal level d1 with reference to a blanking level at this point in time.
- (5) Waiting for Outputting (time t6 to time t7)
The circuit waits in a state where the voltage of M3/G set by sampling of the image signal is maintained. At this time, the current of M3/D driven by the voltage of M3/G is passed from M5.
- (6) Current Outputting (time t7 to time t13)
The current of M3/D driven by the voltage of M3/G is output to Idata as current data.
After (6) (on and after time t13), the same operation is repeated from (1). The voltage-to-current converter GMb outputs a current (operation (6)) during the period from (1) to (5) (time t1 to time t7) and performs the operation (1) to (5) relating to setting of current data during the period (6) (time t7 to time t13).
As illustrated in the timing diagram of FIG. 13, this column control circuit operates with a plurality of control signals (P1 to P6) necessary for timing control. One example of the timing control is the control for causing the fall of a sampling signal SPa to occur after a fall of a control signal P1 in the period from time t3 to t4. This control is performed in order to cause M3/G to self-discharge stably by fixing a first terminal of the capacitor C1 at the potential of the image signal Video during resetting of the threshold voltage Vth. If the fall of the sampling signal SPa occurs in advance of the fall of the control signal P1, the voltage across the capacitor C1 is not changed even when the potential of M3/G is changed by self-discharging during that period. That is, the voltage of the capacitor C1 stored after the self-discharging is larger than the threshold voltage Vth of M3. To avoid this situation, it is necessary to delay the time of the fall of SPa from the time of the fall of P1. The same applies to the operation of P4 and SPb in the period from time t9 to t10 and the operation of P1 and SPa in the period from t15 to t16. No such limitation is imposed on the time of the rise of SPa and that of SPb. This is because, in the operation of preliminary charging (time t1 to time t2), if the rise of SPa is delayed from after that of P1 or P2, the preliminary charging into the capacitor C1 is not affected. One known method for delaying a signal from another signal is one that uses a delay circuit. U.S. Pat. No. 5,302,871 discloses a delay circuit in which a plurality of inverters, each including a plurality of transistors, are connected together. With the delay circuit, the time of the rise of a signal and the time of the fall of a signal are different at the input side and at the output side.
However, if a transistor, in particular, a TFT is used to control delay of a signal, because the characteristics vary, the driving characteristics of inverters or the values of capacitors vary. Because a control signal is input in parallel into column control circuits corresponding to the number of columns, the wiring for supplying the signal has a large time constant, so the signal is delayed. Therefore, when it is necessary to supply a plurality of control signals at slightly different times, a problem arises in which the times of the rises of the control signals or the times of the falls thereof may be inverted, and thus a desired operation may be unachievable.
SUMMARY OF THE INVENTION
The present invention provides a driving circuit capable of causing at least one of the rises of a plurality of control signals and the falls thereof to occur in a desired sequence without using a traditional delay circuit and also provides an active-matrix display apparatus that uses the driving circuit.
According to an aspect of the present invention, a circuit device includes a first circuit including a thin-film transistor and a second circuit including a thin-film transistor. The first circuit outputs control signals for controlling the second circuit, the control signals including a first control signal to be propagated through the second circuit and a second control signal delayed from the first control signal. The second control signal is generated on the basis of the first control signal which has been propagated through the second circuit.
According to another aspect of the present invention, an active-matrix display apparatus includes an image display unit in which pixels are arranged in a matrix in row and column directions, a column control circuit group including thin-film transistors, the column control circuit group being configured to output a data signal to columns of the pixels, and a control-signal generating circuit including a thin-film transistor, the control-signal generating circuit being configured to output a first control signal controlling the column control circuit group. The column control circuit group is controlled by the first control signal and a second control signal delayed from the first control signal. The first control signal is generated by the control-signal generating circuit, then input into the column control circuit group, and then propagated through the column control circuit group. The second control signal is generated on the basis of the first control signal which has been propagated through the column control circuit group.
In accordance with the present invention, at least one of the rises of a plurality of control signals and the falls thereof can occur in a desired sequence without consideration of the characteristics of TFTs and time constant of wiring by generation of a control signal using another control signal propagated through a circuit including a TFT. Accordingly, fine timing control can be performed reliably, and a highly reliable driving circuit that ensures accurate operation and an active-matrix display apparatus that uses the driving circuit can be provided.
Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings).
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit configuration of a display apparatus according to a first embodiment of the present invention.
FIG. 2 illustrates one example configuration of a sampling-signal generating circuit according to the first embodiment.
FIG. 3 is a timing diagram for describing an operation of the sampling-signal generating circuit illustrated in FIG. 2.
FIG. 4 illustrates another example circuit configuration of the display apparatus according to the first embodiment.
FIG. 5 illustrates an example circuit configuration of the display apparatus according to a second embodiment of the present invention.
FIG. 6 illustrates a configuration of a column control circuit according to the second embodiment.
FIG. 7 is a timing diagram for describing an operation of the column control circuit illustrated in FIG. 6.
FIG. 8 illustrates part of a signal generating circuit according to the second embodiment.
FIG. 9 is a timing diagram for describing an operation of the part of the signal generating circuit illustrated in FIG. 8.
FIG. 10 illustrates another example circuit configuration of the display apparatus according to the second embodiment.
FIG. 11 is a block diagram that illustrates a general configuration of a digital still camera system that uses a display apparatus according to an aspect of the present invention.
FIG. 12 illustrates a configuration of a column control circuit in the related art.
FIG. 13 is a timing diagram for describing an operation of the column control circuit illustrated in FIG. 12.
DESCRIPTION OF THE EMBODIMENTS
Best mode for carrying out a display apparatus according to the present invention regarding first to third embodiments is specifically described below with reference to the accompanying drawings. The embodiments described below are applied to a driving circuit including a TFT and to an active-matrix display apparatus that uses the driving circuit and can reliably perform timing control for a control signal.
It is noted that n-type and p-type polysilicon TFTs (poly-Si TFTs) can be used as the TFTs described in the embodiments. An active-matrix organic EL display apparatus is described below by way of example, but the display apparatus of the present invention is not limited to this type. The display apparatus can be of any type as long as displaying of each pixel is controllable by a current signal.
First Embodiment
FIG. 1 illustrates a circuit configuration of a circuit device according to the present embodiment. In FIG. 1, reference numeral 1 represents an image display portion, reference numeral 2 represents a column control circuit group, reference numeral 3 represents a sampling-signal generating circuit, reference numeral 4 represents a control-signal generating circuit, reference numeral 5 represents a row control circuit, reference numeral 6 represents a scanning line (light-emitting period control line), and reference numeral 7 represents a data line. The control-signal generating circuit 4 corresponds to a first circuit included in the circuit device described in the present invention, and the column control circuit group 2 corresponds to a second circuit included in the circuit device described in the present invention.
In the image display portion 1, a plurality of pixels are arranged in a plane. The pixels are arranged in a matrix in the row and column directions within the image display portion 1. Each of the pixels has a group of organic EL elements consisting of an organic EL element emitting light for red (hereinafter referred to as an R element), that for green (hereinafter referred to as a G element), and that for blue (hereinafter referred to as a B element) to emit light for displaying an image in full color. The pixel has a pixel circuit including a TFT for each of the organic EL elements, the TFT controlling a current to be input into the organic EL element. The organic EL element has a pair of electrodes and an organic light-emitting layer disposed between the pair of electrodes. When a current supplied from the pixel circuit is passed through the organic light-emitting layer disposed between the pair of electrodes, light is emitted in accordance with the amount of the current passing through the organic light-emitting layer.
The column control circuit group 2, the sampling-signal generating circuit 3, the control-signal generating circuit 4, and the row control circuit 5 are disposed in the vicinity of the image display portion 1.
The column control circuit group 2 is a group of column control circuits, each of which outputs a data signal to a column. A column control circuit 21, which is hatched in FIG. 1, corresponds to a single column. The column control circuit 21 is the circuit illustrated in FIG. 12. Although being omitted in FIG. 1, an image signal Video is input into the column control circuit group 2, as illustrated in FIG. 12. A current data Idata (data signal) is output from each output terminal to each column in the image display portion 1. The current data (data signal) is input via the data line 7 into a corresponding pixel circuit in the image display portion 1. The configuration and operation of the column control circuit 21 are substantially the same as in those previously described with reference to FIG. 12. The timing diagram of the operation is also substantially the same as in FIG. 13.
Referring back to FIG. 1, the control-signal generating circuit 4 outputs control signals (P1 to P6) having the waveforms illustrated in FIG. 13 and inputs them into the column control circuit group 2. The control signals P1 to P6 correspond to a first control signal for the circuit device according to the present invention. When the organic EL elements for three colors R, G, and B constitute a single pixel and pixels are arranged in m columns in the image display portion 1, i.e., m pixels are arranged in the horizontal direction of the drawing (row direction), because one column control circuit 21 is provided for each column, the total number of the column control circuits 21 arranged is n (n=3 m). The image signal Video is input into the column control circuit group 2 as a parallel signal for three columns in total (one for each of R, G, and B). Therefore, the sampling signal is common to the three column control circuits 21 for RGB. The sampling-signal generating circuit 3 has m output terminals, one for each of parts 31. The sampling signal is supplied from one output terminal to the three column control circuits 21. The control signals (P1 to P6) are generated by the control-signal generating circuit 4 in synchronization with each other and are input into the n column control circuits 21 so as to be common thereto. That is, after the control signals (P1 to P6) are output from the control-signal generating circuit 4, they are propagated from the nearest column control circuit toward the farthest column control circuit (in FIG. 1, from right to left) while being delayed.
The control signals P1 and P4 are propagated through the farthest column control circuit 21 (in FIG. 1, the column control circuit 21 at the leftmost side in the drawing) and then input into one terminal of the sampling-signal generating circuit 3 through routed signal lines. The control signals P1 and P4 after passing through the routed signal lines are represented by control signals P1r and P4r.
FIG. 2 illustrates one example configuration of the sampling-signal generating circuit 3. The part 31 corresponding to one output terminal of the sampling-signal generating circuit 3, the part 31 being surrounded by broken lines in FIG. 2, includes a flip-flop 10, a NOT gate (inverter) 12, two AND gates 13, and two OR gates 14. The output of the flip-flop 10 is connected as the input of the following stage. The flip-flops 10 constitute a shift register 11. In the sampling-signal generating circuit 3, the shift register 11 outputs Q1 to Qm, P1, P4, P1r, P4r, and P7 by transferring a start pulse SP with a clock CLK, and these outputs are input into the logic circuit constituted by the NOT gate 12, the AND gates 13, and the OR gates 14. The logic circuit outputs the sampling signals SPa (SPa1 to SPam) and SPb (SPb1 to SPbm). In the present embodiment, the sampling signals SPa (SPa1 to SPam) and SPb (SPb1 to SPbm) correspond to a second control signal in the circuit device according to the present invention. The control signal P7 is the signal for controlling the sampling signals SPa and SPb such that they are alternately output for each one horizontal scanning period for an image signal.
FIG. 3 is a timing diagram that illustrates an operation of the sampling-signal generating circuit 3 illustrated in FIG. 2. In FIG. 3, (a) to (k) represent the waveforms at the nodes of the symbols illustrated in FIG. 2. (a) represents the waveform of SPa (SPa1 to SPam are referred to collectively as SPa), (b) represents that of P1, (c) represents that of P1r, (d) represents that of A, (e) represents that of B (B1 to Bm are referred to collectively as B), (f) represents that of SPb (SPb1 to SPbm are referred to collectively as SPb), (g) represents that of P4, (h) represents that of P4r, (i) represents that of C, (j) represents that of D (D1 to Dm are referred to collectively as D), and (k) represents that of P7. Because the signals (c) P1r and (h) P4r have been propagated through the n column control circuits, the rise and the fall in their waveforms are less steep, and the signals (c) P1r and (h) P4r are delayed from the signals (b) P1 and (g) P4. Therefore, the edges of the fall in the waveforms (d) A and (i) C occur after those in the waveforms (b) P1 and (g) P4.
In such a way, the edge of the fall of (c) P1r, which is the signal in which the fall of (b) P1 has been reliably propagated through all of the n column control circuits, causes the edge E2 of the fall of (a) SPa to occur. Therefore, it is ensured that the edge E2 of the fall in (a) SPa occurs after the edge E1 of the fall in (b) P1 in all of the n column control circuits. Additionally, the edge of the fall of (h) P4r, which is the control in which the fall of (g) P4 has been reliably propagated through all of the n column control circuits, causes the edge E4 of the fall of (f) SPb to occur. Therefore, it is ensured that the edge E4 of the fall in (f) SPb occurs after the edge E3 of the fall in (g) P4 in all of the n column control circuits. Referring back to FIG. 1, a part 41 surrounded by broken lines, i.e., three column control circuits constituting a single set for RGB among the column control circuit group 2 and one stage of the sampling-signal generating circuit 3 can be collectively considered as a partial circuit 41. The total number of the partial circuits 41 is m. The partial circuit 41 constitutes a single circuit column. The control signals P1 to P6 and P1r and P4r are common to the partial circuits 41 and connected to the partial circuits 41 with their respective pieces of wiring. The partial circuits 41 operate in conjunction with each other by serving as a shift register sequentially transmitting signals to sample the image signal Vdata and output it. The control signals P1 to P6, which is part of the control signals, are generated by the control-signal generating circuit 4 in synchronization with each other and connected to first ends of the pieces of wiring horizontally crossing the circuit columns. The delayed control signals P1r and P4r are also connected to the same first ends. In the foregoing, the driving circuit for use in the display apparatus is described as the circuit device. However, the present invention is not limited to this. The present invention is also applicable to a case in which, in a circuit device that includes collectively operating first and second circuits, similar to the column control circuit group 2 and the sampling-signal generating circuit 3 in the present embodiment, part of control signals of the second circuit is input so as to be delayed from the other control signals. As described above, in the present invention, in circuit operation, a control signal to be input in advance is retrieved from the circuit farthest from the signal input terminal, and a control signal to be input so as to be delayed is generated by use of the retrieved control signal as its input. Therefore, malfunction of each circuit can be reduced, and stable operation is achieved.
FIG. 4 illustrates another example configuration of the circuit device according to the present embodiment. FIG. 4 differs from FIG. 1 in the routing of inputting the control signals P1r and P4r into the sampling-signal generating circuit 3. In FIG. 1, the signal line is routed between the column control circuit group 2 and the sampling-signal generating circuit 3. In this region, the sampling signals SPa and SPb and the image signal Video (not shown) are arranged. Therefore, these signal lines intersect many of the other signal lines, so parasitic impedance is increased. In contrast, in FIG. 4, the signal lines are routed outside the sampling-signal generating circuit 3, i.e., in a more outer region in the display apparatus. This can reduce the intersection with the other signal lines. Therefore, interference in between the signal lines can be reduced. In the circuit configuration illustrated in FIG. 1, because the signal lines can be highly integrated, the size of the region surrounding the image display portion (picture-frame region) can be reduced. As a result, it is advantageous for miniaturization of the display apparatus.
Second Embodiment
The present embodiment is an active-matrix display apparatus including a circuit device similar to that in the first embodiment. FIG. 5 illustrates a circuit configuration of the present embodiment. In FIG. 5, reference numeral 2A represents a column control circuit group, reference numeral 3A represents a sampling-signal generating circuit, and reference numeral 4A represents a control-signal generating circuit. The control-signal generating circuit 4A corresponds to a first circuit, and the column control circuit group 2A corresponds to a second circuit.
The present embodiment is substantially the same as the first embodiment except that it includes the column control circuit group 2A, the sampling-signal generating circuit 3A, and the control-signal generating circuit 4A in place of the column control circuit group 2, the sampling-signal generating circuit 3, and the control-signal generating circuit 4, respectively.
FIG. 6 illustrates a configuration of a column control circuit for one column in the present embodiment. The column control circuit illustrated in FIG. 6 includes two voltage-to-current converters GMa2 and GMb2. In operation, generally, while one of the two voltage-to-current converters GMa2 and GMb2 outputs current data, the other one samples an image signal and sets the current data. In FIG. 6, references M1a to M4a, M6a, M7a, M1b to M4b, M6b, and M7b represent n-type TFTs, references M5a and M5b represent p-type TFTs, references C1a, C2a, C1b, and C2b represent capacitors, reference GND represents a first power source, and reference VCC represents a second power source. Reference Video represents an image signal, references SPa and SPb represent sampling signals, and references P1A to P4A and P1B to P4B represent control signals. The relationship between the gate sizes (width: W, length: L) in the transistors and that between the capacitances are that M1a=M1b, M2a=M2b, M3a=M3b, M4a=M4b, M5a=M5b, M6a=M6b, M7a=M7b, C1a=C1b, and C2a=C2b.
In FIG. 6, a case in which the channel characteristic of each TFT is specified, for example, the channel characteristic of M1a is the n type, and that of M5a is the p type is described. However, this is merely an example. If the relationship between the potential of the first power source GND and that of the second power source VCC is changed or the channel characteristics of the TFTs are inverted, the configuration may be changed as needed in response to the change or inversion.
FIG. 7 is a timing diagram for describing an operation of the column control circuit illustrated in FIG. 6. FIG. 7 illustrates an operation occurring in three horizontal scanning periods for an image signal, in other words, an operation corresponding to three columns (three horizontal scanning periods) for an organic EL display apparatus. Time t1 to time t6 (time t6 to time t11) correspond to one horizontal scanning period.
The operation will be described below with reference to FIG. 7 while the attention is focused on the voltage-to-current converter GMa2. The operation (1) to (6) described below is performed in sequence.
- (1) Preliminary Charging (time t1 to time t2)
C2a is charged by M2a.
- (2) Threshold Voltage Vth Resetting (time t2 to time t3)
M5a is self-discharged such that the voltage between the gate and the source (G-S voltage) approaches its threshold voltage Vth.
- (3) Waiting for Sampling (time t3 to time t4)
The circuit waits in a state where the G-S voltage of M5a is adjacent to its threshold voltage Vth until a sampling signal SPa is input.
- (4) Sampling (time t4 to time t5)
The sampling signal SPa for a corresponding column is generated, and the G-S voltage of M5a maintained adjacent to its threshold voltage Vth is changed by an image signal level d1 with reference to a blanking level at this point in time.
- (5) Waiting for Outputting (time t5 to time t6)
The circuit waits in a state where the G-S voltage of M5a set by sampling of the image signal is maintained.
- (6) Current Outputting (time t6 to time t11)
The current of M5a/D driven by the G-S voltage of M5a is output to Idata as current data.
After (6) (on and after time t11), the same operation is repeated from (1). The voltage-to-current converter GMb2 outputs a current (operation (6)) during the period from (1) to (5) (time t1 to time t6) and performs the operation (1) to (5) relating to setting of current data during the period (6) (time t6 to time t11).
One example of the timing control in this operation for the column control circuit is control of causing the edge of the rise of the control signal P3A and that of P4A to occur after the edge of the fall of P2A at time t6. This control is performed for stable operation of outputting a current with the G-S voltage of M5a set by sampling of an image signal by turning-on of M6a and M7a after turning-off M4a (the same applies to the operation at time t11). That is, in the present embodiment, the control signals P2A and P2B correspond to a first control signal for a driving circuit according to the present invention, and the control signals P3A, P4A, P3B, and P4B correspond to a second control signal for the driving circuit according to the present invention.
In FIG. 5, the control-signal generating circuit 4A outputs the control signals (P1A to P4A and P1B to P4B) having the waveforms illustrated in FIG. 7 and inputs them into the column control circuit group 2A. When the pixels are arranged in n columns, n column control circuits are arranged. The control signals (P1A to P4A and P1B to P4B) input into the n column control circuits are common thereto. After the control signals are output from the control-signal generating circuit 4A, the signals are propagated from the nearest column control circuit toward the farthest column control circuit (from right to left in FIG. 5).
After the control signals P2A and P2B are propagated to the farthest column control circuit (in FIG. 5, the column control circuit at the leftmost side of the column control circuit group 2A), these control signals are returned to the control-signal generating circuit 4A through the routed signal lines. The control signals P2A and P2B after passing through the routed signal lines are represented by control signals P2Ar and P2Br.
FIG. 8 illustrates one example of part of the control-signal generating circuit 4A. Each of the control signals P2A, P2B, P2Ar, and P2Br is input into the logic circuit constituted by the inverter 12 and the OR gate 14. The logic circuit outputs the control signals P3A, P4A, P3B, and P4B. The control signals P5A and P5B are used for generating the control signals P4A and P4B.
FIG. 9 is a timing diagram that illustrates an operation of the part of the control-signal generating circuit 4A illustrated in FIG. 8. In FIG. 9, (a) to (j) represent the waveforms at the nodes of the symbols illustrated in FIG. 8. (a) represents the waveform of P2A, (b) represents that of P2Ar, (c) represents that of P3A, (d) represents that of P4A, (e) represents that of P5A, (f) represents that of P2B, (g) represents that of P2Br, (h) represents that of P3B, (i) represents that of P4B, and (j) represents that of P5B. The waveforms of (e) P5A and (j) P5B are not limited to those illustrated in FIG. 9. They may have any form as long as they can generate the H level of P4A during the period from time t2 to time t3 illustrated in FIG. 7 and during the period from t12 to time t13 and the H level of P4B during the period from time t7 to time t8. Because the signals (b) P2Ar and (g) P2Br have been propagated through the n column control circuits, the rise and the fall in their waveforms are less steep, and the signals (b) P2Ar and (g) P2Br are delayed from the signals (a) P2A and (f) P2B.
In such a way, the edge of the fall of (b) P2Ar, which is the signal in which the fall of (a) P2A has been reliably propagated through all of the n column control circuits, causes the edge of the rise of (c) P3A and that of (d) P4A to occur. Therefore, it is ensured that the edge E6 of the rise in (c) P3A and that in (d) P4A occurs after the edge E5 of the fall in (a) P2A in all of the n column control circuits. Additionally, the edge of the fall in (g) P2Br, which is the control in which the fall of (f) P2B has been reliably propagated through all of the n column control circuits, causes the edge of the rise in (h) P3B and that in (i) P4B to occur. Therefore, it is ensured that the edge E8 of the rise in (h) P3B and that in (i) P4B occurs after the edge E7 of the fall in (f) P2B in all of the n column control circuits.
FIG. 10 illustrates another circuit configuration of the display apparatus according to the present embodiment. FIG. 10 differs from FIG. 5 in the routing in which the control signals P2Ar and P2Br are input into the control-signal generating circuit 4A. In FIG. 5, the signal lines are routed between the column control circuit group 2A and the sampling-signal generating circuit 3A, and in this region, the sampling signals SPa and SPb and the image signal Video (not shown) are arranged. Therefore, these signal lines intersect many of the other signal lines, so parasitic impedance is increased. In contrast, in FIG. 10, the signal lines are routed outside the sampling-signal generating circuit 3A, i.e., in a more outer region in the display apparatus. This can reduce the intersection with the other signal lines. Therefore, interference in between the signal lines can be reduced. In the circuit configuration illustrated in FIG. 5, because the signal lines can be highly integrated, the size of the region surrounding the image display portion (picture-frame region) can be reduced. As a result, it is advantageous for miniaturization of the display apparatus.
The above-described embodiments are applicable to an electronic apparatus.
FIG. 11 is a block diagram that illustrates one example of a digital still camera system to which at least one of the above-described embodiments is applied. In this drawing, reference numeral 50 represents a digital still camera system, reference numeral 51 represents an image capturing portion, reference numeral 52 represents an image-signal processing circuit, reference numeral 53 represents a display panel, reference numeral 54 represents a memory, reference numeral 55 represents a central processing unit (CPU), and reference numeral 56 represents an operating portion.
In FIG. 11, an image captured by the image capturing portion 51 or an image recorded on the memory 54 can be signal-processed by the image-signal processing circuit 52 and can be displayed on the display panel 53. The CPU 55 controls the image capturing portion 51, the memory 54, the image-signal processing circuit 52, and other components in response to input from the operating portion 56 and performs imaging, recording, reproducing, and displaying as circumstances demand. The display panel 53 can also be used as a display portion of other electronic apparatuses.
The driving circuit and the display apparatus using the driving circuit according to the embodiments of the present invention are described above. The present invention relates to a driving circuit including a TFT and to an active-matrix display apparatus using the driving circuit. In particular, the present invention is applicable to an active-matrix display apparatus using organic EL elements. An information processing apparatus can be constructed by the use of this display apparatus, for example. The display apparatus is applicable to, for example, a television system, a personal computer, a cellular phone, a personal digital assistant (PDA), a still camera, a video camera, a camcorder, a portable music player, and a car navigation system. The display apparatus is also applicable to an apparatus achieving a plurality of functions of theses apparatuses. The information processing apparatus includes an information input portion. For example, in the case of a cellular phone, the information input portion includes an antenna. In the case of a PDA or a portable PC, the information input portion includes an interface portion to a network. In the case of a digital camera or a camcorder, the information input portion includes a sensor portion composed of a charge-coupled device (CCD) or complementary metal-oxide semiconductor (CMOS).
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all modifications and equivalent structures and functions.
This application claims the benefit of Japanese Application No. 2007-280441 filed Oct. 29, 2007, which is hereby incorporated by reference herein in its entirety.
Patent Grant
8339336
