Patent Grant
11468827
The present application is based on, and claims priority from JP Application Serial Number 2020-111370, filed Jun. 29, 2020, the disclosure of which is hereby incorporated by reference herein in its entirety.
The present disclosure relates to a circuit device, an electro-optical element, an electronic apparatus, and the like.
JP 2019-132941 A and JP 2008-281827 A disclose a technique in which, in a display device using a light emitting element in a pixel, a pixel is caused to emit light by a time weighted in accordance with each bit of display data to perform grey-scale display as a time average. Additionally, J P 2019-132941 A and JP 2008-281827 A disclose a technique in which, while a plurality of scan lines are selected in order one by one from above, a first bit is written to a pixel connected to each scan line, next, similarly while a plurality of scan lines are selected in order one by one from above, a second bit is written to a pixel connected to each scan line, and these are continued until an MSB.
In JP 2019-132941 A and JP 2008-281827 A described above, a period occurs in which, while a plurality of scan lines are selected in order one by one from above, from writing a certain bit to a pixel connected to each scan line, to starting of writing a next bit, no scan line is selected. Since a length of one frame is determined by a frame rate, there is a problem in that a scan line drive frequency increases due to presence of a period in which no scan line is selected.
An aspect of the present disclosure relates to a circuit device used for an electro-optical element including a plurality of scan lines, a plurality of pixel circuits respectively corresponding to one of the plurality of scan lines, a plurality of pixels respectively corresponding to one of the plurality of pixel circuits, the electro-optical element displaying a single image in a field, the circuit device comprising, a scan line drive circuit configured to output a plurality of selection signals respectively corresponding to the plurality of scan lines; and an enable line drive circuit configured to output a plurality of enable signals respectively corresponding to the plurality of pixel circuits, wherein the field includes first to n-th scan line selection periods in which first to n-th bits of display data are supplied to a pixel circuit included in the plurality of pixel circuits, and first to n-th display periods in which a pixel of the plurality of pixels connected to the pixel circuit is ON-state or OFF-state based on the first to n-th bits supplied to the pixel circuit, n being an integer greater than or equal to 2, the field includes a plurality of subfields, the enable line drive circuit outputs the enable signal that is active in a partial period of the first display period corresponding to the first bit that is a lower bit of the display data, and when the enable signal is active in the partial period of the first display period, the pixel is ON-state or OFF-state.
Another aspect of the present disclosure relates to an electro-optical element including the circuit device described in any of the above. the plurality of scan lines, the plurality of pixels, and the plurality of pixel circuits.
Yet another aspect of the present disclosure relates to an electro-optical element that includes a plurality of scan lines, a data line, a plurality of pixel portions arranged corresponding to respective intersections of the plurality of scan lines and the data line, a scan line drive circuit configured to output a selection signal to the plurality of scan lines, and an enable line drive circuit configured to output an enable signal to the plurality of pixel portions, wherein each pixel portion of the plurality of pixel portions includes a pixel circuit that holds display data of first to n-th bits bit by bit in a predetermined order, n being an integer of 2 or greater, and a pixel that is ON-state or OFF-state based on the enable signal and the held display data, and the enable line drive circuit, in first to n-th display periods in which the pixel is ON-state or OFF-state, outputs the enable signal that is active in a partial period of the first display period corresponding to the first bit, that is a lower bit of the display data.
A further another aspect of the disclosure relates to an electronic apparatus including the circuit device described in any of the above, and the electro-optical element.
Exemplary embodiments of the present disclosure will be described in detail hereinafter. Note that, the present exemplary embodiment described hereinafter is not intended to unjustly limit the content as set forth in the claims, and all of the configurations described in the exemplary embodiment are not always essential requirements.
First, operation when focusing on one scan line will be described using a first scan line as an example. In a selection order 1, the first scan line is selected, and a first bit is written to a pixel circuit connected to the first scan line. In subsequent selection orders 2 to 10, a light emitting element of a pixel does or does not emit light based on the first bit held in the pixel circuit. When the first bit is “1”, the light emitting element emits light, and when the first bit is “0”, the light emitting element does not emit light. Similarly, the first scan line is selected in selection orders 11, 30, and 67, and a second bit, a third bit, and a fourth bit are written to the pixel circuit connected to the first scan line. In subsequent selection orders 12 to 29, 31 to 66, 68 to 139, the light emitting element of the pixel does or does not emit light based on the second bit, the third bit, and the fourth bit held in the pixel circuit.
A period in which a light emitting element of a pixel does or does not emit light will be referred to as a display period. There are first to fourth display periods corresponding to the first to fourth bits. A period for one selection order is a period in which one scan line is selected. Hereinafter, this period is referred to as a scan line selection period, and a length of the period is h. The first to fourth display periods are 9 h, 18 h, 36 h, and 72 h respectively, and are weighted according to grey-scale values of the bits. Since a grey-scale value of an i-th bit is 2i-1, a display period is weighted with 2i-1. As a result, when viewed as a time average, a pixel emits light at brightness corresponding to the grey-scale value. Note that, when display data contains n bits, i is from 1 to n, and n=4 here.
Next, operation when 10 scan lines are scanned will be described. An FRB is a field, and one field constitutes one frame. That is, the field FRB is a period for causing one image to be displayed, and is a period required to write display data corresponding to one image to all pixels. The field FRB includes a subfields SFB1 to SFB4 corresponding to first to fourth bits of display data.
In selection orders 1 to 10 for the subfield SFB1, first to 10th scan lines are sequentially selected, and the first bit is written to a pixel circuit connected to each scan line. Next, in selection orders 11 to 20 for the subfield SFB2, the first to 10th scan lines are sequentially selected, and the second bit is written to the pixel circuit connected to each scan line. In selection orders 21 to 29 for the subfield SFB2, no scan line is selected. Next, in selection orders 30 to 39 for the subfield SFB3, the first to 10th scan lines are sequentially selected, and the third bit is written to the pixel circuit connected to each scan line. In selection orders 40 to 66 for the subfield SFB3, no scan line is selected. Next, in selection orders 67 to 76 for the subfield SFB4, the first to 10th scan lines are sequentially selected, and the fourth bit is written to the pixel circuit connected to each scan line. In selection orders 77 to 139 for the subfield SFB4, no scan line is selected.
When the total number of scan lines for one screen is k, a length of each of the scanning periods TW1 to TW4 is kh. When k is a number sufficiently greater than the number of bits of 4, lengths of the subfields SFB2, SFW3, and SFB4 can be approximated as 2 kh, 4 kh, and 8 kh respectively, and a length of the field FRB can be approximated as (1+2+4+8)×kh=15 kh. At this time, a total scanning period is 4 kh, and a total non-scanning period is 11 kh, so respective ratios occupying in the field are 4/15 and 11/15.
In the above description, the display data contains four bits, but, for example, when the display data contains six bits, a ratio occupied by a scanning period in the field is 6/63, and a ratio occupied by a non-scanning period in the field is 57/63. Since a length of a field is determined by a frame frequency of display, the more the number of bits of display data, the shorter a scanning period of a scan line, and the shorter the length h of a scan line selection period in which one scan line is selected. Further, when the number of scan lines is increased, since a scanning period is shortened, and more scan lines are to be selected within the scanning period, the length h of a scan line selection period in which one scan line is selected is shortened.
As described above, since the non-scanning periods NW2 to NW4 are present in the field FRB in the technique in the past, there is a problem in that the length h of a scan line selection period is shortened, and a drive frequency of a scan line is raised. There is a problem in that, when the drive frequency of a scan line is raised, power consumption of scan line drive increases, or it becomes difficult to increase the number of scan lines or the number of grey scales.
Note that, accurately, respective lengths of the non-scanning periods NW2, NW3, and NW4 are (k−1)h, 3(k−1)h, and 7(k−1)h, and the length of the field FRB is 4 kh+11(k−1)h=(15(k−1)+4)h. When display data contains n bits, the length of the field FRB is ((2n−1)×(k−1)+n)h. As an example, when 256 grey-scale display is performed at a frame frequency of 60 Hz in full high vision, k=1080 and n=8. Accordingly, the length of the scan line selection period is h=1/((28−1)×(1080−1)+8)/60 sec=0.06 μsec.
The display controller 60 outputs display data to the circuit device 100, and performs display timing control. The display controller 60 includes a display signal supply circuit 61 and a VRAM circuit 62.
The VRAM circuit 62 stores display data to be displayed on the pixel array 20. For example, when storing image data for one image, the VRAM circuit 62 stores display data one at a time corresponding to each pixel of the pixel array 20.
The display signal supply circuit 61 generates a control signal for controlling display timing. The control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, or the like. The display signal supply circuit 61 reads display data from the VRAM circuit 62 in accordance with display timing, and outputs the display data and a control signal to the circuit device 100.
The circuit device 100 drives the pixel array 20 based on the display data and the control signal from the display controller 60 to cause the pixel array 20 to display an image. The circuit device 100 includes a scan line drive circuit 110, a data line drive circuit 120, and an enable line drive circuit 130.
The pixel array 20 is a pixel array of an electro-optical element, and includes a plurality of pixel portions 30 arranged in a matrix of k rows and m columns. k and m are each an integer equal to or greater than 2. The pixel portion 30 includes a pixel circuit and a pixel as described below. The pixel array 20 includes scan lines LSC1 to LSCk, inversion scan lines LXSC1 to LXSCk, enable data lines LEN1 to LENk, image data lines LDT1 to LDTm, power source lines LVD1, LVD2, and a ground line LVS.
The scan line LSC1, the inversion scan line LXSC1, and the enable data line LEN1 are connected to the pixel portions 30 in a first row. The scan line drive circuit 110 outputs a selection signal SC1 to the scan line LSC1, and outputs an inversion selection signal XSC1, which is a logic inversion signal of the selection signal SC1, to the inversion scan line LXSC1. The enable line drive circuit 130 outputs an enable signal EN1 to the enable data line LEN1. Similarly, the scan lines LSC2 to LSCk, the inversion scan lines LXSC2 to LXSCk, and the enable data lines LEN2 to LENk are connected to the pixel portions 30 in the second to k-th rows respectively. The scan line drive circuit 110 outputs selection signals SC2 to SCk to the scan lines LSC2 to LSCk respectively, and outputs inversion selection signals XSC2 to XSCk, which are the logic inversion signals of the selection signals SC2 to SCk respectively, to the inversion scan lines LXSC2 to LXSCk respectively. The enable line drive circuit 130 outputs enable signals EN2 to ENk to the enable data lines LEN2 to LENk respectively.
The image data line LDT1 is connected to the pixel portions 30 in the first row. The data line drive circuit 120 outputs an image signal DT1 to the image data line LDT1. The image signal DT1 is a signal of any one of n bits of display data. Similarly, the image data lines LDT2 to LDTm are connected to the pixel portions 30 in the second to m-th rows respectively. The data line drive circuit 120 outputs image signals DT2 to DTm to the image data lines LDT2 to LDTm respectively.
The power source lines LVD1, LVD2, and the ground line LVS are connected to all of the pixel portions 30. A first supply voltage VDD1 is supplied to the power source line LVD1 from a power supply circuit (not illustrated). A second supply voltage VDD2 is supplied to the power source line LVD2 from a power supply circuit (not illustrated). A ground voltage VSS is supplied to the ground line LVS from a power supply circuit (not illustrated). Note that, the power source lines LDV1 and LVD2 may be one common power source line, and a common power supply voltage may be supplied to the power source line.
The pixel 31 is a light emitting element. The light emitting element is, for example, an OLED, a micro LED, or the like. OLED is an abbreviation for Organic Light Emitting Diode, and LED is an abbreviation for Light Emitting Diode. Micro LEDs are inorganic LEDs integrated on a substrate. An anode of the light emitting element is connected to the power source line LVD2, and a cathode is connected to a pixel control node NID of the pixel circuit 32. The pixel 31 is controlled to be ON-state or OFF-state by the pixel circuit 32. Here, ON means that the light emitting element is in a light emitting state due to a current ID flowing to the light emitting element, and OFF means that the light emitting element is in a non-emitting state due to no current ID flowing to the light emitting element.
The pixel circuit 32 holds a bit of display data, which is an image signal DT, and controls the pixel 31 to be ON-state or OFF-state based on the image signal DT and an enable signal EN. The pixel circuit 32 includes a memory circuit 33 and N-type transistors TA, TB1, and TB2.
One of a source and a drain of the N-type transistor TA is connected to the image data line LDT, another of the source and the drain is connected to an input node NI of the memory circuit 33, and a gate is connected to a scan line LSC.
A source of the N-type transistor TB1 is connected to the ground line LVS, a drain is connected to a source of the N-type transistor TB2, and a gate is connected to an output node NQ of the memory circuit 33.
A drain of the N-type transistor TB2 is connected to the pixel control node NID of the pixel circuit 32, and a gate is connected to an enable data line LEN.
The memory circuit 33 is a memory cell that stores one bit of data. The memory circuit 33 stores the image signal DT inputted to the input node NI from the image data line LDT when the N-type transistor TA is ON-state, and outputs the stored signal to the output node NQ as an output signal MCQ. The memory circuit 33 includes P-type transistors TC1, TC3, N-type transistors TC2, TC4, and TC5. Note that, the N-type transistor TC5 may be constituted by a P-type transistor. In this case, it is possible to connect to the scan line LSC, and an inversion scan line LXSC can be omitted.
The P-type transistor TC1 and the N-type transistor TC2 constitute a first inverter, and the P-type transistor TC3 and the N-type transistor TC4 constitute a second inverter. A power supply voltage of the first inverter and the second inverter is VDD1. An input node of the first inverter is connected to the input node NI of the memory circuit 33, an output node NC of the first inverter is connected to an input node of the second inverter, and an output node of the second inverter is connected to the output node NQ of the memory circuit 33. One of a source and a drain of the N-type transistor TC5 is connected to the input node NI, and another of the source and the drain is connected to the output node NQ.
When “1” is written to the memory circuit 33, the output signal MCQ is at a high level, and when “0” is written, the output signal MCQ is at a low level. When the output signal MCQ of the memory circuit 33 and the enable signal EN are at the high level, the N-type transistors TB1 and TB2 are ON, the current ID flows to the pixel 31, and the pixel 31 emits light. When at least one of the output signal MCQ of the memory circuit 33 and the enable signal EN is at the low level, at least one of the N-type transistors TB1 and TB2 is OFF-state, the current ID does not flow to the pixel 31, and the pixel 31 does not emit light.
Note that, the configuration of
In a scan line selection period TS1, a selection signal SC is at a high level, and an inversion selection signal XSC is at a low level. The N-type transistor TA is ON-state, and the N-type transistor TC5 is OFF-state. As a result, the first bit DT[0]=1 is inputted to the memory circuit 33 as the image signal DT, and the memory circuit 33 outputs the output signal MCQ at the high level. The enable signal EN is at the low level, and the pixel 31 is OFF-state in the scan line selection period TS1.
In a display period TD1, the selection signal SC is at the low level, and the inversion selection signal XSC is at the high level. The N-type transistor TA is OFF-state, and the N-type transistor TC5 is ON-state. As a result, the memory circuit 33 holds the first bit DT[0]=1, and holds the output signal MCQ at the high level.
In a period TE, which is ¼ of the display period TD1, the enable signal EN is at the high level, and the pixel 31 is ON-state in the period TE. In the remaining ¾ period of the display period TD1, the enable signal EN is at the low level, and the pixel 31 is OFF-state in that period. In this way, a grey scale can be controlled using the enable signal EN without changing a length of the display period. In the example illustrated in
In a scan line selection period TS3, the selection signal SC is at the high level, and the inversion selection signal XSC is at a low level. The N-type transistor TA is ON-state, and the N-type transistor TC5 is OFF-state. As a result, the third bit DT[2]=1 is inputted to the memory circuit 33 as the image signal DT, and the memory circuit 33 outputs the output signal MCQ at the high level. The enable signal EN is at the low level, and the pixel 31 is OFF-state in the scan line selection period TS3.
In a display period TD3, the selection signal SC is at the low level, and the inversion selection signal XSC is at the high level. The N-type transistor TA is OFF-state, and the N-type transistor TC5 is ON-state. As a result, the memory circuit 33 holds the third bit DT[2]=1 and holds the output signal MCQ at the high level. The enable signal EN is at the high level, and the pixel 31 is ON-state in the display period TD3.
The pixel portion 30 operates in the same manner as described above also in a scan line selection period TS4 and a display period TD4, but the fourth bit DT[3]=0, and thus the pixel 31 is OFF-state in the display period TD4. A length of the display period TD4 is twice a length of the display period TD3, and lengths of the display periods TD3 and TD4 are lengths proportional to grey-scale values of the third bit and the fourth bit respectively.
Note that,
First, operation when focusing on one scan line will be described using a first scan line as an example. In a selection order 1, a first scan line is selected, and a first bit is written to the first scan line. In subsequent selection orders 2 to 10, a pixel is ON-state or OFF-state based on the first bit held in a pixel circuit. At this time, the enable line drive circuit 130 outputs an enable signal such that the pixel is ON-state or OFF-state in a period that is ½ of a display period. Next, the first scan line is selected in a selection order 11, and a second bit is written to the first scan line. In subsequent selection orders 11 to 20, the pixel is ON-state or OFF-state based on the second bit held in the pixel circuit. At this time, the enable line drive circuit 130 outputs an enable signal such that the pixel is ON-state or OFF-state throughout the display period. Similarly, the first scan line is selected in selection orders 21, 40, 77, and, a third bit, a fourth bit, and a fifth bit are written to the first scan line. In subsequent selection orders 22 to 39, 41 to 76, 78 to 149, the pixel is ON-state or OFF-state based on the third bit, the fourth bit, and the fifth bit held in the pixel circuit.
Next, operation when 10 scan lines are scanned will be described. An FRA is a field, and the field FRA includes subfields SFA1 to SFA5 corresponding to first to fifth bits of display data.
In selection orders 1 to 10 of the subfield SFA1, first to 10th scan lines are sequentially selected, and the first bit is written to a pixel circuit connected to each scan line. Next, in selection orders 11 to 20 of the subfield SFA2, the first to 10th scan lines are sequentially selected, and the second bit is written to the pixel circuit connected to each scan line. In selection order 21 to 30 of the subfield SFA3, the first to 10th scan lines are sequentially selected, and the third bit is written to the pixel circuit connected to each scan line. In selection orders 31 to 39 of the subfield SFA3, no scan line is selected. Next, in selection orders 40 to 49 of the subfield SFA4, the first to 10th scan lines are sequentially selected, and the fourth bit is written to the pixel circuit connected to each scan line. In selection orders 50 to 76 of the subfield SFA4, no scan line is selected. Next, in selection orders 77 to 86 of the subfield SFA5, the first to 10th scan lines are sequentially selected, and the fifth bit is written to the pixel circuit connected to each scan line. In selection orders 87 to 149 of the subfield SFA5, no scan line is selected.
In the first example of
As illustrated in
First, operation when focusing on one scan line will be described using a first scan line as an example. In a selection order 1, a first scan line is selected, and a first bit is written to the first scan line. In subsequent selection orders 2 to 7, a pixel is ON-state or OFF-state based on the first bit held in a pixel circuit. Similarly, the first scan line is selected in selection orders 8, 15, 22, 35, and 60, and a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit are written to the first scan line. In subsequent selection orders 9 to 14, 16 to 21, 36 to 59, 61 to 108, the pixel is ON-state or OFF-state based on the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit held in the pixel circuit.
In the above, first to sixth scan line selection periods and first to sixth display periods are provided corresponding to the first to sixth bits in one field respectively. In the first scan line, the first to sixth scan line selection periods are periods corresponding to the selection orders 1, 8, 15, 22, 35, and 60, respectively, and the first to sixth display periods are periods corresponding to the selection orders 2 to 7, 9 to 14, 16 to 21, 36 to 59, and 61 to 108, respectively. Respective lengths of the first to third display periods are the same 6 h, and lengths of the fourth to sixth display periods are 12 h, 24 h, and 48 h, respectively. The enable line drive circuit 130 outputs an enable signal such that the pixel is ON-state or OFF-state in periods that are ¼ and ½ of the first and second display periods respectively. Further, the enable line drive circuit 130 outputs an enable signal such that the pixel is ON-state or OFF-state in all of the third to sixth display periods. Which selection order corresponds to the scan line selection period and the display period varies for each scan line, but the first to sixth scan line selection periods and the first to sixth display periods are similarly provided for each scan line.
Next, operation when 18 scan lines are scanned will be described. An FR is a field, and one field constitutes one frame. That is, the field FR is a period for constituting one image, and is a period required to write display data corresponding to one image to all pixels. Note that, the same field FR is defined for all scan lines based on selection orders in any one scan line. For example, in
The field FR includes the same number of subfields SF1 to SF18 as the number of scan lines k=18. When display data contains n bits, and the number of bits whose grey-scale values are less than 1 is R, the number of subfields is 2n-β+β. In
The scan line drive circuit 110 selects a scan line group to be selected among the first to the 18th scan lines in each subfield. In
The six scan lines belonging to the scan line group are selected in different selection orders respectively. In the subfield SF1 of
When the subfield is advanced by one, the number of the scan line belonging to the scan line group is decreased by one. In other words, a selection order pattern in the subfield moves by one scan line in an upward direction on a screen. This pattern movement of is performed cyclically. In other words, the selection order pattern of the first scan line in a certain subfield is a selection pattern of the 18th scan line in the next subfield. For example, in the subfield SF2, the 18th scan line, the first scan line, the second scan line, the third scan line, the fifth scan line, and the ninth scan line form a scan line group, and the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit are written to the scan lines respectively. In this case, the selection order pattern in the subfield SF1 moves upward by one scan line in a cyclic manner.
In the subfield SF1, the second bit is written to a scan line one line after the scan line to which the first bit is written. Similarly, the third bit, the fourth bit, the fifth bit, and the sixth bit are written to scan lines one line after, one line after, two lines after, four lines after the scan lines to which the second bit, the third bit, the fourth bit, and the fifth bit are written respectively. In the next subfield SF2, the first bit is written to the 18th scan line, but this is eight lines after the 10th scan line. As a result, the first to sixth display periods have lengths corresponding to the grey-scale values. Specifically, when a grey-scale value is 1 or less, a length of a display period is the same, and when a grey-scale value is 1 or greater, a length of a display period is proportional to the grey-scale value.
A description will be given focusing on a display period in the first scan line. First, the second bit is written to the second scan line in the selection order 2, but the selection order pattern moves to the first scan line after one subfield. Since the length of the subfield is 6 h, and the first display period of the first scan line starts from the selection order 2, the length of the first display period is 1×6 h. For similar reasons, the length of the second and third display periods is also 1×6 h. Next, the fifth bit is written to the sixth scan line in the selection order 5, but this selection order pattern moves to the fourth scan line after two subfields. Since the fourth display period of the fourth scan line starts from the selection order 5, the length of the fourth display period is 2×6 h=12 h. Similarly, the length of the fifth display period is 4×6 h, and the length of the sixth display period is 8×6 h.
Since the total number of scan lines is 18, and wiring 6 bits is required per scan line, the total number of scan line selections in one field is 18×6=108. In
The scan line drive circuit 110 selects the scan lines in the selection order pattern as described above, thus the selection orders in which no scan line is selected can be reduced. In other words, the non-scanning periods NW2 to NW4 in the technique in the past illustrated in
As an example, when 256 grey-scale display is performed at a frame frequency of 60 Hz in full high vision, n=8. β=2, and the number of scan lines is set to 16×(28-2+2)=1088. A method in which the number of scan lines is increased from 2n-β+β will be described later, but the basic idea of the scan line selection order is the same as in the second example. The length of the scan line selection period is h=1/(1088×8)/60 sec=1.91 μsec. Since h=0.06 μsec in the technique in the past illustrated in
If the grey-scale control by the enable signal is not performed, the length of each of the first to n-th display periods is weighted by a power of two. Therefore, the number of scan line selections in one field is 2n×n, and is greater than the number of scan line selections in the second example (2n-β+β)×n. When the example of the full high vision described above is applied when the grey-scale control by the enable signal is not performed, h=1/(5×28×8)/60=1.63 μsec, and the scan line drive frequency is lower in the second example.
According to the above-described present exemplary embodiment, the enable line drive circuit 130 outputs an enable signal. The enable signal is active in a partial period of the first display period. The first display period corresponds to a first bit that is a lower bit of display data. When the enable signal is active in a partial period of the first display period, a pixel is ON-state or OFF-state. In the first example in
In the technique in the past illustrated in
In addition, in the present exemplary embodiment, the enable line drive circuit 130 outputs an enable signal such that a length of a period in which the enable signal is active in the first display period is ½ of a length of a period in which the enable signal is active in the second display period. In the first example in
In this way, an enable signal is active in an active period proportional to a grey-scale value, and a pixel is ON-state or OFF-state, thus grey-scale display can be realized even when a display period is the same.
In addition, in the present exemplary embodiment, the scan line drive circuit 110 selects each scan line n times in a field, thus the first to n-th bits of display data is written to each pixel circuit. Specifically, when the scan line drive circuit 110 selects a scan line n times, in each of the selections, the data line drive circuit 120 writes one of the first to n-th bits to a pixel circuit connected to the selected scan line. At this time, the data line drive circuit 120 writes the first to the n-th bits so as not to overlap in the n selections. In
As described above, focusing on one scan line, the first to n-th scan line selection periods and the first to n-th display periods are required in one field. According to the present exemplary embodiment, each scan line is selected n times, and the first to n-th bits are written to the scan line, and thus the first to n-th scan line selection periods and the first to n-th display periods are realized for all the scan lines in one field.
According to the exemplary embodiment in the second example, the scan line drive circuit 110 selects once the scan line group to be selected among the plurality of scan lines, in the subfield included in the plurality of subfields. The scan line group includes a scan line connected to a pixel circuit to which an i-th bit is written in a subfield, and a scan line connected to a pixel circuit to which a j-th bit is written in a subfield. i is an integer from 1 to n, and j is an integer from 1 to n and different from i.
In the technique in the past illustrated in
Here, the plurality of subfields are the subfields included in the field FR, and specifically, a plurality of periods divided from the field FR are the plurality of subfields. In
In addition, in the exemplary embodiment in the second example, each subfield of the plurality of subfields is a period of the same length. In addition, in the exemplary embodiment in the second example, the scan line group includes the n scan lines from the scan line connected to the pixel circuit to which the first bit is written in the subfield, to the scan line connected to the pixel circuit to which the n-th bit is written in the subfield.
The fact that each subfield is the period of the same length is that the number of scan lines of the selected scan line group is the same in each subfield. Then, the same number of scan lines as the number of bits of the display data are selected for each subfield to make one round, and thus the first to n-th bits are written to all of the scan lines. In
Note that in
Further, as illustrated in
In this way, the light emitting element is used as the pixel 31, and the emission or non-emission of light of the light emitting element is controlled in accordance with the first to n-th bits of display data, and thus the grey-scale display is enabled. Furthermore, by storing the first to n-th bits of the display data in the memory circuit 33, power consumption at the time of writing can be reduced compared to a case where the image signal DT is held by the capacitor.
In the second example, the number of scan lines is 2n-β+β for the n-bit display data, but in third and fourth examples, the number of scan lines is 2×(2n-β+β) for the n-bit display data. Note that, an example will be described here in which the number of scan lines is doubled, but the number can be three times or greater in a similar manner.
In the third example of
In the fourth example of
In the third example and the fourth example, the total number of scan line selections in one field is 2×(2n-β+β)×n for n-bit display data. That is, the total number is twice the total number of scan line selections in the second example.
In
In the fifth example as well, similar to the second example, a length of one subfield is 6 h, six scan lines are selected in one subfield, and first to sixth bits are written to the six scan lines, one bit at a time. However, in the fifth example, the bit written to the scan line is different from the second example. Furthermore, the field FR includes j=21 subfields SF1 to SF21.
Taking the subfield SF1 as an example, the sixth bit, the first bit, the second bit, the third bit, the fourth bit, and the fifth bit are written to a first scan line, a second scan line, a fourth scan line, a sixth scan line, a 12th scan line, and a 20th scan line, respectively. This selection order pattern is shifted upward by two scan lines for each subfield. Then, the subfields SF1 to SF21 make one round, each scan line is selected n times, and the first to an n-th bits are written to each scan line. Therefore, the total number of scan line selections in one field is j×n.
In
In the present exemplary embodiment, when the number of scan lines of an electro-optical element is k, the number of dummy scan lines is p, and J=k+p, J is a number that is greater than k and for which the lowest common multiple with n is J×n. The scan line drive circuit 110 performs J×n scan line selections in the field FR, selects k scan lines LSC1 to SCk of the electro-optical element in k×n scan line selections among the J×n scan line selections, and selects p dummy scan lines in p×n scan line selections as internal processing.
Here, a dummy scan line number is a scan line that is present in a selection order pattern as internal processing of the scan line drive circuit 110, but is not present as a scan line of the electro-optical element, and is not an actual drive object.
For example, when display data contains six bits and the number of scan lines of an electro-optical element is 20, 18 in the second example is insufficient, thus is doubled to 36 in the third example or the fourth example. At this time, because the 16 dummy scan lines are generated, the dummy scan lines will be selected 16×6=96 times among the total number of scan line selections 36×6=216. In other words, non-scanning periods for the 96 selections are generated. On the other hand, in the fifth example, by setting k=20 and p=1, a selection order pattern can be constituted with J=21 scan lines. In this case, the total number of scan lines is 21×6=126, and among that, the number of selections of the dummy scan lines is 1×6=6.
Thus, in the fifth example compared to the second to fourth examples, the number of scan lines J in a drive order pattern can be set to a minimum in accordance with the number of scan lines of the electro-optical element. As a result, the number of selections of the dummy scan lines can be reduced, and as a result, the number of total scan line selections in one frame can be reduced. As a result, the scan line drive frequency can be lowered compared to the second to fourth examples, allowing for further low power consumption or reliable writing of data to the pixel circuit.
In the second to fifth examples, when focusing on one scan line, the first to n-th bits are sequentially written, that is, the first to n-th scan line selection periods are sequentially aligned. In sixth and seventh examples, a writing order of first to n-th bits is set so that long display periods corresponding to bits having large grey-scale values are not continuous.
When the long display periods, 12 h, 24 h, and 48 h are adjacent, and a pixel is ON-state in all of the display periods, or when a pixel is OFF-state in all of the display periods, a state may continue where the pixel is ON-state or OFF-state for an extended period of time in a frame. In such a case, it may appear flickering when viewing an image appearing on a screen. According to the present exemplary embodiment, 12 h, 24 h and 48 h, which are the long display periods, are not adjacent, thus it is possible to reduce flickering of an image.
Note that, the order of writing bits may be changed as appropriate in accordance with the number of bits of display data and the like. For example, when display data contains four bits, a writing order may be set to, for example, a first bit, a third bit, a second bit, and a fourth bit.
In
Focusing on one scan line, a first bit, a sixth bit, a third bit, a fourth bit, a sixth bit, a second bit, and a fifth bit are written in that order. A third display period and a fourth display period are inserted between the first sixth display period and the second sixth display period. Lengths of the respective display periods are aligned as 6 h, 24 h, 6 h, 12 h, 24 h, 24 h.
In
According to the present exemplary embodiment, a scan line group selected in the subfield includes n−1 scan lines and two or more scan lines. The n−1 scan lines are n−1 scan lines from a scan line connected to a pixel circuit to which the first bit is written in the subfield to a scan line connected to a pixel circuit to which an n−1-th bit is written in the subfield. The two or more scan lines are two or more scan lines connected to two or more pixel circuits to which an n-th bit, which is a higher bit of display data in the subfield, is written. In the subfield SF1 of
In this way, in the subfield, the n-th bit, which is the higher bit of the display data, is written to the two or more scan lines, and thus, an n-th display period, which is longer than a display period corresponding to a lower bit, can be divided into two or more.
In addition, in the present exemplary embodiment, the n-th display period corresponding to the n-th bit includes a first n-th display period and a second n-th display period. At least one display period of the first to n−1-th display periods is provided between the first n-th display period and the second n-th display period.
In this way, at least one display period of the first to n−1-th display periods that is shorter than the n-th display period can be inserted between the first n-th display period and the second n-th display period. This reduces the likelihood that a pixel may be ON-state or OFF-state for a long period of time, and flickering of an image displayed on a screen can be reduced.
The electro-optical element 15 includes an element substrate 11, a protective substrate 12, terminals 13, the pixel array 20, and the circuit device 100.
The element substrate 11 is a semiconductor substrate such as silicon substrate or the like, for example. The pixel array 20 includes pixel portions 30b, 30g, and 30r arranged in a matrix, and the pixel portions 30b, 30g, and 30r are formed at the element substrate 11. A blue color filter is provided in a light emitting element of the pixel portion 30b, a green color filter is provided in a light emitting element of the pixel portion 30g, and a red color filter is provided in a light emitting element of the pixel portion 30r.
The circuit device 100 is constituted by an integrated circuit formed at the element substrate 11. The circuit device 100 includes the scan line drive circuit 110, the data line drive circuit 120, and the enable line drive circuit 130. The circuit device 100 and the terminals 13 are connected by wiring (not illustrated) formed at the element substrate 11. The terminals 13 are connected to the display controller 60 in
The protective substrate 12 is arranged covering the element substrate 11 except for an arrangement portion of the terminals 13. The protective substrate 12 is provided to protect the pixel array 20 and the circuit device 100 formed at the element substrate 11. The protective substrate 12 is a light transmissive substrate such as, for example, a glass substrate.
The head-mounted display has an eyeglass-like appearance, and allows a user wearing the head-mounted display to visually recognize image light overlaid on external light. The electronic apparatus 300, which is the head-mounted display, includes transparent members 303a, 303b, a frame 302, projection devices 305a and 305b.
The frame 302 supports the transparent members 303a, 303b, the projection devices 305a and 305b. The frame 302 is mounted to a head of the user so that the head-mounted display is mounted to the head of the user. The transparent member 303a is provided at a right eye portion of the frame 302, and the transparent member 303b is provided at a left eye portion of the frame 302. The transparent members 303a and 303b transmit external light, thereby allowing the user to visually recognize external light. The projection device 305a is provided at from a right temple portion of the frame 302 to the right eye portion, and the projection device 305b is provided at from a left temple portion to the left eye portion of the frame 302. The projection devices 305a and 305b cause image light to be incident on the eyes of the user, thereby allowing the user to visually recognize image light overlaid on external light.
The projection device 305a includes the electro-optical element 15a. As illustrated in
The circuit device according to the present exemplary embodiment described above includes the scan line drive circuit and the enable line drive circuit. The scan line drive circuit drives the plurality of scan lines of the electro-optical element. The electro-optical element includes the plurality of scan lines, the plurality of pixels, and the plurality of pixel circuits. The enable line drive circuit outputs an enable signal to the plurality of pixel circuits. A field for constituting a single image includes first to n-th scan line selection periods and first to n-th display periods. During the first to n-th scan line selection periods, first to n-th bits of display data (n is an integer of 2 or greater) are written to pixel circuits included in the plurality of pixel circuits. In the first to n-th display periods, a pixel of the plurality of pixels connected to the pixel circuit is ON-state or OFF-state based on the first to n-th bits written to the pixel circuit. The field includes a plurality of subfields. The enable line drive circuit outputs an enable signal that is active in a partial period of the first display period. The first display period corresponds to a first bit that is a lower bit of display data. When the enable signal is active in a partial period of the first display period, a pixel is ON-state or OFF-state.
According to the present exemplary embodiment, in a part of the first display period corresponding to the first bit, by turning the pixel ON-state or OFF-state using the enable signal, grey-scale display can be realized without changing a length of the display period. As a result, the number of scan line selections in one field can be reduced, in comparison with a case in which the grey-scale control by the enable signal is not performed, and the scan line drive frequency can be lowered.
In addition, in the present exemplary embodiment, the enable line drive circuit may output an enable signal such that a length of a period in which the enable signal is active in a first display period is ½ of a length of a period in which the enable signal is active in a second display period.
According to the present exemplary embodiment, an enable signal is active in an active period proportional to a grey-scale value, and a pixel is ON-state or OFF-state, thus grey-scale display can be realized even when a display period is the same.
Further, in the present exemplary embodiment, in a field, first to n-th bits of display data may be written to each pixel circuit of the plurality of pixel circuits, by the scan line drive circuit selecting each scan line of the plurality of scan lines n times.
Focusing on one scan line, first to n-th scan line selection periods and first to n-th display periods are required in one field. According to the present exemplary embodiment, each scan line is selected n times, and the first to n-th bits are written to the scan line, and thus the first to n-th scan line selection periods and the first to n-th display periods are realized for all the scan lines in one field.
In addition, in the present exemplary embodiment, the scan line drive circuit may select once a scan line group to be selected among the plurality of scan lines, in a subfield included in the plurality of subfields. The scan line group may include a scan line connected to a pixel circuit to which an i-th bit (i is an integer from 1 to n) of first to n-th bits of display data is written in a subfield, and a scan line connected to a pixel circuit to which a j-th bit (j is an integer from 1 to n and different from i) of the first to n-th bits of the display data is written in the subfield.
According to the present exemplary embodiment, the i-th bit is written to one scan line in one subfield, and the j-th bit is written to another scan line. As a result, the non-scanning periods in which no scan line is selected can be reduced, and the scan line drive frequency can be lowered compared to the technique in the past.
In addition, in the present exemplary embodiment, each subfield of the plurality of subfields may be a period of the same length.
In addition, in the present exemplary embodiment, the scan line group may include n scan lines from a scan line connected to a pixel circuit to which a first bit is written in a subfield to a scan line connected to a pixel circuit to which an n-th bit is written in the subfield.
The fact that each subfield is a period of the same length is that the number of scan lines of a selected scan line group is the same in each subfield. Then, a selection order pattern is constituted such that the scan line group includes n scan lines from a scan line connected to a pixel circuit to which a first bit is written, to a scan line connected to a pixel circuit to which an n-th bit is written. By constituting such a selection order pattern, the first to n-th bits can be written to the pixel connected to each scan line in one field, and periods in which no scanning is selected can be reduced.
In addition, in the present exemplary embodiment, a scan line group may include, n−1 scan lines from a scan line connected to a pixel circuit to which a first bit is written in a subfield, to a scan line connected to a pixel circuit to which an n−1-th bit of first to n-th bits of display data is written in the subfield, and two or more scan lines connected to two or more pixel circuits to which the n-th bit, which is a higher bit of display data, is written in the subfield.
According to the present exemplary embodiment, in the subfield, the n-th bit, which is the higher bit of the display data, is written to the two or more scan lines, and thus, an n-th display period, which is longer than a display period corresponding to a lower bit, can be divided into two or more.
In addition, in the present exemplary embodiment, an n-th display period corresponding to an n-th bit may include a first n-th display period and a second n-th display period. At least one display period of first to n−1-th display periods may be provided between the first n-th display period and the second n-th display period.
According to the present exemplary embodiment, at least one display period of the first to n−1-th display periods, that is shorter than the n-th display period can be inserted between the first n-th display period and the second n-th display period. This reduces the likelihood that a pixel may be ON-state or OFF-state for a long period of time, and flickering of an image displayed on a screen can be reduced.
In addition, in the present exemplary embodiment, when the number of scan lines of an electro-optical element is k, the number of dummy scan lines is p, and J=k+p, J may be a number that is greater than k and for which the lowest common multiple with n is J×n. The scan line drive circuit may perform J×n scan line selections in a field, select k scan lines of the electro-optical element in k×n scan line selections among the J×n scan line selections, and select p dummy scan lines in p×n scan line selections as internal processing.
According to the present exemplary embodiment, the number of scan lines J included in a drive order pattern can be set to a number that is not an integer multiple of 2n. Accordingly, the number of scan lines J in the drive order pattern can be set to a minimum in accordance with the number of scan lines of the electro-optical element. As a result, the number of selections of the dummy scan lines can be reduced, and as a result, the number of total scan line selections in one frame can be reduced.
Further, in the present exemplary embodiment, the pixel may be a light emitting element. The pixel circuit may include a memory circuit. In first to n-th scan line selection periods, first to n-th bits may be written to the memory circuit. In first to n-th display periods, the light emitting element may or may not emit light due to the first to n-th bits written to the memory circuit.
According to the present exemplary embodiment, the light emitting element is used as the pixel, and the emission or non-emission of light of the light emitting element is controlled in accordance with the first to n-th bits of display data, and thus grey-scale display is enabled. Furthermore, by storing the first to n-th bits of the display data in the memory circuit, power consumption at the time of writing can be reduced compared to a case where an image signal is held by a capacitor.
Additionally, the electro-optical element according to the present exemplary embodiment includes the circuit device described in any of the above, the plurality of scan lines, the plurality of pixels, and the plurality of pixel circuits.
In addition, the electro-optical element according to the present exemplary embodiment includes the plurality of scan lines, the data line, the plurality of pixel portions arranged corresponding to the respective intersections of the plurality of scan lines and the data line, the scan line drive circuit configured to output a selection signal to the plurality of scan lines, and the enable line drive circuit configured to output an enable signal to the plurality of pixel portions. Each pixel portion of the plurality of pixel portions includes the pixel circuit configured to hold display data of first to n-th bits (n is an integer of 2 or greater) bit by bit in a predetermined order, and the pixel that is ON-state or OFF-state based on an enable signal and the held display data. The enable line drive circuit outputs, in first to n-th display periods in which the pixel is ON-state or OFF-state, an enable signal that is active in a partial period of the first display period corresponding to a first bit, which is a lower bit of the display data.
In addition, in the electro-optical element according to the present exemplary embodiment, the enable line drive circuit may output an enable signal such that a length of a period in which the enable signal is active in a first display period is ½ of a length of a period in which the enable signal is active in a second display period.
Further, in the electro-optical element according to the present exemplary embodiment, in a plurality of subfields, the scan line drive circuit may select each scan line of the plurality of scan lines n times, and thus display data corresponding to each of the bits of first to n-th bits of the display data may be held in the pixel circuit.
In addition, in the electro-optical element according to the present exemplary embodiment, the scan line drive circuit may select once a scan line group to be selected among the plurality of scan lines, in each subfield included in a plurality of subfields. The scan line group, in a subfield, may include a scan line corresponding to a pixel circuit to which display data corresponding to an i-th bit (i is an integer from 1 to n) included in first to n-th bits is supplied, and a scan line corresponding to a pixel circuit to which display data corresponding to a j-th bit (j is an integer from 1 to n and different from i) included in the first to n-th bits is supplied.
In addition, in the electro-optical element according to the present exemplary embodiment, each subfield of a plurality of subfields may be a period of the same length.
In addition, in the electro-optical element according to the present exemplary embodiment, the pixel circuit may include a memory circuit. The pixel may include a light emitting element that does or does not emit light due to display data held in the memory circuit.
Further, the electronic apparatus according to the present exemplary embodiment includes the circuit device described in any of the above, and the electro-optical element.
Further, the electronic apparatus according to the present exemplary embodiment includes the electro-optical element described in any of the above.
Although the present exemplary embodiment has been described in detail above, those skilled in the art will easily understand that many modified examples can be made without substantially departing from novel items and effects of the present disclosure. All such modified examples are thus included in the scope of the disclosure. For example, terms in the descriptions or drawings given even once along with different terms having identical or broader meanings can be replaced with those different terms in all parts of the descriptions or drawings. All combinations of the embodiment and modified examples are also included within the scope of the disclosure. Furthermore, the configurations, operations, and the like of the circuit device, the pixel circuit, the pixel, the electro-optical element, and the electronic apparatus are not limited to those described in the present exemplary embodiment, and various modifications thereof are possible.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP2020-111370 | Jun 2020 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20020093472 | Numao | Jul 2002 | A1 |
| 20040056605 | Yoshida | Mar 2004 | A1 |
| 20040233143 | Kasai | Nov 2004 | A1 |
| 20050231450 | Takai | Oct 2005 | A1 |
| 20130201172 | Jeong | Aug 2013 | A1 |
| 20130328753 | Tsuge | Dec 2013 | A1 |
| 20150302795 | Genoe | Oct 2015 | A1 |
| 20160351121 | Kim | Dec 2016 | A1 |
| 20170061878 | Park | Mar 2017 | A1 |
| 20190235250 | Miyasaka et al. | Aug 2019 | A1 |
| 20210407382 | Momose et al. | Dec 2021 | A1 |
| Number | Date | Country |
|---|---|---|
| 2002-169510 | Jun 2002 | JP |
| 2002-287718 | Oct 2002 | JP |
| 2004-117648 | Apr 2004 | JP |
| 2005-301174 | Oct 2005 | JP |
| 2008-281827 | Nov 2008 | JP |
| 2016-500850 | Jan 2016 | JP |
| 2019-132941 | Aug 2019 | JP |
| 2013021622 | Feb 2013 | WO |
| Entry |
|---|
| Jan. 20, 2022 Office Action issued in U.S. Appl. No. 17/360,591. |
| U.S. Appl. No. 17/360,591, filed Jun. 28, 2021 in the name of Momose et al. |
| Apr. 12, 2022 Notice of Allowance issued in U.S. Appl. No. 17/360,591. |
| Number | Date | Country | |
|---|---|---|---|
| 20210407382 A1 | Dec 2021 | US |
