The present invention relates to a circuit for adjusting a cutoff frequency of a filter in a semiconductor integrated circuit. More particularly, the present invention is suitable for a circuit for adjusting a cutoff frequency of a filter including a capacitor and a resistor.
Conventionally, Filter circuits including capacitors and resistors are used in various electronic circuits.
f
c=½π(RC)1/2
and depends on a resistor value R of the resistor and a capacitive value C of the capacitor.
Here, the resistor value R and the capacitive value C are set at necessary values for obtaining a desired cutoff frequency. However, in a practical semiconductor process, there is a problem that cutoff frequencies are shifted due to manufacturing variation of resistors and capacitors of filter circuits (variation of the resistor value R and the capacitive value C is on the order of ±30% in a semiconductor process) so that a cutoff frequency standard is not satisfied, resulting in a possibility of defective products. Because of this, it is desirable that cutoff frequencies of filter circuits can be adjusted individually before shipping products manufactured with the filter circuits embedded (for example, radio receivers or the like).
Accordingly, a conventional filter circuit has been proposed in which a plurality of resistors having different resistor values are provided and a resistor value is to be variable by being able to select any of the resistors, thereby being able to adjust a cutoff frequency (for example, see Patent documents 1 and 2).
Patent document 1: Japanese Patent Laid-Open No. 2004-23547
Patent document 2: Japanese Patent Laid-Open No. 2004-303508
In Patent documents 1 and 2, how to select an optimum resistor value for obtaining a desired cutoff frequency is not disclosed and a method for selecting a resistor value is not clear even though the resistor value can be selected.
Thus, the present invention has an object to be able to appropriately adjust a cutoff frequency of a filter by using a signal processing part such as DSPs (Digital Signal Processor).
In order to solve the problem described above, a circuit for adjusting a cutoff frequency of a filter according to the present invention includes a filter circuit provided with a plurality of resister elements, a switch to select any of a plurality of the resister elements and a capacitor. A cutoff frequency of the filter circuit is determined based on a resistor value of a resister element selected from a plurality of the resister elements by the switch and a capacitive value of the capacitor. The present invention further includes a clock signal generator that generates a first frequency clock signal as a reference and a second frequency clock signal for adjusting; and a signal processing part that compares a first level of a signal output from the filter circuit when the first frequency clock signal is input to the filter circuit with a second level of a signal output from the filter circuit when the second frequency clock signal is input to the filter circuit, and that controls the switch depending on the comparing result.
Also, a plurality of capacitors may be provided instead of a plurality of the resister elements and the cutoff frequency of the filter circuit may be determined based on a capacitive value of a capacitor selected by the switch and a resistor value of the resister element. Similarly to the above case, a cutoff frequency adjustment in this case is also performed by using the clock signal generator and the signal processing part. For example, it is determined whether a difference between the first level and the second level is within a predetermined value or not, and it is determined which of the second level and the predetermined value is greater if the difference is not within the predetermined value and the switch is controlled depending on the determination result.
According to the present invention with the above configuration, it is possible to select an optimum resistor value or capacitive value by using the signal processing part, thereby being able to appropriately adjust a cutoff frequency of a filter.
Hereinafter, one embodiment of the present invention is described with reference to the drawings.
The DSP 3 performs an on-off control of the respective switches SW1 to SW3 by a mode control signal AE and controls an operation of the clock signal generator 2 by the mode control signal AE and a frequency switching control signal FSEL. When the mode control signal AE output from the DSP 3 is at “Lo” level; a normal mode is employed in which the first and the second switches SW1 and SW2 are off, and the third switch SW3 is on. On the other hand, when the mode control signal AE is at “Hi” level; an adjusting mode of a cutoff frequency is employed in which the first and the second switches SW1 and SW2 are on, and the third switch SW3 is off.
The clock signal generator 2 sequentially generates a first frequency (for example, 2-40 KHz) clock signal CK1 and a second frequency (for example, 480 KHz) clock signal CK2 when the adjusting mode of the cutoff frequency is set by the DSP 3.
Reference numeral 23 denotes a ½ divider circuit dividing the frequency of the clock signal CK (3.84 MHz) into ½. Reference numeral 24 denotes a frequency switching switch whose switching is controlled by the frequency switching control signal FSEL supplied from the DSP 3. A clock signal (undivided signal of 3.84 MHz) supplied from an input terminal of the ½ divider circuit 23 and a clock signal (½ divided signal of 1.92 MHz) supplied from an output terminal of the ½ divider circuit 23 are input to two input terminals of the frequency switching switch 24. When the clock signal CK1 of 240 KHz is generated at the clock signal generator 2, the frequency switching switch 24 selects and outputs the clock signal supplied from the output terminal of the ½ divider circuit 23. On the other hand, when the clock signal CK2 of 480 KHz is generated at the clock signal generator 2, the frequency switching switch 24 selects and outputs the clock signal supplied from the input terminal of the ½ divider circuit 23.
Reference numeral 25 denotes a 3-bit counter performing a count operation based on the clock signal selectively output from the frequency switching switch 24 and outputting a 3-bit count value. Here, reference characters Q0, Q1 and Q2 respectively denote output terminals of a most significant bit, a second bit and a least significant bit. Reference numeral 26 denotes third AND gates each of which is provided to each bit of count values counted by the 3-bit counter 25. The each AND gate 26 corresponding to the each bit operates logical multiplication a value of the each bit output from the 3-bit counter 25 and the mode control signal AE to output the result. In the case of improving voltage accuracy, the number of bits in the counter may be increased.
Reference numeral 27 denotes resistors each of which is provided to three outputs of the third AND gates 26, and a ratio of a resistor value thereof is 4R:2R:R sequentially from the most significant bit. In the case of IC, relative accuracy of the resistances is great. One ends of the three resistors 27 are connected together and a signal at the connecting point is output as the first frequency clock signal CK1 or the second frequency clock signal CK2. Reference numeral 28 denotes a bias resistor applying a bias voltage to the clock signal. The clock signals CK1/CK2 output from the clock signal generator 2 are input to the filter circuit 1 through the second switch SW2 and the buffer 4 shown in
Note that while the circuit in
Reference character CO denotes a capacitor connected to an input terminal IN, reference character C1 denotes a capacitor connected between the plus input terminal of the differential operational amplifier OA and the ground, and reference character C2 denotes a capacitor connected between an output terminal OUT of the differential operational amplifier OA and a connecting point of the resistances R1 and R2. An output of the differential operational amplifier OA is input to a minus input terminal of the differential operational amplifier OA in a negative feedback manner.
The filter circuit 1 shown in
Reference characters S11, S12, . . . , S1N-1 denote switches to select any of a plurality of the resister elements R11, R12, . . . , R1N and reference characters S21, S22, . . . , S2N-1 denote switches to select any of a plurality of the resister elements R21, R22, . . . , R2N. A plurality of the resister elements R11, R12, . . . , R1N and a plurality of the switches S11, S12, . . . , S1N-1 are ladder-connected, and turning on any one of the switches selects a resister element to be serially connected. For example, turning on the first switch S11 short-circuits the first resister element R11 and serially connects the resister elements R12, . . . , R1N from the second resister element onward.
Similarly, a plurality of the resister elements R21, R22, . . . , R2N and a plurality of the switches S21, S22, . . . , S2N-1 are ladder-connected, and turning on any one of the switches selects a resister element to be serially connected. For example, turning on the first switch S21 short-circuits the first resister element R21 and serially connects the resister elements R22, . . . , R2N from the second resister element onward.
Here, both of the i th (i=1 to N−1) switches among a plurality of the switches S11, S12a, . . . , S1N-1 and S21, S22, . . . , S2N-1 synchronize each other to be turned on. In this manner, turning on any one pair of switches S1i and S2i enables the resistor values of the resistances R1 and R2 connected to the differential operational amplifier OA to be variable.
Thus, a cutoff frequency fc of the filter circuit 1 can be variable. Specifically, the cutoff frequency fc of the filter circuit 1 is determined based on combined resistor values of serial connections of the resister elements selected from a plurality of the resister elements R11, R12, . . . , R1N and R21, R22, . . . , R2N by the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1; and the capacitive values of the capacitors C1 and C2. Assume that the combined resistance values of the resistances R1 and R2 are respectively represented by R1 and R2, and the capacitive values of the capacitors C1 and C2 are respectively represented by C1 and C2; the cutoff frequency fc of the filter circuit 1 is obtained by:
f
c=½π(R1R2C1C2)1/2
Returning to
Additionally, in the adjusting mode of the cutoff frequency, the DSP 3 compares a level LV1 of a signal output from the filter circuit 1 when the first frequency clock signal CK1 generated at the clock signal generator 2 is input to the filter circuit 1 with a level LV2 of a signal output from the filter circuit 1 when the second frequency clock signal CK2 generated at the clock signal generator 2 is input to the filter circuit 1; and controls the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 depending on the comparing result. That is, the DSP 3 turns off all the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 or turns on any one pair of the switches S1i and S2i by supplying switch control signals BP1 to BPN-1 to the filter circuit 1.
To specifically describe the control of the switch, the DSP 3 first detects a difference β between the signal levels LV1 and LV2, and determines whether a value of the difference β is equal to a predetermined value α (a value corresponding to a difference between signal levels of 240 KHz and 480 KHz in a frequency characteristic indicating a desired cutoff frequency) or is within a predetermined tolerance x to the predetermined value α.
For example, in the case of constituting the filter circuit 1 with a frequency characteristic like a solid line shown in
On the other hand, in the case where a frequency characteristic is shifted from the desired frequency characteristic like dotted lines due to manufacturing variations of resistors or capacitors, the level LV2 of a signal output from the filter circuit 1 is not −α dB (β≠α) when the clock signal CK2 of 480 KHz is input to the filter circuit 1, so that an error occurs. The DSP 3 determines whether the error is within the predetermined tolerance x. Specifically, if the tolerance is ±x, the DSP 3 determines whether a condition of α−x≦β≦α+x is satisfied or not. Then, if the condition is not satisfied, the DSP 3 determines which of the signal level LV2 and the predetermined value α is greater and switches selection states of the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 depending on the determination result.
Here, when LV2>α, since an actual cutoff frequency is shifted higher than a desired cutoff frequency, switching the switches at more front stage sides (sides of the switches S11 and S12) than the present situation into the on-state increases the combined resistance values R1 and R2, thereby lowering the cutoff frequency. On the contrary, when LV2<α, since the actual cutoff frequency is shifted lower than the desired cutoff frequency, switching the switches at more subsequent stage sides (sides of the switches S1N-1 and S2N-1) than the present situation into the on-state reduces the combined resistance values R1 and R2, thereby increasing the cutoff frequency.
When the difference β between the signal levels LV1 and LV2 is adjusted to be the predetermined value α or within the tolerance x, data indicating a selection state of each switch S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 is held in a not-shown memory, and the DSP 3 holds the selection state of each switch S11, S12, . . . , S1N-1, and S21, S22, . . . , S2N-1 in accordance with the data. Because of this, the desired frequency characteristic is maintained constantly.
The radio receiver shown in
When a normal mode is set by a DSP 3, the IF signal generated at the mixer 53 is supplied to a buffer 4 through a third switch SW3. An IF filter 54 connected to a subsequent stage of the buffet 4, which corresponds to the filter circuit 1 described above, removes a signal of a close channel by a filtering process to the IF signal input from the buffer 4 and outputs the result to an A/D converter 6. The A/D converter 6 converts the IF signal input from the IF filter 54 into digital data and supplies it to the DSP 3. The DSP 3 performs a baseband process including a demodulation process to the input digital data.
On the other hand, when an adjusting mode of a cutoff frequency is set by the DSP 3, clock signals CK1 and CK2 sequentially generated at a clock signal generator 2 are supplied to the buffer 4 through a second switch SW2. The IF filter 54 performs the filtering process to the clock signals CK1/CK2 input from the buffer 4 and outputs the result to the A/D converter 6. The A/D converter 6 converts the signal input from the IF filter 54 into digital data and supplies it to the DSP 3. The DSP 3 controls switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 of the IF filter 54 (filer circuit 1) by using the input digital data (data indicating signal levels LV1 and LV2).
Next, the clock signal generator 2 generates the clock signal CK1 of 240 KHz in accordance with the control of the DSP 3 (step S3). The first frequency clock signal CK1 generated here is processed at the filter circuit 1 and the A/D converter 6, and supplied to the DSP 3. The DSP 3 detects the signal level LV1 based on data input from the A/D converter 6 and holds it in a not-shown memory (step S4).
Next, the clock signal generator 2 generates the clock signal CK2 of 480 KHz in accordance with the control of the DSP 3 (step S5). The second frequency clock signal CK2 generated here is processed at the filter circuit 1 and the A/D converter 6, and supplied to the DSP 3. The DSP 3 detects the signal level LV2 based on data input from the A/D converter 6, and holds it in the not-shown memory (step S6).
Then, the DSP 3 calculates a difference P between the signal levels LV1 and LV2 (step S7) and determines whether a value of the difference β is equal to a predetermined value α or within a predetermined tolerance ±x. Specifically, the DSP 3 determines whether a condition of α−x≦β≦α+x is satisfied or not (step S8). If the condition is not satisfied, the DSP 3 determines whether the signal level LV2 is greater than the predetermined value α or not (step S9).
If LV2>α, since an actual cutoff frequency is shifted higher than a desired cutoff frequency, the DSP 3 controls the switches at more front stage sides (sides of the switches S11 and S21) than the switches turned on in step S1 so as to be switched into the on-state (step S10). This increases combined resistance values R1 and R2, thereby lowering the cutoff frequency.
On the other hand, if LV2<α, since the actual cutoff frequency is shifted lower than the desired cutoff frequency, the DSP 3 controls the switches at more subsequent stage sides (sides of the switches S1N-1 and S2N-1) than the switches turned on in step S1 so as to be switched into the on-state (step S11). This reduces the combined resistance values R1 and R2, thereby bringing the cutoff frequency higher.
After the process of step S10 or step S11, the processing returns to step S3 for repeating the similar process. The processing may return to step S5 instead of step S3. Like this repeating processing sequentially switches which switch to be turned on among the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1. Then, if the condition of α−x≦β≦α+x is satisfied in step S8, the DSP 3 holds switch control signals BP1 to BPN-1 at that time in the not-shown memory (step S12), and switches the mode control signal AE back to “Lo” (step S13). If the condition of step S8 is not satisfied even though the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 are switched in any manner, an error processing is performed.
States of the switches S11, S12, . . . , S1N-1 and S21, S22, . . . , S2N-1 are established by holding the switch control signals BP1 to BPN-1 in the memory in step 12. This memory may be a nonvolatile or a volatile memory. If a nonvolatile memory is used, once a cutoff frequency adjustment is performed, another adjustment is not required after that. If a volatile memory is used, a cutoff frequency adjustment is performed every time, for example, a power supply of the radio receiver is turned on. Note that, even if a nonvolatile memory is used, it is also possible to perform the adjustment again.
As described above in detail, according to the embodiment, it is possible to select an optimum resistor value of the filter circuit 1 by a digital signal processing with the DSP 3 so that a cutoff frequency of the filter circuit 1 can be appropriately adjusted.
In the embodiment, an example is described in which selecting any of a plurality of the resister elements R11, R12, . . . , R1N and R21, R22, . . . , R2N makes a resistor value variable, thereby adjusting a cutoff frequency of the filter circuit 1, however, the present invention is not limited thereto. For example, it is: also possible that a plurality of capacitors are provided and selecting any of the capacitors makes a capacitive value variable, thereby adjusting the cutoff frequency of the filter circuit 1.
Also, in the embodiment, an example is described in which 240 KHz and 480 KHz are used as frequencies for the clock signals CK1 and CK2 generated at the clock signal generator 2, however, the present invention is not limited to the frequencies.
Also, in the embodiment, the secondary active filter is described as an example of the filter circuit 1, however, the present invention is not limited thereto. For example, a primary or a higher-order active filter, or a passive filer may be used. Additionally, it can also be applied to various types of filters such as a Chebyshev filter, a Bessel filter and a biquad filter.
Also, in the embodiment, an example is described in which the circuit for adjusting a cutoff frequency is applied to the radio receiver, however, the present invention is not limited thereto. The circuit for adjusting a cutoff frequency can be applied to anything as long as it is an electronic circuit with a filter circuit including a capacitor and a resistor or an applied product thereof.
While the embodiment only shows a concrete example for carrying out the present invention, the technical scope of the present invention should not be limited thereto. Thus, various modifications and changes may be made thereto without departing from the spirit and the main features of the present invention.
The present invention is useful for a circuit for adjusting a cutoff frequency of a filter circuit including a capacitor and a resistor.
Number | Date | Country | Kind |
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2005-362252 | Dec 2005 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2006/314211 | 7/12/2006 | WO | 00 | 6/12/2008 |