The present invention relates generally to integrated circuits, and in particular, to a circuit for and a method of preventing multi-bit upsets induced by single event transient.
Programmable logic devices (PLDs) are a type of integrated circuit that enable the downloading of configuration bits to implement a user's circuit designs. PLDs include various memory elements, as will be described in more detail below. Configuration random access memory (CRAM), including configurable logic element memory (CLEM) are subject to upset from cosmic neutrons, thermal neutrons and terrestrial alpha particles. The failure rate associated with this is commonly known as Soft Error Rate (SER). The industrial metric used to quantify the SER of the circuit is known as FIT rate or FIT/Mb when normalized to device's size. SEU enhanced solutions are used to reduce SEU upsets in CLEM elements. Multi-bit upsets (MBUs) are events in which two or more error bits occur in the same word. With the adequate interleaving strategy and ECC scheme they are expected to be correctable.
In an ASIC or FPGA, a single ion strike may cause one or more voltage pulses/glitches to propagate through the circuit. The glitches are called single-event transients (SETs). If a SET propagates through the logic and induces a corrupted logic state to be latched in a memory cell, the SET is then considered an SEU and can results in an increase of the integrated circuit or FPGA FIT rate. SETs in a shift register latch (SRL) clock circuit have been identified as a source of abnormally large MBUs in CLEM logic by allowing erroneous data to be latched in given lookup table RAM (LUTRAM) arrays. These SET induced MBUs are larger than the cell interleaving size and therefore are uncorrectable. SETs in CLEM elements increase the FPGA FIT rate and force the user to reconfigure the FPGA.
A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal.
A method of preventing multi-bit upsets induced by single event transients is also described. The method comprises generating a first clock signal and a second clock signal, wherein the first clock signal is the same as the second clock signal; receiving a first input signal at a first memory element; generating a first output signal at an output of the first memory element in response to the first clock signal; receiving the first output of the first memory element at a second memory element; receiving the second clock signal at a clock input of the second memory element; and generating a second output signal.
Other features will be recognized from consideration of the Detailed Description and the Claims, which follow.
While the specification includes claims defining the features of one or more implementations of the invention that are regarded as novel, it is believed that the circuits and methods will be better understood from a consideration of the description in conjunction with the drawings. While various circuits and methods are disclosed, it is to be understood that the circuits and methods are merely exemplary of the inventive arrangements, which can be embodied in various forms. Therefore, specific structural and functional details disclosed within this specification are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the inventive arrangements in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the circuits and methods.
The circuits and methods set forth below eliminate or reduce the probability of uncorrectable multiple-bit upsets (MBUs) induced by single event transients (SETs) in CLEM elements. The circuits and methods generally include an additional inverter in clock circuits to generate separate clock signals that are provided to memory elements. According to a first technique, individual clock signals are assigned to each LUTRAM column, and reduce a count of LUTRAM columns affected by SET, and therefore reduce the number of bit upsets by a factor of 2. According to a second technique, the clock signals of the LUTRAM pass gates are interleaved, and also reduce the probability of SET induced bit upsets by a factor of 2.
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The pair of memory elements 305 for example comprises gating circuitry enabling the coupling of input signals and inverted input signals to inputs of the memory elements. More particularly, a first gating circuit 412 and a second gating circuit 414 are implemented. The first gating circuit 412 comprises a first pass gate 416 (shown here as a transistor) configured to receive the input signal (Sin0) at an input 418 and the Clk_a signal at a control terminal of the pass gate. An inverted input signal is coupled to a second pass gate 420 at an input 422, where the control terminal of the pass gate 420 is also configured to receive the Clk_a signal. Outputs of the pass gates are coupled to corresponding inputs of the memory element 306.
Similarly, the second gating circuit 414 comprises a first pass gate 424 configured to receive an output of the memory element at an input 426 and the Clk_b signal at a control terminal of the pass gate. An inverted output signal is coupled to a second pass gate 428 at an input 430, where the control terminal of the pass gate 428 is also configured to receive the Clk_b signal. Outputs of the pass gates are coupled to corresponding inputs of the memory element 306. As is apparent in
SETs in an SRL clock circuit, such as a clock circuit for generating clock signals to LUTRAMs of an FPGA, can lead to erroneous data to be latched in LUTRAMs and generate abnormally large multi-bit upsets (MBUs). These events are uncorrectable because they are larger than the implemented interleaving strategy size. A single ion strike may cause one or more voltage pulses/glitches, or single-event transients (SETs), to propagate through the circuit. If a SET occurs on Clk_a and pass gates 416 and 420 are on, a corrupted input signal Sin0 (e.g. an erroneous logic “1”) forces q_b to 1. This erroneous value may be latched into 2×16 LUTRAMs of an array receiving the clock signal. Because interleaving is 8:1, the events are uncorrectable. Therefore, 32 bits are upset by the SET. The additional inverters required to generate the extra clock signal has a small impact on the LUTRAMs performance and increase the CLEM area by less than 2%.
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In some FPGAs, each programmable tile includes a programmable interconnect element (INT) 811 having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element 811 also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of
For example, a CLB 802 may include a configurable logic element (CLE) 812 that may be programmed to implement user logic plus a single programmable interconnect element 811. A BRAM 803 may include a BRAM logic element (BRL) 813 in addition to one or more programmable interconnect elements. The BRAM includes dedicated memory separate from the distributed RAM of a configuration logic block. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as five CLBs, but other numbers may also be used. A DSP tile 806 may include a DSP logic element (DSPL) 814 in addition to an appropriate number of programmable interconnect elements. An IOB 804 may include, for example, two instances of an input/output logic element (IOL) 815 in addition to one instance of the programmable interconnect element 811. The location of connections of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The programmable interconnects, in response to bits of a configuration bitstream, enable connections comprising interconnect lines to be used to couple the various signals to the circuits implemented in programmable logic, or other circuits such as BRAMs or the processor.
In the pictured embodiment, a columnar area near the center of the die is used for configuration, clock, and other control logic. The config/clock distribution regions 809 extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA. Some FPGAs utilizing the architecture illustrated in
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In the pictured embodiment, each memory element 902A-902D may be programmed to function as a synchronous or asynchronous flip-flop or latch. The selection between synchronous and asynchronous functionality is made for all four memory elements in a slice by programming Sync/Asynch selection circuit 903. When a memory element is programmed so that the S/R (set/reset) input signal provides a set function, the REV input terminal provides the reset function. When the memory element is programmed so that the S/R input signal provides a reset function, the REV input terminal provides the set function. Memory elements 902A-902D are clocked by a clock signal CK, which may be provided by a global clock network or by the interconnect structure, for example. Such programmable memory elements are well known in the art of FPGA design. Each memory element 902A-902D provides a registered output signal AQ-DQ to the interconnect structure. Because each LUT 901A-901D provides two output signals, O5 and O6, the LUT may be configured to function as two 5-input LUTs with five shared input signals (IN1-IN5), or as one 6-input LUT having input signals IN1-IN6.
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It can therefore be appreciated that new circuits for and methods of preventing multi-bit upsets induced by single event transients have been described. It will be appreciated by those skilled in the art that numerous alternatives and equivalents will be seen to exist that incorporate the disclosed invention. As a result, the invention is not to be limited by the foregoing embodiments, but only by the following claims.
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