Patent Application
20070030260
The present invention relates to display of an image such as a waveform, and more particularly, to a circuit for controlling display of a modulated image such as a persistence or afterglow added image, and to an associated image display method and device.
Conventionally, a variety of techniques are known in the art of a raster scan type digital oscilloscope for providing a persistence or afterglow characteristic as provided in an analog oscilloscope. For example, Laid-open Japanese Patent Application No. 7-280842 entitled “Digital Image Display Device”, opened to the public on Oct. 27, 1995, discloses a raster scan type digitizing oscilloscope which comprises a display memory and a decrementer state machine for providing “gray scale information (or a variable persistence characteristic)”, visible in an analog oscilloscope. A decrementer disposed in the digitizing oscilloscope reads pixel data from the display memory on a pixel-by-pixel basis, decrements the read pixel data, and then rewrites the decremented pixel data to an original memory location. However, in using this processing a data transfer rate from a frame memory to a display is limited to one half (or less) of a memory access rate of the display memory, i.e., a maximum of one frame memory. Also, since the processing must be repeated for each pixel, the frame memory must also be switched between a read and a write state in pixel units, which requires use of a complicated switching control. Further, since image data is not taken into the frame memory at the same time as that for decrementing for a persistence display, a resulting image is intermittently displayed.
In Laid-open Japanese Patent Application No. 4-313066 entitled “Display Device”, opened to the public on Nov. 5, 1992, a display such as a CRT display increments or decrements a display content as appropriate, at an attenuation rate in accordance with the content to be displayed, to thereby provide in a raster scan type digital oscilloscope an afterglow or persistence characteristic mode provided in an analog oscilloscope. This display device includes a buffer memory for modulating image data, and reads the image data from the buffer memory, modulates the read image data, and rewrites the modulated image data into the buffer memory. However, a problem exists in this technique, as is the case with the aforementioned laid-open Japanese Patent Application No. 7-280842, in that a data transfer rate from the buffer memory or a frame memory to the display is limited to one half or less of the memory access rate of the frame memory.
Further, Laid-open Japanese Patent Application No. 6-317609 entitled “Display Circuit Apparatus”, and opened to the public on Nov. 15, 1994 discloses a display circuit apparatus which comprises a display frame memory, provided between a capture frame memory and a display, for realizing a variable persistence characteristic as provided in an analog oscilloscope. The display frame memory is used for writing a persistence data added display image frame, and for reading the frame to the display (for example, a Braun tube) and to a subtractor for forming persistence data. The provision of the display frame memory enables input image data to be captured even during persistence processing, thereby providing for a continuous waveform display. However, since two frame memories are connected in cascade between the image data input and the display, a signal to the display must pass through the frame memory twice, which results in three intervening frame periods: a write period in which the signal is written into the display frame memory, a read period in which the signal is read from the display frame memory (which also serves as a write period in which the signal is written into the display frame memory), and a read period in which the signal is read from the display frame memory. The existence of these three intervening three frame periods causes a significant delay from a time when image data is input to a time when a waveform is displayed, which makes it impossible to display an input image in real time.
To overcome the problems of the prior arts as described above, it is an object of the present invention to provide a method and circuit for controlling a display of a modulated image, which enable a modulated image such as a persistence image to be rapidly displayed.
It is another object of the present invention to provide an image display method and device which enable a modulated image to be displayed substantially in real time in response to an image data input.
It is a further object of the present invention to provide an image display method and device for implementing the modulated image display control as described above.
To achieve the above objects, the present invention provides a method of controlling a display of a modulated image on a raster scan type display in response to an input image frame comprised of a frame of input pixel data. The method includes the steps of receiving input pixel data within the input image frame, and adding modulated pixel data for displaying a modulated image to the received input pixel data to form display pixel data within a display image frame supplied to the display. According to the present invention, the modulated image may be a persistence added image, and the modulated pixel data may be persistence pixel data.
The present invention also provides a method of controlling persistence display in a raster scan type display in response to an input image frame comprised of a frame of input pixel data. The method includes the steps of receiving input pixel data within the input image frame supplied to the display, and adding persistence pixel data for persistence display to the received input pixel data to generate display pixel data within a display image frame supplied to the display.
According to the present invention, the step of adding persistence pixel data may include the steps of receiving the display pixel data within the display image frame, forming, from the display pixel data, persistence pixel data within a persistence image frame to be added to the input pixel data within the input image frame during a frame immediately after the input image frame containing the input pixel data, and adding to the input pixel data within the input image frame persistence pixel data within the persistence image frame at a pixel position corresponding to the input pixel data. Further, the step of forming persistence pixel data may include forming the persistence pixel data during a period of a frame occurring immediately after the input image frame containing the input pixel data. Alternatively, the step of forming persistence pixel data may include forming the persistence pixel data during the period of the same frame as the input image frame containing the input pixel data. In this event, the step of forming persistence pixel data may include the steps of attenuating the display pixel data within the display image frame in accordance with a predetermined scheme to generate persistence pixel data, storing the persistence pixel data in a persistence frame memory, and storing the display pixel data in the persistence frame memory as persistence pixel data to form the persistence image frame.
The present invention also provides an image display method which includes the method of controlling persistence display described above. In this method, the image may be a waveform.
The present invention further provides a modulated image display control circuit for controlling display of an image on a raster scan type display based on an input image frame comprised of a frame of input pixel data. The circuit includes modulated pixel data adding means for adding modulated pixel data to input pixel data within the input image frame to generate display pixel data within a display image frame supplied to the display. In this circuit, the modulated image may be a persistence added image, and the modulated pixel data may be persistence pixel data.
The present invention further provides a persistence display control circuit for controlling display of an image on a raster scan type display based on an input image frame comprised of a fame of input pixel data. The circuit includes persistence data adding means for adding persistence pixel data to input pixel data within the input image frame supplied to the display to generate display pixel data within a display image frame supplied to the display.
According to the present invention, the persistence data adding means may include persistence pixel data forming means connected to receive the display pixel data within the display image frame for forming, from the display pixel data, persistence pixel data within a persistence image frame to be added to the input pixel data within the input image frame during a frame occurring immediately after the input image frame containing the input pixel data, and persistence pixel data adding means connected to receive the persistence pixel data within the persistence image frame from the persistence pixel data forming means and to receive the input pixel data within the input image frame for adding to the input pixel data persistence pixel data within the persistence image frame at a pixel position corresponding to the input pixel data.
According to the present invention, the persistence pixel data forming means may be configured to form the persistence pixel data during a period of the frame immediately after the input image frame containing the input pixel data. In this configuration, the persistence pixel data forming means may include persistence frame memory means for storing the display pixel data within the display image frame, and persistence pixel data forming means connected to receive the display pixel data within the display image frame from the persistence frame memory means for attenuating the display pixel data in accordance with a predetermined scheme to form the persistence pixel data.
Also, according to the present invention, the persistence pixel data forming means may be configured to form the persistence pixel data during a period of the same frame as the input image frame containing the input pixel data. In this configuration, the persistence pixel data forming means may include persistence pixel data forming means for attenuating the display pixel data within the display image frame in accordance with a predetermined scheme to form the persistence pixel data, and persistence frame memory means for storing the persistence pixel data from the persistence pixel data forming means to form the persistence image frame.
Further, according to the present invention, the persistence frame memory means may include a first and a second frame memory, and selecting means for alternately selecting the first and second frame memories as a read frame memory and a write frame memory, respectively, on a frame-by-frame basis. In this event, the selecting means can connect the persistence pixel data adding means to the read frame memory, and connect the persistence pixel data forming means to the write frame memory. In addition, one of the first and second frame memories selected as the read frame memory stores the persistence image frame formed during a frame immediately before the input image frame. The other frame memory of the first and second frame memories selected as the write frame memory stores the persistence image frame for use during a frame occurring immediately after the input image frame. In the next frame, the frame memory selected as the read frame memory is selected as a write frame memory by the selecting means to store the persistence image frame for use during a frame next to the next frame, and the other frame memory selected as the write frame memory is selected as the read frame memory by the selecting means such that the persistence image frame stored in the write frame memory is able to serve as the persistence image frame for the next frame.
The present invention further provides an image display device which includes the persistence display control circuit.
In the following description, the present invention will be described in detail with reference to a number of embodiments.
Referring next to
The persistence data addition unit 30 has an input connected to the output of the capture memory 10, and an output connected to an input of the display 50, and adds a persistence pixel data word to each of input pixel data words, which make up an input image frame received at the input, and then outputs the resulting display pixel data word, as will be later described. The display 50 has an input connected to the output of the persistence data addition unit 30, and a control input connected to receive the synchronization signal from the display timing generator 12. The display 50 may be a raster scan type CRT display or an LCD display, as is the case with the foregoing.
Describing the persistence data addition unit 30 in greater detail, the persistence data addition unit 30 generally comprises a persistence pixel data word addition unit 300; a persistence pixel data word formation unit 302; a persistence frame memory pair unit 304; a frame memory selector 306; an address generator unit 308; and a memory switching timing generator 310. More specifically, the persistence pixel data word addition unit 300 comprises, for example, an adder 3000 which has an input for receiving an input pixel data word from the capture frame memory 10; another input for receiving a persistence pixel data word from the selector 306; and an output for generating the display pixel data word resulting from the addition of the two inputs. The persistence pixel data word formation unit 302 comprises, for example, a subtractor 3020 which has an input connected to the output of the adder 3000 for receiving a display pixel data word from the adder 3000, and attenuates the received pixel data word in a predetermined attenuation sequence to form a persistence pixel data word. For example, the attenuation sequence may include subtracting the same amount from the received pixel data word each time, whereas the attenuation may be implemented by another scheme (for example, a scheme of using a lookup table for providing, for example, a non-linear attenuation characteristic). The persistence pixel data word thus formed is generated at the output of the subtractor 3020. The output of the subtractor 3020 is next connected to the persistence frame memory pair unit 304 through the frame memory selector 306. More specifically, the frame memory selector 306 comprises an input switch 3060 and an output switch 3062. The input switch 3060 has an input terminal connected to the output of the subtractor 3020, and two output terminals a, b. The output switch 3062 in turn has two input terminals a, b and one output terminal which is connected to the other input of the adder 3000. These two switches 3060, 3062 each have a control input such that they are switched to their respective terminals a or b depending on a signal at the control inputs.
The memory switching timing generator 310 comprises a memory switching timing generator 3100 which has an input connected to the output of the display timing generator 12 for receiving the synchronization signal, and generates a memory switching control signal at an output. The memory switching control signal inverts the state every frame period based on the synchronization signal. The switches 3060, 3062 switch between the terminals a and b, as described above, in response to the memory switching control signal.
The persistence frame memory pair unit 304 comprises two persistence frame memories 1, 2. Each of the frame memories 1, 2 has a capacity of one frame of persistence pixel data words, i.e., a persistence image data frame.
The persistence frame memory 1 has a data input terminal connected to the output terminal a of the input switch 3060 for receiving an input, and a data output terminal connected to the input terminal b of the output switch 3062 for generating an output. The persistence frame memory 2 in turn has a data input terminal connected to the output terminal b of the input switch 3060 for receiving an input, and a data output terminal connected to the input terminal a of the output switch 3062 for generating an output. As a result, when the respective switches 3060, 3062 are in a first state, i.e., on the a side, the persistence frame memory 1 functions as a write frame memory while the persistence frame memory 2 functions as a read frame memory. On the other hand, when the respective switches 3060, 3062 are in a second state, i.e., on the b side, the persistence frame memory 1 functions as a read frame memory while the persistence frame memory 2 functions as a write frame memory. In this way, by using the two frame memories alternately for writing and reading every frame period, a read of a persistence image frame for use with a current frame can be performed simultaneously with a write of a persistence image frame for use with the next frame. Each of the frame memories 1, 2 has an address input for receiving an address for writing and reading.
The address generator unit 308 comprises an address generator 3080; and two sets of address switches 3082, 3086 and delays 3084, 3088. A first set of address switch 3082 and delay 3084 is associated with the persistence frame memory 1, while a second set of address switch 3086 and delay 3088 is associated with the persistence frame memory 2. More specifically, the address generator 3080 has an input connected to the output of the display timing generator 12 for receiving the synchronization signal, and generates address signals at an output for sequentially addressing memory locations in the associated frame memory. The address switch 3082 in the first set has two input terminals a, b and one output terminal. The input terminal a is directly connected to the output of the address generator 3080; the input terminal b is connected to the output of the address generator 3080 through the delay 3084; and the output terminal is connected to the address input of the persistence frame memory 1. The delay 3084 provides a delay equal to a delay caused by the adder 3000 and subtractor 3020, such that an address for reading from the frame memory is used as an address for writing into the frame memory by delaying the read address by the delay time.
Thus, the input terminal a functions as a terminal for receiving an address for reading from the persistence frame memory 1, and the input terminal b functions as a terminal for receiving an address for writing into the persistence frame memory 1. The address switch 3082 has a control input which is connected to the output of the memory switching timing generator 310 for receiving the memory switching control signal. In this way, the address switch 3082 switches to the a side or to the b side depending on the state of the memory switching control signal.
Similarly, the second set of address switch 3086 and delay 3088 has substantially the same configuration as the first set, except that the delay 3088 is connected to the input terminal a of the switch 3086. This is because the persistence frame memory 2 is operated reverse to the write/read operations of the persistence frame memory 1.
Next, operation of the image display device B having the foregoing configuration will be described with reference to
Describing the operation in greater detail, during the frame n, for example, the switches 3060, 3062 are on the b side, while the switches 3082, 3086 are on the a side, causing the persistence frame memory 1 to perform a read operation (
As described above, two persistence frame memories are provided for use in alternate writing and reading of persistence pixel data words, and read/write cycles of the two persistence frame memories are shifted such that they alternately perform a read and a write, thereby enabling persistence pixel data words to be simultaneously written into one persistence frame memory and read from the other persistence frame memory. As a result, a frame period for forming a persistence image frame can be removed from a transmission path from the capture memory 10 to the display 50, thereby increasing data transfer rate from the capture frame memory 10 to the display 50, to display the image substantially in real time.
Next, an image display device C according to another embodiment will be described with reference to
In the embodiments of the present invention described above in detail, a persistence added image has been described as a modulated image, however, as should be understood by those skilled in the art, the present invention can be applied to any arbitrary additional image which must be formed on the basis of an input image. Also, for purposes of description, the predetermined attenuation sequence for forming a persistence pixel data word involves, as one example, decreasing a same amount from a pixel data word each time irrespective of a displayed content. The present invention, however, can employ any other arbitrary type of attenuation sequence or attenuation scheme for providing a variable persistence characteristic.
According to the present invention described above in detail, an improved data transfer rate between the image input and the display in the image display device enables the image display device to display a persistence image more rapidly than before, so that the image can be displayed substantially in real time. The use of the frame memory pair permits the formation of a persistence image to be performed simultaneously with the addition of the persistence image, facilitating a more rapid display of the persistence image. Also, by virtue of improved real time display of an image, when an image captured by a camera is monitored on a waveform monitor, the image can be displayed on the monitor with less delay, thereby reducing discomfort of an operator.
Furthermore, not limited to a persistence added image, the present invention can rapidly display an image to which another modulated image is added.
| Number | Date | Country | Kind |
|---|---|---|---|
| 23437/2002 | Jan 2002 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10353978 | Jan 2003 | US |
| Child | 11468150 | Aug 2006 | US |
