Claims
- 1. A circuit for allowing the transfer of data between first and second data busses, comprising:
- a first buffer for coupling packets from said second bus to said first bus, and for generating an empty signal,
- a second buffer for coupling packets from said first bus to said second bus, and for generating a full signal,
- a source device for transmitting packets of data to said second bus and for generating a source data request signal when said source device requires that data be output,
- a destination device for receiving packets of data from said second bus and for generating a destination data request signal when said destination device requires data to be input,
- means for generating a freeze signal for each device,
- first logic means for receiving said source data request signal, said buffer empty signal and said source device freeze signal, and for generating a first output signal therefrom only if said source device freeze signal is inactive,
- second logic means for receiving said destination data request signal, said buffer full signal and said destination device freeze signal, and for generating a second output signal therefrom only if said destination device freeze signal is inactive, and
- an arbitrator responsive to said first and second output signals for generating an enabling signal for enabling either a transfer of data from said source device to said first buffer or a transfer of data to from said second buffer to said destination device, said arbitrator being further adapted to allow the completion of the transfer of a packet of data when said enabling signal is interrupted by a freeze signal during the transmission of a packet.
Parent Case Info
This application is a continuation-in-part of application Ser. No. 08/259,095, filed Jun. 13, 1994, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5029124 |
Leahy et al. |
Jul 1991 |
|
5191581 |
Woodbury et al. |
Mar 1993 |
|
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
259095 |
Jun 1994 |
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