Circuit for Heartbeat Detection and Beat Timing Extraction

Abstract

A circuit and method for long term electrocardiogram (ECG) monitoring is implemented with the goal of reducing power consumption, battery size, and consequently device size. In one embodiment, the integrated circuit includes an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell in communication with the output of the amplifier cell; a baseline amplifier cell in communication with the output of the amplifier cell; a comparator cell having a first input terminal in communication with the output terminal of the QRS amplifier cell; and a VDC cell having an input in communication with the output of the baseline amplifier cell and an output in communication with the second input terminal of the comparator cell, wherein the comparator cell generates an output pulse in response to the output signal from the amplifier cell and the output signal from the baseline amplifier cell.

Description

FIELD OF THE INVENTION

This invention relates generally to heartbeat monitors and more specifically to portable, wearable heartbeat monitors.

BACKGROUND OF THE INVENTION

Referring to FIG. 1, traditionally the circuit topology for heartbeat detection circuit 10 known to the prior art consists of a low noise instrumentation amplifier (IA) 14, an anti-alias filter 18, an analog-to-digital converter (ADC) 22, and a digital signal processor (DSP) or microcontroller 26. This topology is generally employed in a wearable clinical heart monitor.

In this topology, the IA 14 amplifies the differential Electrocardiogram (ECG) signal derived from patient electrodes, using low noise operational amplifiers (op-amps) to minimize the addition of circuit noise. The gain of the IA 14 is set so that the amplified output is not saturated. The output signal from the IA next passes through the anti-alias filter 18, and then the ADC 22 uniformly quantizes the ECG signal, treating small features such as ECG's P wave and large features such as ECG's R wave with equal resolution. The ADC 22 is usually implemented with a medium resolution successive approximation register (SAR) architecture to minimize power consumption. Finally, to detect heartbeats, the digitized ECG is processed by the microprocessor 26 using a peak detection algorithm to detect R-waves. Depending on the computational power of the available microprocessor or DSP 26, such an algorithm ranges from a simple thresholding algorithm to one employing wavelet transforms.

This traditional topology is necessary for clinical ECG measurements, where multilead or multielectrode ECG signals are acquired with high quality in order to diagnose complex arrhythmias. These recordings are usually quantized with at least 12 bits to preserve the finer details of the P wave of the ECG. The American Heart Association recommends that the ADC use a sampling frequency of at least 150 Hz to capture all features, while stating that a bandwidth of 1 Hz to 30 Hz generally produces a stable ECG without digitization artifacts.

However, for applications employing the wearable heart monitor, generally only the R-wave timing is relevant. What is needed is a monitor that will provide this timing while removing the need for ADC and signal processing and thereby significantly decreasing the circuit's power requirements and size while robustly extracting heartbeat timings in the presence of motion artifacts and degraded signal quality.

The present invention addresses this need using a new topology for the heartbeat detection circuit.

SUMMARY OF THE INVENTION

In one aspect, the invention relates to an integrated circuit for heartbeat detection. In one embodiment, the integrated circuit includes an amplifier cell, such as a PGA amplifier cell, having a plurality of input terminals and an output terminal; a QRS amplifier cell having an input terminal and an output terminal, the input terminal of the QRS amplifier cell in communication with the output terminal of the amplifier cell; a baseline amplifier cell having an input terminal and an output terminal, the input terminal of the baseline amplifier cell in communication with the output terminal of the amplifier cell; a comparator cell having a first input terminal and a second input terminal and an output terminal, the first input terminal of the comparator cell in communication with the output terminal of the QRS amplifier cell; and a V_DC cell having a first input terminal in communication with the output terminal of the baseline amplifier cell and an output terminal in communication with the second input terminal of the comparator cell, wherein the amplifier cell outputs an output signal on the output terminal of the amplifier cell in response to input signals input to the input terminals of the amplifier cell, and wherein the comparator cell generates an output pulse in response to the output signal from the QRS amplifier cell and the output signal from the V_DC cell.

In another embodiment, the V_DC cell has a second input terminal, and the integrated circuit further includes a microcontroller cell having an input terminal in communication with the output terminal of the comparator cell and an output terminal in communication with the second input terminal of the V_DC cell.

In another aspect, the invention relates to a method for detecting a heartbeat. In one embodiment, the method includes the steps of amplifying a signal from an ECG electrode to form an amplified ECG signal; amplifying the amplified ECG signal with an amplifier having a bandwidth of 20-40 Hz to form a QRS signal; amplifying the amplified ECG signal with an amplifier having a bandwidth of 1 Hz to generate baseline voltage; adding a DC offset to the baseline to form an offset baseline; comparing the QRS signal to the offset baseline; and generating an output signal if the QRS signal is greater than the offset baseline. In another embodiment, the method further includes adjusting the amplification value of the ECG electrode signal. In yet another embodiment, the timing of an R-wave is estimated in response to measuring the midpoint timing of its corresponding digital output pulse.

In yet another aspect, the invention relates to a method of selecting a DC offset. In one embodiment, the method includes the steps of (a.) setting a DC voltage to a predetermined value; (b.) comparing an amplified filtered ECG signal to the sum of a baseline signal and DC voltage to produce an output signal; (c.) if the output signal is not a series of regularly spaced pulses of 40 ppm to 180 ppm then incrementing the DC voltage; (d.) iteratively repeating steps b and c until the output signal is a series of regularly spaced pulses of 40 ppm to 180 ppm.; and (e.) setting the DC offset at the value of the DC voltage.

In still yet another aspect, the invention relates to a method of selecting an offset baseline. In one embodiment, the method includes the steps of (a.) determining the peak voltage of an R-wave of a heartbeat; (b.) determining a baseline DC voltage; and (c.) calculating one-half the difference between the baseline DC voltage and peak voltage of the heartbeat and adding the baseline DC voltage to obtain the offset baseline.

In another aspect, the invention relates to a detection device that, in one embodiment, includes an amplifier cell having a plurality of input terminals and an output terminal; a signal amplifier cell having an input terminal and an output terminal, the input terminal of the signal amplifier cell in communication with the output terminal of the amplifier cell; a baseline amplifier cell having an input terminal and an output terminal, the input terminal of the baseline amplifier cell in communication with the output terminal of the amplifier cell; a comparator cell having a first input terminal and a second input terminal and an output terminal, the first input terminal of the comparator cell in communication with the output terminal of the signal amplifier cell; and a V_DC cell having a first terminal in communication with the output terminal of the baseline amplifier cell and a second terminal in communication with the second input terminal of the comparator cell, wherein the amplifier cell outputs an output signal on the output terminal of the amplifier cell in response to input signals input to the input terminals of the amplifier module, and wherein the comparator cell generates an output pulse in response to the output signal from the signal amplifier cell and the output signal from the V_DC cell. In another embodiment, the signal at the input of the amplifier is one of a PPG, a BCG and a respiration signal.

In yet another aspect, the invention relates to a method for detecting a periodic signal comprising the steps of amplifying a signal from a signal source to form an amplified signal; amplifying the amplified signal with an amplifier having a bandwidth of sufficient to form a filtered amplified signal with the highest frequency pulsatile features of amplified signal preserved; amplifying the amplified signal with an amplifier having a bandwidth sufficient to preserve the baseline while removing the pulsatile components; adding a DC offset to the baseline to form an offset baseline; comparing the filtered amplified signal to the offset baseline; and generating an output signal if the filtered amplified signal is greater than the offset baseline. In one embodiment, the bandwidth of the baseline is 1 Hz. In another embodiment, the bandwidth of the baseline is 0.05 Hz.

BRIEF DESCRIPTION OF THE DRAWINGS

The structure and function of the invention can be best understood from the description herein in conjunction with the accompanying figures. The figures are not necessarily to scale, emphasis instead generally being placed upon illustrative principles. The figures are to be considered illustrative in all aspects and are not intended to limit the invention, the scope of which is defined only by the claims.

FIG. 1 is a standard topology of a heartbeat detection circuit known to the prior art;

FIG. 2 is an embodiment of a new topology for ECG heartbeat detection with voltage nodes labeled as constructed in accordance with the invention;

FIG. 3( a) is a series of matched time waveforms illustrating the QRS complex, baseline, and V_Baseline with V_DC offset;

FIG. 3( b) is an embodiment of a digital output corresponding to the waveforms in FIG. 3(a) and measured by the system of FIG. 2 when the baseline is set at b1;

FIG. 3( c) is an embodiment of a digital output corresponding to the waveforms in FIG. 3(a) and measured by the system of FIG. 2 when the baseline is raised to b2 in FIG. 3a;

FIGS. 4( a) and 4(b) are flow charts of embodiments of the calibration of the system at startup (4(a)) and runtime (4(b)) accomplished by raising the baseline;

FIG. 5 is a flowchart of an embodiment of the calibration of the system using the accelerated process;

FIG. 6 is a block diagram of an embodiment of the circuit components for an ECG ASIC, constructed in accordance with the invention;

FIG. 7 is a schematic diagram of an embodiment of a V_DC generator constructed in accordance with the invention;

FIG. 8( a) is a diagram of the operation of the V_DC generator of FIG. 7 during clock phase Φ_b;

FIG. 8( b) is a diagram of the operation of the V_DC generator of FIG. 7 during clock phase Φ;

FIG. 9 is a diagram of the switch configurations of a portion of the V_DC generator of FIG. 7 showing that the sign of C_VDC can be flipped during phase Φ_b in case of reversed electrodes;

FIG. 10 is graph of gain response and noise response of an embodiment of a PGA-QRS Amp signal path measured using an Agilent 35670A Dynamic Signal Analyzer;

FIG. 11 is a comparison graph of an embodiment of the PGA-QRS Amp's Noise efficiency Factor (NEF) plotted against other published biopotential amplifiers;

FIG. 12( a) is a chest ECG taken with a subject at rest (gain=52 dB);

FIG. 12( b) is the output signal of the device of FIG. 3 of the ECG of FIG. 12a;

FIG. 13( a) is a chest ECG with baseline drift due to motion of the subject (gain=52 dB);

FIG. 13( b) is the output signal of the device of FIG. 3 of the ECG of FIG. 13(a);

FIG. 14( a) is a chest ECG with muscle artifacts and signal clipping (gain=64 dB);

FIG. 14( b) is the output signal of the device of FIG. 3 of the ECG of FIG. 14(a);

FIG. 15( a) is an ear-neck ECG with high gain and low SNR (gain=84 dB);

FIG. 15( b) is the output signal of the device of FIG. 3 of the ECG of FIG. 15(a); and

FIG. 16 is a graph indicating how R-wave-timing may be estimated from midpoint timing measurements.

DESCRIPTION OF A PREFERRED EMBODIMENT

The proposed new circuit topology is based on the fact that heartbeat detection relies on QRS complex of the ECG, which has a higher frequency content and a greater magnitude than adjacent ECG features. A generalized embodiment of this circuit topology 40 is shown in FIG. 2, along with a general illustration of the ECG waveform (FIG. 3(a)) and the output of the circuit (FIG. 3(b and c)).

In FIG. 2, a differential ECG signal is first amplified by a low noise gain amplifier 44. In one embodiment, the gain amplifier is a programmable gain amplifier, or PGA. The output signal of the amplifier 44 is split into two paths. The first signal path is to an amplifier termed a “QRS Amp” 48, which has a bandwidth of 20 Hz to 40 Hz that preserves the signal structure of the QRS complex. The second signal path is to an amplifier termed a “Baseline Amp” 52, which is a low pass filter amplifier with an equal gain but a lower bandwidth than the QRS Amp 48. This Baseline Aamp 52, which has a bandwidth of about 1 Hz, preserves only the low frequency baseline drift in the ECG signal caused by motion artifacts. If respiration is the signal, then a bandwidth of about 0.05 is used to remove the respiration signals from baseline

A positive inline DC offset V_DC 54 is added to the output (V_Baseline) of the Baseline Amp 52 to create an adaptive threshold signal equal to (V_Baseline+DC) using a V_DC circuit described in detail below. Using this threshold value, a QRS complex (or heartbeat) is detected whenever V_QRS>V_Baseline+DC. In this circuit, this comparison is performed by a comparator 56, which consequently pulses a high output signal (D_OUT) when a heartbeat is detected.

To correctly set the DC offset voltage (V_DC), the DC offset voltage is incremented until the period between D_OUT pulses is regular and is in the range of human beat-to-beat interval. As shown in FIG. 3(a), there is a wide range of valid V_DC values since V_DC can be set at any signal voltage level between the R-wave voltage level and the voltage level of the next highest feature (usually the T-wave). Referring to FIGS. 3(a) and 3(b), with the baseline originally set at (b1) (shown here at about 0.1V), multiple peaks (ps1-ps7) in the signal(s) (FIG. 3(a)) would generate pulses (ps1′-ps7′) at the output D_OUT of the circuit (FIG. 3(b)). These pulses are irregular in time and would not be considered to correspond to a series of heartbeat pulses. Next, the V_DC voltage value is iteratively increased and fewer and fewer peaks in the signal(s) trigger the output signal pulses. These step increases continue until at some value (b2) (FIG. 3(a)), the output signal D_OUT is reduced to a regular time series of pulses (ps1, ps4, ps7) as shown in FIG. 3(c).

This V_DC voltage value is set initially by an off chip microcontroller 60 (FIG. 2) at the beginning of measurement, and the calibration routine generally takes less than one minute. The external microcontroller 60 then is powered off after the calibration is complete, or until the time series of the pulses at the output D_OUT become irregular again and a recalibration has to be done. The pulses can become irregular for multiple reasons such as a change in position of the patient, as shown in the ECGs below. The microprocessor 60 includes configuration registers to load 77 bits of configuration settings into the ASIC using shift registers. The shift registers are modified to be able to serially read out internal bits for verification. The configuration settings include: C_OUT settings (7 bits), C_VDD settings (4 bits), and reverse V_DC (1 bit).

Referring to FIG. 4(a), during initial setup, the microprocessor 60 sets V_DC=0 (Step 1). The output D_OUT is checked to determine if the pulses of D_OUT are both regularly spaced and within the range of 40-180 pulses per minute (ppm) (Step 2). If not, V_DC is incremented (or decremented if the electrodes are reversed) (Step 3) and the output D_OUT is checked to determine if the pulses of D_OUT are both regularly spaced and within the range of 40-180 pulses per minute (ppm) (Step 2) again. These steps are repeated until the pulses of D_OUT are both regularly spaced and within the range of 40-180 pulses per minute (ppm). At this point, V_DC is incremented slightly as a safety margin (Step 4) and calibration is complete (Step 5). The pulses per minute (ppm) now correspond to the beats per minute (bpm).

Referring to FIG. 4(b), at runtime, the microprocessor 60 sets V_DC equal to the previous value set during calibration (Step 6). The output D_OUT is checked to determine if the pulses of D_OUT are irregularly spaced, or outside the range of 40-180 pulses per minute (ppm), and have been so for ten seconds (Step 7). If yes, then if the pulses are less than 40 per minute, V_DC is decremented (or incremented if the electrodes are reversed) (Step 8). If the pulses are greater than 180 per minute, V_DC is incremented (or decremented if the electrodes are reversed) (also Step 8). In both cases, the output D_OUT is checked to determine if the pulses of D_OUT are irregularly spaced and outside the range of 40-180 pulses per minute (ppm) and have been so for ten seconds (Step 7) again. These steps are repeated until the pulses of D_OUT are both regularly spaced and within the range of 40-180 beats per minute (ppm). At this point, V_DC calibration is complete (Step 9).

Alternatively, the above method of setting V_DC can be accelerated if the R-wave peak voltage level is known in advance, in which case V_DC initially can be set at the midpoint between a baseline near zero and R-wave peak voltage. This measurement avoids the region of V_DC where V_Baseline+DC is close to V_Baseline and thus D_OUT is noisy and invalid.

Referring to FIG. 5, the flowchart of the accelerated calibration described above is shown. In (Step 10) the value of V_DC is set as one-half the difference between the peak voltage and the baseline voltage, and this result added to the baseline voltage:

V _DC=(V_peak−V_baseline)/2+V_baseline  (1)

At this point, the calibration is complete (Step 11).

There are several advantages to this new topology in terms of circuit design. First, no signal processor or ADC is required, which significantly further reduces the device power consumption and physical die area. Second, a low voltage supply is possible because a clipped R-wave that exceeds the amplifier's dynamic range still possesses beat information. Third, any comparator offset is automatically compensated for due to the V_DC calibration. Fourth, amplifier linearity is unimportant because the signal path is highly nonlinear. In terms of practical usage, this topology is tolerant to motion artifacts because the signal is compared against its own baseline. Furthermore, no predefined subject-dependent parameters are needed.

The function of the V_DC generator 54 (FIG. 6) is to provide a voltage V_DC to add to V_Baseline to produce an adaptive threshold V_Baseline+DC. The schematic of an embodiment of the V_DC generator 54 is shown in FIG. 7.

In more detail, C_VDD is a 4-bit binary weighted capacitor bank of capacitors ranging from 15 fF to 155 fF, and C_Gnd is a 7-bit binary weighted capacitor bank of capacitors ranging from 40 fF to 5.1 pF. The C_VDD and C_Gnd values that are to be used are selected during the initial V_DC calibration by the microcontroller 60 (FIG. 2).

Non-overlapping clock phases Φ and Φ_b are generated on-chip at 1.9 kHz by the clock generator 64 (FIG. 6). The clock frequency is chosen as a compromise between low power (which favors lower frequency) and low charge leakage (which favors higher frequency). During clock phase Φ_b (FIG. 7 and FIG. 8a), capacitor banks C_VDD and C_Gnd are reset to V_DD and ground respectively by closing switches 80, 84, 88 and 92 and the opening of switches 96, 100 and 104. During the following clock phase 1 (FIG. 7 and FIG. 8b), capacitor C_VDC is charged to a final voltage of V_DC=V_DDC_VDD/(C_VDD+C_Gnd). During this clock phase Φ (FIG. 8b), switches 80, 84, 88 and 92 are opened and switches 96, 100 and 104 are closed. V_DC is added to V_Baseline to produce V_Baseline+DC, while C_VDD and C_Gnd are again reset. Capacitor C_tank is present to reduce voltage ripples.

In consideration of potential long term at-home usage where the ECG electrodes are applied by the wearer, the V_DC generator has the ability to generate negative V_DC if the user accidentally reverses the electrodes. This is symbolized by the two digital blocks 120, 124 in FIG. 7 and FIG. 9 that can reverse C_VDC during phase Φ_b. In this case, where the ECG polarity is reversed and C_VDC is reversed, then the heartbeat occurs when D_OUT=0 instead of D_OUT=1.

The role of the comparator 56 is to output a digital high (or digital low if electrodes are reversed) when a QRS complex has occurred, that is, when V_QRS>V_Baseline+DC. A dynamic latched comparator is used in one embodiment. The dynamic topology is chosen because it consumes power only when latching.

The ECG's amplification path goes through the amplifier and then QRS Amp. FIG. 10 shows the gain response and input-referred noise response at the highest gain setting in an embodiment using a PGA amplifier. The measured level of noise is compatible with sensing ECG at the head, where the QRS amplitude is approximately 30 μV_pp.

A widely used figure of merit for amplifier power-noise performance is the Noise Efficiency Factor (NEF) which is defined as:

$\begin{array}{cc}\mathrm{NEF}=V_{\mathrm{ni},\mathrm{rms}}\sqrt{\frac{2I_{\mathrm{total}}}{\pi V_{\mathrm{thermal}}4\mathrm{kTBW}}}& \left(2\right)\end{array}$

In Equation (2), V_ni,rms is the input-referred RMS noise voltage, I_total is the total amplifier supply current, and BW is the amplifier bandwidth in Hertz. T is the absolute temperature and V_thermal is equal to kT/q where q is the charge on the electron and k is the Boltzmann constant. This value is about 25 mV at room temperature. The NEF for the PGA-QRS Amp circuit blocks is 5.7. FIG. 11 compares the ECG ASIC's amplifier performance with published biopotential front-end amplifiers, where it is the lowest powered amplifier with an NEF of less than 10.

FIGS. 12( a) to 15(b) show measured ECG and digital outputs from various wearable ECG scenarios to demonstrate the ASIC's robustness in the presence of baseline drift, muscle artifacts, and attenuated signal. In FIG. 12(a), the at-rest chest ECG signal offers 1.8 mV_pp of stable signal. Here, V_DC is set to 0.3V so that V_Baseline+DC is approximately half of the V_QRS amplitude. However, any V_DC setting between 0.1 V and 0.65V would produce the correct digital QRS output at D_OUT shown in FIG. 12(b). In FIG. 13(a), the chest ECG contains significant baseline drift due to patient motion. Despite the baseline drift, the same V_DC setting as in FIG. 9(a) results in a correct D_OUT (FIG. 13(b)). In fact, any V_DC setting between 0.1 V-0.5V would suffice. This demonstrates the ASIC's tolerance to motion artifacts because its adaptive threshold V_Baseline+DC tracks the baseline drift.

In FIG. 14(a), pectoral muscle artifacts are present from a rapid horizontal 90° arm movement. Also, the higher gain of 64 dB increases the amplified ECG to 2.8V_pp, which is beyond V_DD=0.8V and is clipped. To produce the correct D_OUT (FIG. 14(b)), V_DC needs to be increased to 0.5V so that V_Baseline+DC rises above V_QRS's muscle artifacts and heightened T-waves. The QRS complex's clipping does not matter because the beat information is still present.

In FIG. 15(a), the ECG is measured across the ear and the middle-upper neck. The gain is increased to 84 dB to sense the 30 p V_pp of ear ECG. At this high gain, a significant portion of the amplified output is noise and QRS clipping is present. However, with the identical V_DC setting as in FIGS. 12 and 13, V_Baseline+DC is able to rise above the noise and allow the correct capture of QRS complexes as shown by D_OUT (FIG. 15(b)).

Accurate ECG R-wave timing is necessary for calculations of pre-ejection period (PEP) and pulse arrival time (PAT) for cuffless blood pressure estimation and for calculations of RR intervals for heart rate variability (HRV) analysis. Although the R-wave is clipped and its peak is lost in the eventual digital output D_OUT, this section shows that the original R-wave timing can be recovered with minimal error.

R-wave timing can be estimated from the midpoint timing of D_OUT pulses. This method was tested on normal chest ECG records from ten subjects totaling 2,304 heartbeats. Subjects 1 to 5 were from the MIT-BIR PhysioNet database, and Subjects 6 to 10 were from a MIT clinical test. Estimated R-wave timings are compared with manually annotated timings. The results for all ten subjects are summarized in Table 1.

The mean R-wave timing error arises from the fact that the QR slope may be different from the RS slope, thus resulting in the R-wave not being exactly at the midpoint. The mean R-wave timing error for nine out of ten of the subjects is within the sampling period (4 ms and 2 ms). In six out of ten subjects, the estimation is accurate to within 1 ms of the actual R-wave timing. The standard deviation of R-wave timing error is mainly due to time quantization caused by sampling. As expected, when the sampling frequency is doubled for subjects 6 to 10, the standard deviation of R-wave timing error approximately halves. In nine out of ten subjects, the standard deviation of R-wave timing error is less than half of the sampling period. In summary, the R-wave midpoint estimation method is an accurate way to recover the ECG peak timing information from D_OUT. This enables the use of the ECG ASIC for applications beyond heartbeat detection, such as cuffless blood pressure estimation and HRV analysis, both of which require accurate R-wave timings.

It should be noted that this circuit, although presented for ECG sensing, can also be applied to other physiological signals that are pulsatile in shape and are synchronous with periodic physiological functions. Such an application of the circuit can extract periodic events such as heartbeat or respiration using non-ECG signals such as PPG, BCG, and respiration.

Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations can be used by those skilled in the computer and software related fields.

Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “comparing”, “generating” or “determining” or “committing” or “checkpointing” or “interrupting” or “handling” or “receiving” or “buffering” or “allocating” or “displaying” or “flagging” or Boolean logic or other set related operations or the like, refer to the action and processes of a computer system, or electronic device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's or electronic devices' registers and memories into other data similarly represented as physical quantities within electronic memories or registers or other such information storage, transmission or display devices.

The aspects, embodiments, features, and examples of the invention are to be considered illustrative in all respects and are not intended to limit the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and usages will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.

It should be understood that the order of steps or order for performing certain actions is immaterial so long as the present teachings remain operable. Moreover, two or more steps or actions may be conducted simultaneously.

It is to be understood that the figures and descriptions of the invention have been simplified to illustrate elements that are relevant for a clear understanding of the invention, while eliminating, for purposes of clarity, other elements. Those of ordinary skill in the art will recognize, however, that these and other elements may be desirable. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the invention, a discussion of such elements is not provided herein. It should be appreciated that the figures are presented for illustrative purposes and not as construction drawings. Omitted details and modifications or alternative embodiments are within the purview of persons of ordinary skill in the art.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. A heartbeat detection device comprising: an amplifier cell having a plurality of input terminals and an output terminal;a QRS amplifier cell having an input terminal and an output terminal, the input terminal of the QRS amplifier cell in communication with the output terminal of the amplifier cell;a baseline amplifier cell having an input terminal and an output terminal, the input terminal of the baseline amplifier cell in communication with the output terminal of the amplifier cell;a comparator cell having a first input terminal and a second input terminal and an output terminal, the first input terminal of the comparator cell in communication with the output terminal of the QRS amplifier cell; anda VDC cell having a first terminal in communication with the output terminal of the baseline amplifier cell and a second terminal in communication with the second input terminal of the comparator cell,wherein the amplifier cell outputs an output signal on the output terminal of the amplifier cell in response to input signals input to the input terminals of the amplifier module,wherein the comparator cell generates an output pulse in response to the output signal from the QRS amplifier cell and the output signal from the VDC cell.

2. The heartbeat detection circuit of claim 1, wherein the VDC cell has a second input terminal, andwherein the device further comprises; a microcontroller cell having an input terminal in communication with the output terminal of the comparator cell and an output terminal in communication with the second input terminal of the VDC cell.

3. The heartbeat detection circuit of claim 1 wherein the amplifier is a PGA amplifier.

4. A method for detecting a heartbeat comprising the steps of: amplifying a signal from an ECG electrode to form an amplified ECG signal;amplifying the amplified ECG signal with an amplifier having a bandwidth of 20-40 Hz to form a QRS signal;amplifying the amplified ECG signal with an amplifier having a bandwidth of 1 Hz to generate baseline voltage;adding a DC offset to the baseline to form an offset baseline;comparing the QRS signal to the offset baseline; andgenerating an output signal if the QRS signal is greater than the offset baseline.

5. The method of claim 4 further comprising adjusting the amplification value of the ECG electrode signal.

6. The method of claim 4 wherein the timing of an R-wave is estimated in response to measuring the midpoint timing of the corresponding digital output pulse.

7. A method of selecting a DC offset comprising the steps of: a. setting a DC voltage to a predetermined value;b. comparing an amplified filtered ECG signal to the sum of a baseline signal and the DC voltage to produce an output signal;c. if the output signal is not a series of regularly spaced pulses of 40 ppm to 180 ppm then incrementing the DC voltage;d. iteratively repeating steps b and c until the output signal is a series of regularly spaced pulses of 40 ppm to 180 ppm; ande. setting the DC offset at the value of the DC voltage.

8. A method of selecting an offset baseline comprising the steps of: a. determining the peak voltage of an R-wave of a heartbeat;b. determining a baseline DC voltage; andc. calculating one half the difference between the baseline DC voltage and peak voltage of the heartbeat and adding the baseline DC voltage to obtain the offset baseline.

9. A detection device comprising: an amplifier cell having a plurality of input terminals and an output terminal;a signal amplifier cell having an input terminal and an output terminal, the input terminal of the signal amplifier cell in communication with the output terminal of the amplifier cell;a baseline amplifier cell having an input terminal and an output terminal, the input terminal of the baseline amplifier cell in communication with the output terminal of the amplifier cell;a comparator cell having a first input terminal and a second input terminal and an output terminal, the first input terminal of the comparator cell in communication with the output terminal of the signal amplifier cell; anda VDC cell having a first terminal in communication with the output terminal of the baseline amplifier cell and a second terminal in communication with the second input terminal of the comparator cell,wherein the amplifier cell outputs an output signal on the output terminal of the amplifier cell in response to input signals input to the input terminals of the amplifier module,wherein the comparator cell generates an output pulse in response to the output signal from the signal amplifier cell and the output signal from the VDC cell.

10. The system of claim 9 wherein the signal at the input of the amplifier is one of a PPG, a BCG and a respiration signal.

11. A method for detecting a periodic signal comprising the steps of: amplifying a signal from a signal source to form an amplified signal;amplifying the amplified signal with an amplifier having a bandwidth sufficient to form a filtered amplified signal with highest frequency pulsatile features of amplified signal preserved;amplifying the amplified signal with an amplifier having a bandwidth sufficient to preserve the baseline while removing the pulsatile components;adding a DC offset to the baseline to form an offset baseline;comparing the filtered amplified signal to the offset baseline; andgenerating an output signal if the filtered amplified signal is greater than the offset baseline.

12. The method of claim 11 wherein the bandwidth is 1 Hz.

13. The method of claim 11 wherein the bandwidth is 0.05.