CIRCUIT FOR IMPROVING CLOCK RATES IN HIGH SPEED ELECTRONIC CIRCUITS USING FEEDBACK BASED FLIP-FLOPS

Abstract

A flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.

Description

FIELD OF THE INVENTION

The present invention relates to a circuit for enhancing clock rates in high speed electronic circuits.

BACKGROUND OF THE INVENTION

Modern electronic products, including, for example, consumer electronics, computers, telecommunication equipment and automobile electronics use flip-flop circuits to store data during data processing operations. Flip-flop circuits are bistable circuits having output signals assuming one of two stable states based on a signal level or signal transition of an input signal.

D-Flip-Flop, also known as data-Flip-Flop is a fundamental circuit block in digital logic circuits and is quite frequently used block in transmitters and receivers. However, transmitters and receivers are still electrical in nature and do not work at very high speed, for example emerging optical links target more than 100 Gb/s capacities. This speed limitation is primarily from the circuits of the receiver and transmitter involved in communication links. Accordingly, the channel bandwidth is underutilized. However, if transmitters and receivers can work at high speed then the available channel may be utilized efficiently. To achieve a high speed of more than 100 Gb/s, Bi-CMOS technologies can be used; however due to their high cost they are usually not taken into account. CMOS technologies are good replacement of Bi-CMOS technologies but are slow in nature.

D-Flip-Flops with master-slave configuration are generally used in high speed applications. The present master-slave flip-flop comprises a master latch and a slave latch having respective data inputs, data outputs, and clock inputs, with the data output of the master latch connected to the data input of the slave latch. The data input of the master latch is the flip-flop's data input, and the data output of the slave latch is the flip-flop's data output.

In high speed application the devices are generally made wide to carry large amount of current which increases the input capacitance. D-Flip-Flops are also driven by source which has finite output impedance. These factors such as parasitic resistances and capacitances lead to input data having inter-symbol interference in D-Flip-Flops. It causes erroneous output and jitter.

Furthermore, inverter delays and switching delays in relation to the clock signal transitions, referred to as setup and hold delays, limit the speed at which a latch is able to setup and hold data represented in the input signal. Conventional latches have setup and hold delays of typically several picoseconds. In other words, there is an interval of several picoseconds before a clock signal transitions from a sample period to a hold period, wherein no change in the output signal would likely occur despite a change in the input signal. As a result, conventional latches are undesirably limited to processing signals having higher data rates.

In communication links such as serializers/deserializers, clock to data recovery (CDR) circuits, frequency dividers, delay elements etc., inductive peaking, active feedback technique, capacitive degeneration, T-coil techniques etc. are generally used to increase speed of high speed modules. However such modifications are neither cost effective nor do they provide a required result in an efficient manner.

Nevertheless, a need exists in the electronic industry to process data at even greater data rates.

SUMMARY OF THE INVENTION

Accordingly, the present invention in one aspect provides a flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.

In another embodiment, the present invention provides a latch having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: an amplifier stage whose input terminal is the input terminal of the latch and the output terminal is the output terminal of the latch; a positive feedback stage connected to the output terminal of the latch; and a feedback path that adds signal to the input of the latch from the output of the latch.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will be made to embodiments of the invention, examples of which may be illustrated in accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.

FIG. 1 is a block diagram of circuit according to present invention;

FIG. 2 is a simulation result with input data at 11.9 Gb/s data rate;

FIG. 3 is a block diagram of D-Flip-Flop based on feedback based latches;

FIG. 4 is a schematic view of D-Flip-Flop based on feedback latches according to present invention;

FIG. 5 a is a block diagram of latch according to present invention;

FIG. 5 b shows equivalent circuit of the block diagram described in FIG. 4a;

FIG. 6 is an equivalent circuit at the input of latch described in FIG. 4a;

FIG. 7 is a time domain waveform for transparent mode of conventional latch and feedback based latch for ζ=0.7;

FIG. 8 is a frequency domain waveform for various ζ for second order equations;

FIG. 9 is a simulation result with input data at 12.2 Gb/s data rate;

FIG. 10 is a block diagram of feedback based D-Flip-Flop using feedback based latches;

FIG. 11 is a simulation result with input data at 13.5 Gb/s data rate;

FIG. 12 is an eye diagram of feedback based D-Flip-Flop using feedback based latches output (13.5 Gb/s data rate, jitter_pp=3.6 ps and eye opening=300 mv);

FIG. 13 is a block diagram of 2⁷−1 PRBS generator;

FIG. 14 a is simulation result at 10.6 Gb/s data rate

FIG. 14 b is an eye diagram of XOR output at 10.6 Gb/s data rate (jitter_pp=4 ps in the conventional PRBS generator and eye opening=160 mv);

FIG. 15 is a block diagram of equalized XOR and D-Flip-Flop;

FIG. 16 a is a simulation result at XOR output node;

FIG. 16 b is a simulation results after D-Flip-Flop output node

FIG. 16 c is an eye diagram of compensated XOR, D-Flip-Flop at 10.6 Gb/s data rate (jitter_pp=3.5 ps and eye opening=240 my in the proposed PRBS generator);

FIG. 17 a is a simulation result of 2⁷−1 PRBS generator (complete 127 cycles);

FIG. 17 b is eye diagram for 2⁷−1 PRBS generator at 13 Gb/s data rate (jitter_pp=8 ps and eye opening=200 mv);

FIG. 18 is a block diagram of clock and data recovery circuits with feedback based flip-flops;

FIG. 19 is a simulation result of Hogge phase detector based CDR circuit;

FIG. 20 is a block diagram of Serializer;

FIG. 21 is a block diagram of Deserializer.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to circuit for enhancing clock rates in a high speed electronic circuits thereby improving the performance of high speed communication links.

Finite output impedance of the source and large input capacitance in a conventional D-Flip Flop forms a low pass filter. To nullify the effect of this low pass filter, a high pass filter is needed. According to the present invention, this high pass filter is implemented by a negative feedback across D-Flip-Flop. Each D-Flip-Flop of communication systems are thus used to equalize previous erroneous data which forms distributed equalizer so additional power hungry equalizers requirement is relaxed.

FIG. 1 is a block diagram of circuit according to present invention. As shown in the circuit, negative feedback loop 102 is connected across a conventional D-Flip-Flop 104 according to present invention to adjust or correct or enhance the clock input of the D-Flip-Flop. Negative feedback across D-Flip-Flop also mitigates timing errors which is caused by RC delay at the input of D-Flip-Flop.

FIG. 2 is a simulation result using the circuitry described in FIG. 1 with input data at 11.9 Gb/s data rate. FIG. 2a shows an input data at 11.9 Gb/s data rate. FIG. 2b shows the result of a conventional D-Flip-Flop wherein data rate of 11.9 Gb/s is not resolved. FIGS. 2c and 2d shows that D-Flip-Flop according to present invention is working fine with 200 mV input data in same simulation conditions. FIG. 2d relates to eye diagram of D-Flip-Flop according to present invention showing 326 mV eye opening with Ips jitter_pp. It may be noted that any adaptive algorithm for finding feedback coefficient of feedback e.g. least square algorithm, least mean square algorithm may be implemented. The feedback can be adaptive, based on load conditions i.e. the feedback coefficient is adjusted based on adaptive algorithms.

In another embodiment of the present invention, circuit according to present invention is a master slave configuration. FIG. 3 shows a master-slave configuration of D-Flip-Flop according to present invention. There are two CML latches 302; 304 having respective local feedback 306; 308. Each latch 302; 304 in a master-slave configuration have two modes of operation, transparent mode and latch mode. In, D-Flip-Flop when clock is high, master latch is in transparent mode and slave latch is in latch mode and vice-versa. As mentioned, local negative feedback 306; 308 is employed in each of the D-Flip-Flop. In transparent mode, it will cause 2-stage amplification using amplifying stage. Here, it is shown as a buffer 310; 312 but it can be any g_m cell. For two stage amplifiers, the overall dc gain and the bandwidth are obtained by G_T=G² and ω_bw=ω√{square root over (2^1/2−1)}.

FIGS. 1, 3 and 10 particularly describes a flip-flop having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal. The flip-flop comprises two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches. The feedback path may be a path from the output of the flip-flop and added to the input of the flip-flop or a path from the output of the first latch and is added to the input of the flip-flop. The flip-flop described herein may also comprise a first feedback path from the output of the first latch and is added to the input of the flip-flop; and a second feedback path from the output of the flip-flop and is added to the input of the second latch. The feedback path may further comprise a transconductance stage or an inverter stage. The feedback may be a negative feedback and further the strength of feedback can be adapted using a control mechanism.

FIG. 4 is a schematic view of D-Flip-Flop based on feedback latches according to present invention. Figure shows a feedback circuit comprising transistors M5, M6 and M8. Output voltage V_out is fed to the feedback circuit through transistor M6 wherein clock signal Clk− is connected to the transistor M5 whereby when clock signal CLK+ is high then the buffer works and when clock signal CLK− is low then the feedback circuit works.

FIG. 5 a is a block diagram of latch according to present invention comprising an amplifier 401, a positive feedback 402, buffer 404, and a feedback 403. Feedback 403 is a negative feedback according to present invention as described hereinbefore. FIG. 5a describes a latch having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: an amplifier stage whose input terminal is the input terminal of the latch and the output terminal is the output terminal of the latch; a positive feedback stage connected to the output terminal of the latch; and a feedback path that adds signal to the input of the latch from the output of the latch. The feedback path from the output terminal to the input terminal may be a transconductance stage or an inverter stage. The feedback may be a negative feedback and further the strength of feedback can be adapted using a control mechanism.

FIG. 5 b shows equivalent circuit of the block diagram described in FIG. 5a wherein the circuit comprises a latch amplifier 404, latch feedback 405 and buffer 406. FIG. 6 is an equivalent circuit at the input of latch described in FIG. 4a wherein I_in denotes input current, inductance L_s connected with resistance R_s whereas C_p and R_p are parallel capacitance and resistance of the circuit.

Referring to FIGS. 4a and 4b, it gives:

$\begin{array}{cc}-i_{\mathrm{in}}-g_{\mathrm{mf}}V_{\mathrm{out}}+V_1/R_1+V_1C_1s=0& \left(1\right)\\ g_{m2}-V_1+V_{\mathrm{out}}/R_L+V_{\mathrm{out}}C_Ls=0& \left(2\right)\\ \frac{i_{\mathrm{in}}}{V_1}=\frac{\frac{1}{\left(R_L+C_Ls\right)}}{g_{m2}\times g_{\mathrm{mf}}}+\frac{1}{R_1}+{\mathrm{sC}}_1& \left(3\right)\end{array}$

Equation 3 shows an inductive peaking where, R_p=R₁, C_p=C₁,

$R_s=\frac{R_L}{g_{m2}\times g_{\mathrm{mf}}}\mathrm{and}C_s=\frac{C_L}{g_{m2}\times g_{\mathrm{mf}}}.$

Transparent mode shows improvement because it generates inductive peaking at the input of latch. It causes parallel resonance.

$\begin{array}{cc}\frac{V_{\mathrm{out}}}{V_1}=-\frac{g_{m2}}{\left(\frac{1}{R_L}+{\mathrm{sC}}_L\right)}& \left(4\right)\end{array}$

Equation 4 shows gain stage but at the same time, V_out/V_in is determined by FIGS. 5a and 5b. Such an arrangement employs a transconductance stage G_mf to return a fraction of the output to the input of G_m2. The transfer function of the overall amplifier is given by:

$\begin{array}{cc}\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}=\frac{A_{\mathrm{vo}}\omega n^2}{s^1+2\varsigma \omega S+{\omega }_n^2}\mathrm{Where},& \left(5\right)\\ A_{\mathrm{vo}}=\frac{G_{m1}G_{m2}R_1R_L}{1+G_{m1}G_{m2}R_1R_L}& \left(6\right)\\ \zeta =\frac{1}{2}\frac{R_1C_1+R_LC_L}{\sqrt{R_1R_LC_1C_L\left(1+G_{m1}G_{m2}R_1R_L\right)}}& \left(7\right)\\ \omega n^2=\frac{1+G_{\mathrm{mf}}G_{m2}R_1R_L}{R_1R_LC_1C_L}& \left(8\right)\end{array}$

Denominator of RHS of equation is second order equation 5. It provides complex conjugate poles which cause frequency resonance and peaking depending on ζ as shown in FIG. 6. FIG. 7 is a time domain waveform for transparent mode of conventional latch and feedback based latch for ζ=0.7 whereas FIG. 8 is a frequency domain waveform for various ζ for second order equations. For an maximally-flat butter-worth response, ζ=√{square root over (2)}/2. The result reveals that local negative feedback increases the GBW in transparent phase of latch. In the place of buffer, any g_m cell providing current to its capacitive load can be used. Time delay for latches are given by:

$\begin{array}{cc}{T}_d=\tau \ln \frac{V_{\mathrm{logic}}}{\Delta V}\mathrm{Where},\tau =\frac{G_m}{C}& \left(9\right)\end{array}$

G_m=Trans-conductance of latch transistors.C=output capacitances.V_logic=Voltage level to be achieved.ΔV=Minimum input that can be resolved correctly.

By using proposed D-Flip-Flop, ΔV will be higher as compare to conventional D-Flip-Flop which leads to less time for latching for same clock frequency. Its application in serializers and deserilizers are shown in FIGS. 20 and 21.

FIG. 9 is a simulation result with input data at 12.2 Gb/s data rate. Data rate of the D-Flip-Flop is enhanced by approximately 30% using local negative feedback in transparent phase of latch. This increases the data rate by 31% of the high speed D-Flip-Flop with 25% area and 12.5% power overhead. Simulation results in standard 90 nm CMOS technology of the high speed simulation confirmed the working of this technique with 12.2 Gb/s data rate, while consuming 18 mW off a 1V supply.

FIG. 10 shows feedback based flip-flops using feedback based latches according to present invention. In this technique, advantage of feedback 1002; 1004 across latches 1008; 1010 based D-Flip-Flop and feedback based D-Flip-Flop are incorporated by adding same number of negative feedback loops across D-Flip-Flop. This improves high speed D-Flip-Flop by 45%. This is applicable to all the applications mentioned hereinafter for feedback based flip-flops and negative feedback across latches based D-Flip-Flop. Feedback is provided by transconductance stage during implementation that can be made adaptive in nature based on process corner, temperature and decision of input. FIGS. 11 and 12 show simulation results of feedback based flip-flops with negative feedback across latches. This shows for 13.5 Gb/s input data-rate, only modified feedback based D-Flip-Flop with feedback across latches is working fine. A detailed comparison of D-Flip-Flops for same technology is shown in Table 1.

TABLE 1
					Feed-
					back
	Con-		Feed-	Feed-	in DFF
CML DFF	ven-	Series	back	back in	and
based on	tional	Inductors	in DFFs	latches	Latches
Power (mW)	16	16	17	18	19
Speed (Gb/s)	9.25	13	11.9	12.2	13.5
Area (um2)	30 × 40	200 × 220	30 × 44	30 × 50	30 × 54
Eye Opening (mV)	438	247	326	340	300
$Q=\frac{\mathrm{Eye}\text{-}\mathrm{opening}}{\mathrm{Max}\left(\mathrm{eye}\text{-}\mathrm{amp}.\right)}\left(\%\right)$	87	56	60	62	81.3
Jitterpp (ps)	13	18	7	5.3	3.6
$\mathrm{FOM}\left(\frac{\mathrm{Gbit}}{J\times \mathrm{Hz}\times m^2}\right)$	4.01	0.15	4.41	3.76	3.65

$\mathrm{FOM}=\frac{\mathrm{DataRate}}{f_T\times \mathrm{Area}\times \mathrm{Power}}\left(\mathrm{The}\mathrm{higher}\mathrm{the}\mathrm{better}\right)$

EXAMPLE 1

Pseudo Random Binary Sequence Generator (PRBSG)

FIG. 13 is a block diagram of 2⁷−1 PRBS generator. A Pseudo Random Binary Sequence Generator (PRBSG) is based on linear feedback shift registers (LFSR). It contains minimum N flip-flops for 2^N−1 PRBSG. Number of XORs and tapping of XORs ensure pseudo random sequence. 2⁷−1 PRBSG and its critical path are shown in FIG. 13. Maximum clock frequency is given by:

$\begin{array}{cc}{f}_{{\mathrm{Clk}}_{\max }}=\frac{1}{T_{D{67}_{\mathrm{Clk}-Q}}+T_{\mathrm{PXOR}}+T_{D1_{\mathrm{set}-\mathrm{up}}}}& \left(10\right)\end{array}$

Where, T_D67Clk-Q=Max(T_D6Clk-Q, T_D7Clk-Q), T_D6Clk-Q=Clock-to-Q delay of 6th D-Flip-Flop, T_D7Clk-Q=Clock-to-Q delay of 7th D-Flip-Flop, T_PXOR=propagation delay of XOR and T_D1set-up=Setup time of D-Flip-Flop.

In propagation delay of XOR, interconnect delay is major contributor because it contains longest path as shown in FIG. 13 thus making it the critical path. Each node of the PRBSG consist of parasitic resistance and capacitance which causes ISI. For example, parasitic resistance and capacitance at the XOR output node consist of

R_par=R_int  (11)

C _par =C _{D XOR} +C _int +C _{G DFF}   (12)

Where, R_par=Parasitic resistance of XOR output,R_int=Parasitic resistance of interconnect,C_DXOR=Parasitic capacitance at output XOR,C_int=Parasitic capacitance of interconnect,C_GDFF=Parasitic capacitance of the input of the D-Flip-Flop.

In the present invention work, interconnect is considered as an RC delay line as shown in FIG. 13 and negative feedback across D-Flip-Flops are applied to enhance its bandwidth. Once the critical path is compensated as mentioned above, the signal path between 2 D-Flip-Flop's becomes the frequency limiting channel. This channel consists of 2 filters, 1) Interconnect between the latch output and CML buffer input of the D-Flip-Flop. 2) Between the CML buffer output and the input of subsequent D-Flip-Flop. These channels are also compensated by putting a feedback around a subsequent D-Flip-Flop's in the same manner. Multiple feedback coefficients can also be used with and without adaptation for improving the performance further. Any adaptation algorithm can be used to estimate feedback factors. FIG. 14a is simulation result at 10.6 Gb/s data rate and FIG. 14b is an eye diagram of XOR output at 10.6 Gb/s data rate (jitter_pp=24 ps in the conventional PRBS generator and eye opening=160 mv).

CML D-Flip-Flop is used to provide delay and output of D-Flip-Flop is fed back to Y through one trans-conductance stage as shown in FIG. 15. The incorporation of the feedback stages changes the parasitic loading. Hence some empirical optimization of the feedback factor at the circuit level needs to be done, which leads to a feedback factor of 0.3. Output of equalized PRBSG is shown in FIG. 16b. FIG. 16c shows the eye diagram which has vertical eye opening of 250 mV and jitter_pp of 3.5 ps. Same technique is employed on other nodes of PRBSG for enhancing data-rate. Only inspection of the eye diagram may not be sufficient, as even a single misinterpreted bit by XOR can reduce the run length of the PRBS drastically. Hence one should verify the PRBS by examining the total generated sequence. Comparison between conventional, inductive peaking based and modified PRBS generator is shown in Table 2.

TABLE 2
PRBS Gen.	Conventional	Inductor based	Proposed
Power (mW)	190	190	222
Maximum Speed (Gb/s))	10.6	13	13
Area (PRBS core) (um2)	64 × 187	800 × 400	64 × 220
Eye Opening (mV)	263	247	200
Jitterpp (ps)	9	15	8
$\mathrm{FOM}\left(\frac{\mathrm{Gbit}}{J\times \mathrm{Hz}\times m^2}\right)$	93.1	3.48	90.84

$\mathrm{FOM}=\frac{{\log }_2\left(\mathrm{MLS}\right)\times \mathrm{DataRate}}{f_T\times \mathrm{Area}\times \mathrm{Power}}\left(\mathrm{The}\mathrm{higher}\mathrm{the}\mathrm{better}\right)$

In modified PRBSG, speed is increased with approximately same FOM. Simulation results at 13-Gb/s confirm correct functional operation of the PRBS as shown in FIG. 17a and FIG. 17b. As a worst case a triangular waveform is used as the clock. Simulation are performed in typical-typical corner with temperature of 100 C. For optimized performance across temperature and process variations, the feedback factor can be adjusted by adjusting current in the feedback amplifier.

EXAMPLE 2

Clock and Data Recovery (CDR) Circuit

Clock and data recovery (CDR) circuits are used for clock extraction and re-timing of data at receiver side. In this demonstration of feedback across latches based D-Flip-Flop, phase detector of CDR circuit is modified. Hogge phase detector is shown in FIG. 18. Simulation results shown in FIG. 19 reflects proposed D-Flip-Flop based CDR has good eye opening with less jitter as compare to conventional D-Flip-Flop based CDR which helps it in settle quickly. Similarly, any type of phase detector can be used in same fashion with proposed negative feedback based D-Flip-Flop. This technique can also be employed on serialization of data before the multiplexer and also in de-multiplexing of data.

EXAMPLE 3

Serializers and Deserializers

Implementation of negative feedback across latches based D-Flip-Flop, as described in FIG. 3, in serializers and deserializers are shown in FIGS. 20 and 21. This technique improves performance of D-Flip-Flop by improving each latch performance using feedback based latches. Feedback factor of local loop of latches can be made adaptive based on process corner and temperature i.e. the feedback coefficient is adjusted automatically based on a process and temperature detection circuitry.

As described hereinbefore, performance of D-Flip-Flop is improved by negative feedback and individual latches are also improved by negative feedbacks. Negative feedback across D-Flip-Flop mitigates timing errors which is caused by RC delay at the input of D-Flip-Flop. Similarly, latches are also improved. The difference between these two feedbacks are, feedback based flip-flops is discrete time in nature and negative feedback based latches are continuous time in nature. Individually, these improve speed by 35% and 25% respectively and combination of these two types of feedback provides 45% improvement in speed while consuming 18.75% power and 35% area with respect to conventional D-Flip-Flop. Timing errors are also corrected so efficiently that it creates distributed equalization in communication links and helps to relax requirement of equalizers using negative feedbacks.

While the present invention has been described with respect to certain embodiments, it will be apparent to those skilled in the art that various changes and modification may be made without departing from the scope of the invention as defined in the following claims.

Claims

1. A flip-flop having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; andat least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.

2. A flip-flop as claimed in claim 1, comprising a first feedback path from the output of the flip-flop and is added to the input of the flip-flop.

3. A flip-flop as claimed in claim 1, comprising a second feedback path from the output of the first latch and is added to the input of the flip-flop.

4. A flip-flop as claimed in claim 1, comprising a first feedback path from the output of the first latch and is added to the input of the flip-flop; anda second feedback path from the output of the flip-flop and is added to the input of the second latch.

5. A flip-flop as claimed in claim 1, wherein at least one feedback path comprises a transconductance stage.

6. A flip-flop as claimed in claim 1, wherein at least one feedback path comprises an inverter stage.

7. A flip-flop as claimed in claim 1, wherein at least one feedback is a negative feedback.

8. A flip-flop as claimed in claim 1, wherein the strength of feedback can be adapted using a control mechanism.

9. A latch having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: an amplifier stage whose input terminal is the input terminal of the latch and the output terminal is the output terminal of the latch;a positive feedback stage connected to the output terminal of the latch; anda feedback path that adds signal to the input of the latch from the output of the latch.

10. A latch as claimed in claim 9, wherein the feedback path from the output terminal to the input terminal comprises a transconductance stage.

11. A latch as claimed in claim 9, wherein the feedback path from the output terminal to the input terminal comprises an inverter stage.

12. A latch as claimed in claim 9, wherein the feedback path from the output terminal to the input terminal is a negative feedback.

13. A latch as in claim 9, wherein the strength of the feedback from the output terminal to the input terminal can be adapted using a control mechanism.