Circuit for recognizing oscillations in a useful signal due to feedback between acoustic input and output transducers

Abstract

A circuit arrangement for suppressing oscillations, such as acoustic feedback in a hearing aid, has a circuit which recognizes the presence of oscillations in a useful signal, an oscillatory frequency search circuit, and an oscillation modifying circuit controlled by the search circuit. The oscillation modifying circuit suppresses oscillations by filtering. Drift effects are avoided by a frequency clamp-on sub-circuit in the search circuit, which retains the frequency of the recognized oscillation at the modifying circuit, even when the oscillatory signal at the input of the search circuit disappears.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit arrangement for suppressing oscillations, and in particular to such a circuit arrangement for suppressing acoustic feedback in a hearing aid.

2. Related Application

The subject matter of the present application is related to the subject matter of a co-pending application of the same inventor, filed simultaneously herewith, entitled Circuit Arrangement For Recognizing Oscillations, Ser. No. 152,326.

3. Description of the Prior Art

The risk of acoustic feedback is present in electronic systems having a microphone and a speaker in relatively close proximity to each other. Hearing aids are particularly susceptible to such feedback effects because the acoustic transducers (microphones and earpieces, or receivers) are disposed only a slight distance from each other. This results in disturbing tones such as, for example, a whistling effect, to be experienced by the wearer.

In hearing aids, efforts have been undertaken to reduce the susceptibility of the hearing aid to feedback oscillation mainly by constructing the auditory channel, and by improving the sound-insulating capability of the plastic used to make the ear mold. Efforts have also been undertaken from an electrical standpoint, however these have been limited to clipping or shifting the frequency band, rather than attacking the oscillatory signal itself. For example, constant attenuation of the output signal is described in "A Feedback Stabilizing Circuit For Hearing Aids," by D. Preves in "Hearing Instruments, Vol. 37, No. 4, pages 34, 36-41 and 51.

Other circuits have recently been developed (for example as offered by RIM-Elektronik of Munich, West Germany, and the circuits described in U.S. Pat. Nos. 4,232,192 and 4,079,199) which recognize oscillations, and take steps to suppress the oscillations. Such circuits take the useful signal between the input transducer and a final amplifier, which precedes the output transducer, and amplify the signal with an additional amplifier. The amplified signal is compared to a threshold voltage in a comparator stage, and is supplied to a phase-locked loop (PLL). The PLL recognizes an oscillation when it occurs, and forwards a suppress signal to a notch filter, preceding the final amplifier. The notch filter suppresses the frequency range of the oscillation, or reduces the gain, as in the case of the circuit described in U.S. Pat. No. 4,079,199. As is known, however, when the input signal falls off, a PLL becomes unstable and drifts. The result of the drift is a periodic, acoustic noise signal.

Another oscillation-suppressing circuit is described in U.S. Pat. No. 4,091,236. In this known circuit, the filter used therein skips to a prescribed frequency when the oscillation ceases. A risk of drift when the input signal appears is also present in this circuit, however, because the circuit generates oscillation recognition signals as soon as input signals having irregular periods (the normal case) are no longer acquired.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an oscillation-suppressing circuit which recognizes the presence of an oscillation in a useful signal, suppresses the oscillation, and remains stable, i.e., does not begin to drift, when the input signal disappears.

The above object is achieved in a circuit arrangement wherein an oscillation-recognizing circuit identifies the presence of an oscillation in a useful signal and an oscillatory frequency search circuit controls an oscillation modifying circuit to suppress the oscillation by means of a filter. Drift effects are avoided by a clamp-on sub-circuit in the search circuit, which retains the frequency in the oscillation modifying circuit of the recognized oscillation, even when the oscillatory signal at the input of the search circuit disappears.

In accordance with the principles of the present invention, the oscillatory frequency search circuit takes the place of the PLL in conventional circuits, and further the oscillatory frequency search circuit includes a clamp-on sub-circuit, which continues to generate an output signal after the disappearance of the oscillation. This output signal holds the oscillation modifying circuit, for example, a notch filter, in a permanently set condition. Acoustic noise signals which may arise in the filter circuit, due to drifting thereof, therefore do not occur.

In one embodiment, the circuit arrangement is connected between the final amplifier and the output transducer of an acoustic system, which eliminates the need for the additional amplifier used in certain of the prior art approaches. This permits the circuit arrangement to be constructed economically and, as is particularly useful in hearing aids, in a smaller volume than conventional circuits.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of an acoustic system, such as a hearing aid, including a circuit arrangement for suppressing oscillations constructed in accordance with the principles of the present invention.

FIG. 2 is a circuit diagram showing details of the oscillation recognition circuit in the circuit arrangement constructed in accordance with the principles of the present invention.

FIG. 3 is a voltage/time diagram showing the relevant signals in the operation of the oscillation recognition circuit of FIG. 2.

FIG. 4 is a schematic block diagram of an oscillatory frequency search circuit for the circuit arrangement constructed in accordance with the principles of the present invention.

FIG. 5 is a circuit diagram of an oscillation modifying circuit in a circuit arrangement constructed in accordance with the principles of the present invention, in the form of a notch filter.

FIGS. 6 and 7 are respective circuit diagrams of further embodiments of an oscillation recognition circuit and an oscillatory frequency search circuit connected thereto, in a circuit arrangement constructed in accordance with the principles of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An acoustic system, such as a hearing aid, is generally shown in FIG. 1 including a circuit arrangement constructed in accordance with the principles of the present invention for suppressing oscillations, such as feedback effects.

The oscillation-suppressing circuit is generally referenced at 4, and is constructed in the manner of an electrical feedback circuit. The circuit suppresses electrical signals which are generated as a consequence of acoustic feedback effects, which usually result in unattenuated oscillations in the remainder of the circuit. The feedback effect is schematically indicated in FIG. 1 by the dashed line arrow between the acoustic output transducer 2 and the microphone 1.

An acoustic useful signal SE, together with the acoustic feedback signal SR, are converted into an electrical signal SO in the microphone 1. The output signal S5 of the oscillation-suppressing circuit 4 is subtracted from this signal SO in a subtraction element 5. The remaining signal S1 is amplified in a non-inverting final amplifier 3 to form a signal S2. In the output transducer 2, this signal S2 is converted into an acoustic signal SA. At the same time, the signal S2 is supplied to the oscillation suppressing circuit 4 as an input signal.

Analyzed in terms of function, the oscillation-suppressing circuit 4 includes an oscillation recognition circuit 6, an oscillatory frequency search circuit 7, and an oscillation modifying circuit 8. In the oscillation-suppressing circuit 4, the signal S2 is conducted to the oscillation recognition circuit 6, and is also supplied to the modifying circuit 8. A check is undertaken in the recognition circuit 6 to determine whether the signal S2 contains an oscillation arising from acoustic feedback effects. If an oscillation is present, the recognition circuit 6 generates an output signal S3. The signal S3 places the oscillatory frequency search circuit 7 in operation, causing a sequence of signals S4 to be generated as an output by the search circuit 7, until the signal S3 at the output of the recognition circuit 6 disappears. The signal S4 at the output of the search circuit 7 when the signal S3 disappears is maintained by the search circuit 7 until a new oscillation appears. The signals S4 control the modifying circuit 8 such that frequency ranges in the overall frequency spectrum of the signal SO, which are allocated to the recognized oscillation, are substantially suppressed. As described above, the signal S5 is the output signal of the oscillation-suppressing circuit 4.

The details of the oscillation recognition circuit 6 are shown in FIG. 2, and the relevant signals in FIG. 3. Because oscillations are long-lasting alternating voltages having relatively large amplitude and relatively high frequency, the recognition circuit 6 checks the input signal S2 for these characteristics. In a first stage, the amplitude of the input signal S2 is compared to a first threshold voltage UT1 in a first comparator 9. If the amplitude of the signal S2 upwardly exceeds the threshold UT1, a rectangular voltage signal S21 is generated, with time intervals t.sub.o through t.sub.n between the pulses.

The following stage in the recognition circuit 6 includes an RC element consisting of an ohmic resistor 10, a diode 10' and a capacitor 11, and also includes a second comparator 12. The capacitor 11 is rapidly charged by the signal S21 via the diode 10', and is in turn discharged via the resistor 10 with a prescribed time constant. This time constant, together with the threshold voltage UT2 of the second comparator 12, define a first time interval T11 which defines the minimum frequency to which the oscillation recognition 6 responds. If a short time constant is selected, the recognition circuit 6 essentially responds only to high-frequency signals. Given low-frequency signals, the capacitor 11 has enough time to discharge below the threshold voltage UT2 of the second comparator 12. These low-frequency signals, therefore, are not acquired. It is thus assured that the recognition circuit 6 only reacts to signals which result from acoustic feedback effects, with signal components appearing periodically with low frequency in the useful signal (for example a voice signal) do not trigger a response in the recognition circuit 6.

When the oscillation criteria of "high amplitudes" and "high frequencies" have been met in the first and second stages of the recognition circuit 6, output signals S23 are supplied to a third stage of the recognition circuit 6. The output signals S23 are rectangular voltage signals having a respective duration equal to the time which the signals S22 exceed the threshold of the comparator 12. The signals S23 thus reflect the duration T.sub.1 of the large amplitude, high frequency input signal. The third stage of the recognition circuit 6 includes a diode 13, an RC element consisting of a resistor 14 and a capacitor 15, and a third comparator 16. The capacitor 15 is charged with the signal S23 via the resistor 14. The resistor 14 and the capacitor 15 are dimensioned such that the charging time constant is high, for example, 0.5 through 2 seconds. The capacitor 15 is immediately discharged via the diode 13 when the output voltage S23 drops even briefly. If, however, the rectangular signal S23 lasts longer than a second selected time constant T12, the capacitor 15 is charged to such an extent that the voltage upwardly exceeds the threshold UT3 of the third comparator 16. In this instance, the input signal S2 meets all of the oscillation recognition criteria, and the signal S3 is generated by the comparator 16 as an output of the recognition circuit 6, indicating the presence of an oscillation.

The details of an oscillatory frequency search circuit constructed in accordance with the principles of the present invention are shown in FIG. 4. The search circuit 7 is connected between the recognition circuit 6 and the modifying circuit 8, and controls the modifying circuit 8 so that recognized oscillations are suppressed. A first stage 17 of the search circuit 7 generates digital, frequency-defining signals S33, and is controlled by the output signals S3 from the recognition circuit 6. The main component of the first stage 17 is a counter unit 18 which includes a counter 19, a counting direction switch 20, and a reset element 21, also referred to as a "power-on reset." The first stage 17 also includes an oscillator 22 and an AND gate 23. The counter 19 simultaneously serves as a clamp-on means for the frequencies of the recognized oscillation, as described in greater detail below.

When the search circuit 7 is energized, the reset element 21 sets all of the output signals S32 at all four output lines of the counter 19 to zero (also referred to as the "low" status). This 0000 status is digitally incremented by 1 each time a pulse S32 ("high") is registered at the input of the counter 19. When all four output lines have been switched to "high" the original zero condition is produced again upon the occurrence of the next pulse S31, and the incrementation sequence is repeated. A pulse S31, however, is only generated if an output signal S3 from the recognition circuit 6 is present at one input of the AND gate 22 preceding the counter 19. If such a signal is present, pulses S31', generated by the oscillator 22, are forwarded as the incrementation pulses S31. The oscillator 22 therefore defines the speed at which the counter 19 is incremented.

The counter 19 increments the output pulses S32 until the output signal S3 from the recognition circuit 6 disappears. (The signal S3 disappears when the oscillation has been suppressed by the modifying circuit 8, as described below). When the signal S3 disappears, the counter 19 receives no further pulses S31, and remains in its current state, until a new output signal S3 from the recognition circuit 6 appears. The counter 19 thus stores the state or condition which has been set, and together with the AND gate 23, functions as a clamp-on means for retaining the frequency of the recognized oscillation at the modifying circuit 8. It is preferable to include such a clamp-on means in the search circuit 7 to prevent the oscillation suppression circuit 4 from drifting, and thus avoiding the reappearance of a previously suppressed oscillation.

The first stage 17 of the search circuit 7 also includes a count direction switch 20 at the output of the counter 19. The switch 20 has three output lines, and prevents a discontinuous "skip" from the count 111 to 000 in the frequency-defining output signals S33. This is accomplished by decrementing every second sequence from 111 to 000 by inverting the input signals S32. Avoidance of such a "skip" is preferable so that the filter in the modifying circuit 8 for suppressing the oscillatory frequency does not jump from one end of the frequency spectrum to the other given a reversal of the counting direction, but instead migrates back and forth in the frequency spectrum.

A second stage in the search circuit 7 samples the frequency-defining signals 33 from the first stage 17 (received from the switch 20) and controls the modifying circuit 8 by output signals S4. The second stage 24 includes a decoder 25 which transfers the eight possible signal combinations via the three incoming lines onto eight different output lines. These eight signals S4 control the modifying circuit 8 to define the frequency range in the selectable frequency spectrum which is to be filtered by the modifying circuit 8.

The decoder 25 thus cycles through each of the frequency ranges, as long as the frequency-defining signals S23 are continually changing by virtue of the incrementing count of the counter 19, which increments as long as the signal S3 is present. When the frequency range containing the unwanted oscillation is cycled through, and thus that frequency range is suppressed, as described below, and the oscillation is also suppressed, the signal S3 disappears and the counter 19 is no longer incremented, so the decoder 25 no longer cycles, but an output signal for the frequency range which successfully suppressed the oscillation is retained, as described above, by the operation of the clamp-on means.

The decoder 25 controls the modifying circuit 8 by means of a discretely variable resistor bank 26, as shown in FIG. 5. Given an existing oscillation, the signals S4 are conducted via one or more lines of the resistor unit 26. Each line includes at least one transistor 27, one ohmic resistor 28, and one inverter 29, the resistors 28 having respectively different resistance values. If an oscillation is not present (i.e., signal S33 is 000), all transistors 27 are in a conducting state (by inversion of the signals S4 in the inverters 29). Given a signal S33 of 111, by contrast, all of the transistors 27 are in a non-conducting, or inhibiting, state. The resistance values of the resistors 28 are preferably selected so that the modifying circuit 8 selects eight adjacent frequency ranges between 1 kHz through infinity. It is also preferable that at least one transistor-resistor combination permits selection of a frequency range above the acoustic limit of human hearing, so that only this range is filtered after the apparatus is energized and before an oscillation appears.

The modifying circuit 8 also includes a further ohmic resistors 30, capacitors 31, and an amplifier 32, which are connected in the form of a bandpass filter. Such a filter is known, for example, from the book "Halbleiter-Schaltungs Technik," (Semiconductor Circuit Technique) by Teitze and Schenk, 7th Edition (1985) at pages 419-421. Because the bandpass filter generates negative feedback for the final amplifier 3, the modifying circuit 8 simulates a notch filter which forms an acceptor circuit at the resonant frequency. The bandwidth and the gain of the simulated filter are dependent on the discretely variable resistor unit 26. The resonant frequency can thus be varied by changing the values of resistance in the resistor unit 26 without influencing the bandwidth or gain. An output resistor 33 defines the weighting of the feedback signal S5 at the subtraction element 5 (shown in FIG. 1).

Other embodiments of the modifying circuit 8 not described in detail herein are also possible. The modifying circuit may alternatively be fashioned, for example, as a C--R high-pass filter, a phase shifter, a phase switcher, or a gain reducing circuit.

The recognition circuit 6 and the search circuit 7 may also be modified. Modified versions 6' and 7' of those circuits are shown in FIGS. 6 and 7. In the embodiment of FIG. 6, the third stage (consisting of components 13 through 16 in FIG. 2) of the recognition circuit 6 is replaced in the recognition circuit 6' by a counter stage which includes an inverter 34, a digital counter 35, and an AND gate 36.

In the same manner as described in connection with FIG. 2, the input signal is examined for the oscillatory characteristics of "high amplitude" and "high frequencies." An output signal S23, however, in the embodiment of 6' is digitally processed to determine whether the large amplitude, high-frequency input signal is long-lasting. The counter 35 compares two signal inputs. One input is the rectangular voltage signals S21, and the other input is a reset input which, in combination with the inverter 34, constantly resets the counter 35 to zero except when a signal S23 appears. The counter 35 counts the rectangular signals S21 as long as a signal S23 is present. After the occurrence of a selected number of signals S21, the input signal is recognized as an oscillation. Together with the AND gate 36, the counter 35 generates incrementing pulses S3 in response thereto. These incrementing pulses can be directly forwarded to the counter 19 of the search circuit 7'. The search circuit 7' thus does not require an oscillator, in contrast to the search circuit 7.

In the embodiment of FIG. 7, the first and second stages of the recognition circuit 6 (elements 10 through 13 in FIG. 2) are replaced by digital components. A counter 37 is reset to a 000 reading at the occurrence of each signal S21. This event corresponds to a rapid charging of the capacitor 11 in the analog embodiment of FIG. 2. The counter 37, having a Q output in the "low" status, is incremented at a rate prescribed by an oscillator 38. This incrementation corresponds to the discharging of the capacitor 11 in the analog embodiment. By means of an inverter 39, the "low" status at the Q output of the counter 37 is inverted to a "high" status at the input of an AND gate 40, so that the incrementing pulses from the oscillator 38 are forwarded to the input of the counter 37. A selected count limit is set in the counter 37. If a further signal S21 arrives before the counter 37 reaches this limit count, the Q output of the counter 37 remains at the "low" status. If, however, the counter 37 reaches the limit count, the Q output of the counter 37 is switched to "high" and the AND gate 40 blocks the incrementing pulses from the oscillator 38. Reaching the count limit corresponds to discharging of the capacitor 11 down to the threshold UT2 in the embodiment of FIG. 2.

Another counter 35 is provided in the embodiment of FIG. 7, corresponding to the second comparison stage in the embodiment of FIG. 2. The counter 35 measures the time duration T.sub.1 of a series of successive signals S21. The counter 35 is always reset to a 000 status only when no signal S21 is present at one input of a further AND gate 41. As soon as a signal S21 appears at this input, both inputs of the AND gate 41 will be at a "high" status, which produces a "low" input via the inverter 34 at the reset input of the counter 35. The counter 35 is incremented by pulses from the oscillator 38 until the signals S21 disappear, or until a selected extremely high limit count is reached. This extremely high limit count is comparable to the slow charging of the capacitor 15 in the embodiment of FIG. 2 to the threshold UT3. The counter 35 generates oscillation recognition signals S3 in the same manner described earlier in connection with FIG. 6.

Although other modifications and changes may be suggested by those skilled in the art it is the intention of the inventor to embody within the patent warranted hereon all changes and modifications as reasonably and properly come within the scope of his contribution to the art.

Claims

1. In an acoustic system having an acoustic input transducer and an acoustic output transducer, a circuit for recognizing oscillations in a useful signal due to feedback between said input and output transducers, said circuit comprising:

input means to which said useful signal is supplied for generating a signal whenever, and for as long as, the amplitude of said useful signal exceeds a selected value; and

signal evaluation means to which said signal generated by said input means is supplied for generating a signal indicating recognition of an oscillation due to feedback, said signal evaluation means including

means for generating a first evaluation signal corresponding to the intervals between signals generated by said input means, and

means for generating a second evaluation signal corresponding to the time duration of a selected series of successive signals generated by said input means,

said signal evaluation means generating a signal indicating recognition of said oscillation dependent on said first and second evaluation signals.

2. A circuit as claimed in claim 1, wherein said means for generating a first evaluation signal comprises:

means for setting a threshold at a level corresponding to a selected time interval; and

means for comparing said signals from said input means to said threshold, said means for comparing generating said first evaluation signal as long as said intervals between said signals generated by said input means are less than said threshold and thus less than said selected time interval.

3. A circuit as claimed in claim 2, wherein said means for setting said selected time interval comprises:

means for setting a time constant for said signals generated by said input means; and

means for setting a threshold value for said means for comparing.

4. A circuit as claimed in claim 3, wherein said means for setting a time constant is a means to which said signals from said input means are supplied for generating a signal which changes in magnitude over time proportional to the respective durations of said signals from said input means.

5. A circuit as claimed in claim 4, wherein said means for generating a signal changing in magnitude is a capacitor connected to an output of said input means to be discharged by said signals generated by said input means.

6. A circuit as claimed in claim 4, wherein said means for generating a first evaluation signal further includes means for generating a series of counting pulses, wherein said means for generating a signal changing in magnitude is a counter having a reset input to which said signals from said input means are supplied and a counting input to which said counting pulses are supplied, said counting pulses incrementing the count of said counter from an initial count set by the occurrence of said signal from said input means up to a limit count, and wherein said means for generating a first evaluation signal further comprises means for generating said first evaluation signal as long as the count of said counter is less than said limit count.

7. A circuit as claimed in claim 6, wherein said counter has a Q output at which said count of said counter is present, and wherein said means for generating said first evaluation signal as long as said count of said counter is less than said limit count comprises:

an inverter having an input connected to said Q output; and

an AND gate having a first input connected to said means for generating counting pulses, a second input connected to an output of said inverter, and an output connected to said counting input of said counter.

8. A circuit as claimed in claim 1, wherein said means for generating a second evaluation signal comprises:

means for setting a threshold at a level corresponding to a selected time interval; and

means for comparing said first evaluation signal to said threshold, said means for comparing generating said second evaluation signal as long as said first evaluation signal exceeds said threshold and thus exceeds said selected time interval, said second evaluation circuit constituting said signal of said signal evaluation means indicating recognition of said oscillation.

9. A circuit as claimed in claim 8, wherein said means for setting a selected time interval comprises:

means for setting a time constant for said first evaluation signal; and

means for setting a threshold level for said means for comparing.

10. A circuit as claimed in claim 9, wherein said means for setting a time constant is a means to which said first evaluation signal is supplied for generating a signal changing in magnitude proportional to the duration of said first evaluation signal.

11. A circuit as claimed in claim 10, wherein said means for generating a signal changing in magnitude is a capacitor connected to an output of said means for generating a first evaluation signal to be charged by said first evaluation signal.

12. A circuit as claimed in claim 10, wherein said means for generating a second evaluation signal includes means for generating a series of counting pulses, and gate means for generating a signal in the presence of both said first evaluation signal and said signal from said input means, and wherein said means for generating a signal changing in magnitude is a counter having a reset input to which said signal from said gate means is supplied and a counting input to which said counting pulses are supplied, said counting pulses incrementing said counter from an initial count set by said signal from said gate means up to a limit count.

13. A circuit as claimed in claim 12, wherein said gate means comprises:

an inverter having an output connected to said reset input of said counter; and

an AND gate having a first input to which said first evaluation signal is supplied, a second input to which said signals from said input means are supplied, and an output connected to a input of said inverter.

14. A circuit as claimed in claim 1, wherein said input means is a means for comparing the amplitude of said useful signal to a threshold corresponding to said selected value.

15. In an acoustic system having an acoustic input transducer and an acoustic output transducer, a circuit for recognizing oscillations in a useful signal due to feedback between said input and output transducers, said circuit comprising:

first comparing means for comparing the amplitude of said useful signal to a first selected threshold, said first comparing means generating a first signal whenever, and for as long as, said amplitude of said useful signal exceeds said first selected threshold;

a first capacitor connected to an output of said first comparing means to be discharged by said first signal, thereby setting a time constant for said first signal;

second comparing means for comparing the voltage across said first capacitor to a second selected threshold, said second means for comparing generating a second signal as long as said voltage across said first capacitor exceeds said second selected threshold;

a second capacitor connected to an output of said second comparing means to be charged by said second signal; and

third comparing means for comparing the voltage across said second capacitor to a third selected threshold, said third comparing means generating a third signal as long as the voltage across said second capacitor exceeds said third selected threshold, said third signal indicating the presence of an oscillation due to feedback in said useful signal.

16. In an acoustic system having an acoustic input transducer and an acoustic output transducer, a circuit for recognizing oscillations in a useful signal due to feedback between said acoustic input and acoustic output transducers, said circuit comprising:

means for comparing the amplitude of said useful signal to a selected value and generating a first signal whenever, and for as long as, the amplitude of said useful signal exceeds said selected value;

means for generating a series of counting pulses;

a first counter having a reset input to which said first signal is supplied and having a counting input to which said counting pulses are supplied, said counting pulses incrementing the count of said first counter from an initial value set by the occurrence of said first signal up to a first limit count;

logic means connected to said first counter for generating a second signal as long as the count of said first counter is less than said first limit count;

second logic means connected to said first logic means and to said means for comparing for generating a signal in the presence of both said first and second signals; and

a second counter having a reset input to which said signal from said second logic means is supplied and a counting input to which said counting pulses are supplied, said counting pulses incrementing the count of said second counter from an initial value set by the occurrence of said signal from said second logic means up to a second limit count, said second counter generating a third signal as long as the count of said second counter is less than said second limit count, said third signal indicating, the presence of an oscillation due to feedback in said useful signal.

17. A circuit as claimed in claim 16, wherein said first counter has a Q output at which the count of said first counter is present, and wherein said first logic means comprises

an inverter having an input connected to said Q output of said first counter; and

an AND gate having a first input connected to said means for generating counting pulses, a second input connected to an output of said inverter, and an output connected to said counting input of said first counter.

18. A circuit as claimed in claim 16, wherein said second logic means comprises:

an inverter having an output connected to said reset input of said second counter; and

an AND gate having a first input connected to an output of said first logic means, a second input connected to an output of said means for comparing, and an output connected to an input of said inverter.