Claims
- 1. A semiconductor memory device with redundant memory cells, comprising:
- a plurality of memory cells arranged in a matrix of (n+2) rows and m columns;
- (n+2) row lines arranged in said (n+2) rows, each row line having connected thereto memory cells arranged in a corresponding row;
- m column lines arranged in said m columns, each column line having connected thereto memory cells arranged in a corresponding column;
- row decoder means receiving row address signals and having n output lines, and for selecting one of said n output lines in accordance with received row address signals;
- column decoder means responsive to column address signals for selecting a column line of said m column lines;
- n connecting means, one for each output line of said row decoder means, provided between said n output lines of said row decoder means and said (n+2) row lines, each said connecting means including a first transistor element having a first conduction terminal connected to a corresponding output line of said row decoder means and a second conduction terminal connected to a row line arranged in a related row, and a second transistor having a first conduction terminal connected to said corresponding output line of said row decoder means and a second conduction terminal connected to a row line arranged in a next nearest row in a physical sequence with respect to said related row; and
- selecting means for setting one of the first and second transistor elements of each connecting means in a conductive state, and for setting the other of the first and second transistor elements in a non-conductive state.
- 2. A semiconductor memory device with redundant memory cells comprising:
- a plurality of memory cells arranged in a matrix of n rows and (m+2) columns;
- n row lines arranged in said n rows, each row line having connected thereto memory cells arranged in an associated row;
- (m+2) column lines arranged in said (m+2) columns, each column line having connected thereto memory cells arranged in an associated column;
- row decoder means responsive to row address signals for selecting a row line of said n row lines;
- column decoder means receiving column address signals and having m output lines, and for selecting an output line of said m output lines;
- (m+2) transfer gate means arranged in (m+2) columns, one for each of said (m+2) column lines;
- m connecting means, one for each output line of said column decoder means, each said connecting means including a first transistor element having a first conduction terminal connected a corresponding output line of said column decoder means and a second conduction terminal connected to a control gate of a transfer gate means arranged in a corresponding column, and a second transistor element having a first conduction terminal connected to said corresponding output line of said column decoder means and a second conduction terminal connected to a control gate of a transfer gate means arranged in a next nearest column with respect to said corresponding column; and
- selecting means for setting one of the first and second transistor elements of each connecting means in a conductive state, and for setting the other of the first and second transistor elements of each connecting means in a non-conductive state.
Priority Claims (1)
Number |
Date |
Country |
Kind |
1-142450 |
Jun 1989 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/828,254 filed Jan. 30, 1992, which is a continuation of application Ser. No. 07/500,965 filed Mar. 29, 1990 U.S. Pat. No. 5,134,585.
US Referenced Citations (14)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0090331 |
Mar 1983 |
EPX |
0300467 |
Jul 1988 |
EPX |
61-61300 |
Mar 1986 |
JPX |
Continuations (2)
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Number |
Date |
Country |
Parent |
828284 |
Jan 1992 |
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Parent |
500965 |
Mar 1990 |
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