Circuit for sample rate conversion

Abstract

The present invention is related to a circuit for converting the sample rate of a digital signal, comprising an input for applying the digital signal,a conversion filter having either a symmetrical or anti-symmetrical impulse response and implemented as a plurality of subfilters in parallel, each subfilter having a symmetrical or anti-symmetrical response derived from components of a polyphase decomposition of said impulse response,combining means for deriving from said applied digital signal input signals of said plurality of subfilters or for combining output signals of said plurality of subfilters into a digital signal with converted sample rate,an output for outputting said digital signal with converted sample rate.

Description

This application claims priority from Great Britain Patent Application, No. GB 0716942.8 filed on 31 Aug. 2007, which is incorporated by reference in its entirety.

FIELD

The present invention relates to the field of digital integer factor sample rate conversion (i.e. decimation and interpolation).

BACKGROUND

Digital sample rate conversion (SRC) is a technique to replace a system that includes a variety of master clock rates with a fixed clock rate system. Applications are abundant, e.g. acquisition (signal generator) systems with an oversampled ADC (DAC), followed (preceded) by a digital decimator (interpolator) to relieve the analog anti-aliasing (reconstruction) filter specifications. Integer factor SRC also appears in analysis (i.e. decimation) and synthesis (i.e. interpolation) filter banks.

To explain the problem tackled in the present invention a linear phase digital filter is assumed of order N, implying a finite impulse response h(k) of length N+1 (Eq. 1) with symmetric (Eq. 2) or anti-symmetric (Eq. 3) impulse response.

$\begin{array}{cc}y\left[n\right]=\sum _{k=0}^{N}h\left[k\right]x\left[n-k\right]& \left(\mathrm{Eq}.1\right)\\ h\left[k\right]=h\left[N-k\right]\mathrm{with}k\in 0\dots N& \left(\mathrm{Eq}.2\right)\\ h\left[k\right]=-h\left[N-k\right]\mathrm{with}k\in 0\dots N& \left(\mathrm{Eq}.3\right)\end{array}$ T_ƒis defined as the sample period of the output signal (for an interpolator) or the input signal (for a decimator). Thus, T_ƒis the sample period of the signal with the fastest sample rate. For a single-rate filter T_ƒis equal to the sample period of both input and output signals.#M is defined as the number of multiplications per output sample and per sample period T_ƒ. A single rate realisation of Eq. 1 results in #M as given in Eq. 4. Also naive realisations of Eq. 1 in integer factor interpolators and decimators have that same #M as shown in Eq. 4.#M=N+1  (Eq. 4)In a single-rate system a linear phase FIR realisation can take advantage of its impulse response symmetry (Eq. 5) or anti-symmetry (Eq. 6); whereby └ ┘ denotes a truncation to the lower integer.

$\begin{array}{cc}y\left[n\right]=\sum _{k=0}^{\lfloor \frac{N}{2}\rfloor }h\left[k\right]\left(x\left[n-k\right]+x\left[n+k-N\right]\right)\mathrm{for}N\mathrm{odd}y\left[n\right]=h\left[\lfloor \frac{N}{2}\rfloor \right]x\left[\lfloor \frac{N}{2}\rfloor \right]+\sum _{k=0}^{\lfloor \frac{N}{2}\rfloor -1}h\left[k\right]\left(x\left[n-k\right]+x\left[n+k-N\right]\right)\mathrm{for}N\mathrm{even}& \left(\mathrm{Eq}.5\right)\\ y\left[n\right]=\sum _{k=0}^{\lfloor \frac{N}{2}\rfloor }h\left[k\right]\left(x\left[n-k\right]-x\left[n+k-N\right]\right)\mathrm{for}N\mathrm{odd}y\left[n\right]=h\left[\lfloor \frac{N}{2}\rfloor \right]x\left[\lfloor \frac{N}{2}\rfloor \right]+\sum _{k=0}^{\lfloor \frac{N}{2}\rfloor -1}h\left[k\right]\left(x\left[n-k\right]-x\left[n+k-N\right]\right)\mathrm{for}N\mathrm{even}& \left(\mathrm{Eq}.6\right)\end{array}$ By means of Eq. 5 and Eq. 6 the number of multiplications per output sample #M is reduced from N+1 to

$\begin{array}{cc}\#M=\lfloor \frac{N}{2}\rfloor +1& \left(\mathrm{Eq}.7\right)\end{array}$

Another generally known principle is multi-phase decomposition for sample rate conversion. Equation 8 defines the polyphase components h_λ(n·LT_ƒ) for an L-fold decomposition of impulse response h(k·T_ƒ).h′_λ(n·LT_ƒ)=h((nL+λ)T_ƒ)  (Eq. 8)

• • with λ=0 . . . L−1The filter h(k·T_ƒ) has a frequency response to select the desired signal image (for an interpolator) or anti-aliasing band (for a decimator).The corresponding Z-transforms are combined in vector H(z) (Eq. 9).H_λ(z)=Z{(h_λ(n·LT_ƒ)}H(z)=[H₀(z) . . . H₁(z) . . . H_L−1(z)]^T  (Eq. 9)The polyphase equation for an L-factor interpolator is shown in Eq. 10:Y(z)=H(z)·X(z)  (Eq. 10)whereby X(z) denotes the Z-transform of the input signal x(n·LT) and Y(z) the decomposition of the output signal y(k·T_ƒ) as defined in Eq. 11.y_λ(n·LT_ƒ)=y((nL+λ)T_ƒ)Y_λ(z)=Z{y_λ(n·LT_ƒ)}Y(z)=[Y₀(z) . . . Y₁(z) . . . Y_L−1(z)]^T  (Eq. 11)
  • with λ=0 . . . L−1For an L-factor decimator the polyphase equation is shown in equation 12.Y(z)=H^T(z)·X(z)  (Eq. 12)y(n·LT_ƒ) hereby represents the output signal. The decomposition of the input signal x(k·T_ƒ) is as defined in equation 13.x_λ(n·LT_ƒ)=x((nL+λ)T_ƒ)X_λ(z)=Z{x_λ(n·LT_ƒ)}X(z)=[X₀(z) . . . X₁(z) . . . X_L−1(z)]^T  Eq. 13
  • with A=0 . . . L−1The efficiency of the polyphase realisations (as in Eqs. 10 and 12) lies in the fact that all filter operations are performed at the lowest rate, i.e. at 1/(LT_ƒ) instead of at 1/T_ƒ. The average number of multiplications per output sample and per T_ƒfor a polyphase interpolator (or decimator) is given in Eq. 14.

$\begin{array}{cc}\#M=\frac{N+1}{L}& \left(\mathrm{Eq}.14\right)\end{array}$

However, the h(kT_ƒ) (anti-)symmetry generally does not yield intra-phase (anti)-symmetry in most h_λ(nLT) phases. The 2-fold decomposition for an even (N=8) order impulse response h(kT_ƒ) as shown in Eq. 15 is one example of an exception. Since h_8=i=h_i, both phases H₀(z) and H_f(z) are symmetric.H₀(z)=h₀+h₂z⁻¹+h₄z⁻²+h₆z⁻³+h₈z⁻⁴ H₁(z)=h₁+h₃z⁻¹+h₅z⁻²+h₇z⁻³  (Eq. 15)In Eq. 16 (where L=3 and N=11), H₁(z) is symmetric for a symmetric H(z), but the other phases H₀(z) and H₂(z) are not symmetric.H₀(z)=h₀+h₃z⁻¹+h₆z⁻²+h₉z⁻³ H₁(z)=h₁+h₄z⁻¹+h₇z⁻²+h₁₀z⁻³ H₂(z)=h₂+h₅z⁻¹+h₈z⁻²+h₁₁z⁻³  (Eq. 16)However, in general, the multiplication reduction offered by filter response (anti-)symmetry, as in (Eq. 4) and (Eq. 5), is partially or completely lost with a polyphase realisation.

SUMMARY

The present invention aims to provide an integer factor sample rate conversion circuit, wherein the benefits of a symmetrical or asymmetrical impulse response on the one hand and those of a polyphase realisation on the other hand are combined.

The present invention relates to a circuit for converting the sample rate of a digital signal, comprising

• • an input for applying the digital signal,
  • a conversion filter having either a symmetrical or anti-symmetrical impulse response and implemented as a plurality of subfilters in parallel, each subfilter having a symmetrical or anti-symmetrical response derived from (a combination of) components of a polyphase decomposition of the impulse response,
  • combining means deriving from said applied digital signal input signals of said plurality of subfilters or for combining output signals of said plurality of subfilters into a digital signal with converted rate,
  • an output for outputting the digital signal with converted sample rate.

In a preferred embodiment the combining means are arranged for combining and interpolating output signals of the subfilters. The combining means further comprise means for adding and multiplying signals. The described circuit then acts as an L-factor interpolator.

In another preferred embodiment the combining means are arranged for decimating the input digital signal and for combining input signals to the subfilters. The combining means further comprise means for adding and multiplying signals. The circuit for sample rate conversion then advantageously further comprises adder means for summing output signals of the subfilters. The described circuit then acts as an L-factor decimator.

In another aspect the invention relates to an integrated circuit comprising a circuit for sample rate conversion as described.

SHORT DESCRIPTION OF THE DRAWINGS

FIG. 1 represents an L-factor interpolator circuit according to the invention.

FIG. 2 represents an L-factor decimator circuit according to the invention.

DETAILED DESCRIPTION

In the description of the invention below a Finite Impulse Response (FIR) with a symmetrical impulse response h(k) of length N+1 is assumed. Derivations for anti-symmetrical finite impulse response filters are similar and can readily be performed by a person skilled in the art. The filter is used as anti-imaging or anti-aliasing filter for L-factor interpolation or decimation, respectively.

The present invention aims at exploiting the h(k) symmetry and so to reduce the number of multiplications in a polyphase implementation, i.e. further than the factor L reduction in Equation 14.

The reduction is based on the fact that for each H_λ(z) that is not symmetrical by itself (“intra” symmetrical), a polyphase component with the “flipped” response exists. Define two transfer functions of order P, A(z) and B(z), as complementary if equation 17 is true. A(z) then is a “flipped” version of B(z), and vice versa.A(z)=z^−PB(z⁻¹)  (Eq. 17)First it is shown that each polyphase component H_λ(z) has a complement H_κ(z), according to equation 17, with P and κ given in equations 18 and 19, respectively. Note that P is always an integer number.

$\begin{array}{cc}P=\frac{N-\lambda -\left(N-\lambda \right)\mathrm{mod}L}{L}& \left(\mathrm{Eq}.18\right)\\ \kappa =\left(N-\lambda \right)\mathrm{mod}L& \left(\mathrm{Eq}.19\right)\end{array}$ Hence, it has to be proven that equation 20 is an identity.H_λ(z)=z^−PH_κ(z⁻¹)  (Eq. 20)Substituting (Eq. 19) yields (Eq. 21)H_λ(z)=z^−PH_{(N−λ)mod L}(z_{31 1})  (Eq. 21)Using the definition of Z-transform yields equation 22.

$\begin{array}{cc}\sum _{i=-\infty }^{i=\infty }{z}^{-i}{h}_{\lambda }\left(i\right)=\sum _{j=-\infty }^{j=\infty }{z}^{-\left(P-j\right)}{h}_{\left(N-\lambda \right)\mathrm{mod}L}\left(j\right)& \left(\mathrm{Eq}.22\right)\end{array}$ Substituting equation 8 yields equation 23.

$\begin{array}{cc}\sum _{i=-\infty }^{i=\infty }{z}^{-i}h\left(\lambda +\mathrm{Li}\right)=\sum _{j=-\infty }^{j=\infty }{z}^{-\left(P-j\right)}h\left(\left(N-\lambda \right)\mathrm{mod}L+\mathrm{Lj}\right)& \left(\mathrm{Eq}.23\right)\end{array}$ Polynomes are equal if, for each power of z, corresponding coefficients are equal. So, substituting j with P−i yields equation 24.h(λ+Li)=h((N−λ)mod L+L(P−i))  (Eq. 24)Using equation 2 yields equation 25.h(λ+Li)=h(N−(N−λ)mod L−L(P−i))  (Eq. 25)Substituting Equation 18 yields equation 26.

$\begin{array}{cc}h\left(\lambda +\mathrm{Li}\right)=h\left(N-\left(N-\lambda \right)\mathrm{mod}L-L\left(\frac{N-\lambda -\left(N-\lambda \right)\mathrm{mod}L}{L}-i\right)\right)h\left(\lambda +\mathrm{Li}\right)=h\left(N-\left(N-\lambda \right)\mathrm{mod}L-N+\lambda +\left(N-\lambda \right)\mathrm{mod}L+\mathrm{Li}\right)h\left(\lambda +\mathrm{Li}\right)=h\left(\lambda +\mathrm{Li}\right)\left(Q.E.D.\right)& \left(\mathrm{Eq}.26\right)\end{array}$ It is to be noted that if λ=(N−λ)mod L, the complement of H_λ(z) is H_λ(z) itself, in which case H_λ(z) is symmetrical. The fact that all polyphase components H_λ(z) are complementary, either with H_λ(z) itself or with another polyphase component, can be exploited to reduce the number of multiplications. This is elaborated next.

Define the L×L matrix A=[α_i,j], constructed row by row α_λ^T according to the following procedure (given in pseudocode):

for (λ = 0; λ L; ++λ)// start with row 0, end with row L-1
κ = (N − λ)modL; //find complementary phase with Eq. 19
if (κ == λ)     // symmetrical phase
// type 1 row: all 0 except 1 on diagonal
aλT=⁢0aλ,λ=⁢1;(Eq.⁢27)
else if (κ > λ) //2 phases with flipped response
// row of type 2: all 0 except two 1's
aλT=⁢0⁢aλ,λ=⁢aλ,Κ=1;//(Eq.⁢28)
// row of type 3: all 0 except single 1 and −1
aΚT=⁢0;aΚ,λ=⁢1;aΚ,Κ=⁢-1;//(Eq.⁢29)

Matrix A has the following properties:

• • 1. A^T=A (A is symmetric)
  • 2. A is invertible.
  • 3. inner product <α_i^T,α_j>=0 if i≠j (the rows in A are orthogonal)
  • 4. For the three types of rows a_i^T defined above
    • Type 1: <a_i^T,a_i>=1
    • Type 2: <a_i^T,a_i>=2
    • Type 3: <a_i^T,a_i>=2Using properties 3 and 1, A^TA is a diagonal matrix (Eq. 30).

$\begin{array}{cc}\begin{array}{c}{A}^{T}A=\left[\begin{array}{ccc}\langle a_0^T,a_0\rangle & \dots & \langle a_0^T,a_{L-1}\rangle \\ \dots & \dots & \dots \\ \langle a_{L-1}^T,a_0\rangle & \dots & \langle a_{L-1}^T,a_{L-1}\rangle \end{array}\right]\\ =\left[\begin{array}{ccc}\langle a_0^T,a_0\rangle & \dots & 0\\ \dots & \dots & \dots \\ 0& \dots & \langle a_{L-1}^T,a_{L-1}\rangle \end{array}\right]\end{array}& \left(\mathrm{Eq}.30\right)\end{array}$ Equation 31 defines an L×L matrix D:

$\begin{array}{cc}D=\left[\begin{array}{ccc}\frac{1}{\langle a_0^T,a_0\rangle }& \dots & 0\\ \dots & \dots & \dots \\ 0& \dots & \frac{1}{\langle a_{L-1}^T,a_{L-1}\rangle }\end{array}\right]& \left(\mathrm{Eq}.31\right)\end{array}$ Then equation 32 is true, with I_L×L the L×L identity matrix.DA^TA=I_L×L  (Eq. 32)Substituting (Eq. 32) into (Eq. 10) yields equations 33 and 34.G(z)=A H(z)  (Eq. 33)Y(z))=DA^TG(z)X(z)  (Eq. 34)

Next it is pointed out why applying the expression of equation 34 is more efficient than that of Eq. 10 in terms of number of multiplications.

• • 1. G(z) can be precomputed (offline), so Eq. 33 does not take any real-time computing resources, and hence only Eq. 34 is considered.
  • 2. A^T is very sparse and contains only 1 or −1 as non-zero values. Hence, multiplication with A^T has no multiplication cost.
  • 3. D is a diagonal matrix. Using property 4, the values

$\frac{1}{\langle a_i^T,a_i\rangle }$ on its diagonal are either 1 or ½. Hence, multiplicating with D involves virtually no multiplication cost.

• • 4. Three types of G_i(z) as elements of G(z) exist, depending on the row type a_i^T in A^T.Type 1:

Since (N−i)mod L=i, H_i(z) is its own complement, i.e. is symmetrical.

Using (Eq. 27) and (Eq. 33), G_i(z)=H_i(z) and so G_i(z) inherits the symmetry present in H_i(z).

Type 2:

Using (Eq. 28)G_λ(z)=H_λ(z)+H_κ(z)Using (Eq. 19)G_λ(z)=H_λ(z)+H_{(N−λ)mod L}(z)Replace z by z⁻¹ and multiply both sides with z^−P z^{31 P}G_λ(z⁻¹)=z^−PH_λ(z⁻)+z^−PH_{(N−λ)mod L}(z⁻¹)Using equation 21 (which is true because Eq. 20 is proven to be true):z^−PG_A(z⁻¹)=H_{(N−λ)mod L}(z)+H_λ(z)z^−PG_λ(z⁻¹)=G_λ(z)Hence G_λ(z) is symmetric.Type 3:Using (Eq. 29):G_λ(z)=H_λ(z)−H_κ(z)Using (Eq. 19)G_λ(z)=H_λ(z)−H_{(N−λ)mod L}(z)Replace z by z⁻¹ and multiply both sides with z_−P z^−PG_λ(z⁻¹)=z^−PH_λ(z⁻¹)−z^−PH_{(N−λ)mod L}(z⁻¹)Using equation 21 (which is true because Eq. 20 is proven to be true):z^−PG_λ(z⁻¹)=H_{(N−λ)mod L}(z)−H_λ(z)z^−PG_λ(z⁻¹)=−G_λ(z)Hence G_λ(z) is anti-symmetric.

It has thus been shown that all elements G_i(z) are either symmetrical or anti-symmetrical functions of order P, with P given in (Eq. 18). Substituting P for N into (Eq. 7) and summing over all i=0 . . . L−1, averaged over L output samples yields the average number of multiplications per output sample #M (Eq. 35).

$\begin{array}{cc}\#M=\frac{1}{L}\sum _{i=0}^{L-1}\left(\lfloor \frac{N-i-\left(N-i\right)\mathrm{mod}L}{2·L}\rfloor +1\right)& \left(\mathrm{Eq}.35\right)\end{array}$ For N>>L,

$\#M\approx \lfloor \frac{N}{2·L}\rfloor +1,$ which is approximately a factor of two improvement versus (Eq. 14).The original polyphase filtering operation H(z) in Eq. 10 is replaced by a sequence of 3 operations (Eq. 34) applied in the order G(z), A^T, D.

FIG. 1 shows the corresponding schematic for an L-factor interpolator realisation. As represented by the arrows at the bottom in FIG. 1, the signal flows from left to right, starting with a scalar input signal X(z) and transformed consecutively by G(z), A^T and D, into the polyphase vector Y(z).

First, X(z) is multiplied with G(z), a vector with only symmetrical and anti-symmetrical transfer functions as elements. This fact can be exploited for multiplication reduction, as explained before.

Then, the signal is multiplied with A^T, a sparse vector with only 1 and −1 as non-zero values.

Then, the signal is multiplied with D, a diagonal matrix with either 1 or ½ on the diagonal.

Finally, the vector signal Y(z) is combined into the (interpolated) higher-rate, scalar output signal Y(z). This combination is the inverse operation of polyphase decomposition (Eq. 11). Note that this final stage has the behaviour of a parallel-to-serial conversion, or also of a fast commuting switch, picking in turn a value for Y(z) from each of the Y_λ(z) element.Depending on the actual value of (L,N), matrix A^T consists of a number of Type 1 rows (Eq. 27) and a number of Type 2 (Eq. 28) and Type 3 (Eq. 29) row pairs, as explained before. The example in FIG. 1 shows one d_ia_i^Tg_i(z) row for α_i^T of Type 1, i.e. i=(N−i)modL, and one row pair for j≠(N−j)modL, i.e. with rows α_i^T and α_(N−j)modL^T of Types 2 and 3, respectively.

Equation 36 is the L-phase decimator equivalent for (Eq. 34).Y(z)=G^T(z)AD^TX(z)  (Eq. 36)The same expression for #M as given in equation 35 applies. FIG. 2 shows the corresponding schematic for an L-factor decimator realisation. As represented by the arrows at the bottom in FIG. 2, the signal flows from left to right. First, according to Eq. 13, a serial-to-parallel converter performs a polyphase decomposition from the scalar input signal X(z) into the output vector X(z).Then, the vector X(z) is multiplied with diagonal matrix D^T, with either 1 or ½ on the diagonal.Next, the signal is multiplied with A, a sparse matrix with only 1 and −1 as non-zero values.Finally, a dot product with G^T(z) results in the scalar low rate (decimated) output signal Y(z). All elements of vector G^T(z) are either symmetrical or anti-symmetrical transfer functions. This can be exploited to reduce the number of multiplications, as explained before.Depending on the actual value of (L,N), matrix A consists of a number of Type 1 rows (Eq. 27) and a number of Type 2 (Eq. 28) and Type 3 (Eq. 29) row pairs.The example in FIG. 2 shows one row for a_i^T of Type 1, i.e. i=N−i)modL, and one row pair for j≠(N−j)modL, i.e. with rows a_i^T and α_(N−j)modL^T of Types 2 and 3, respectively.

Claims

1. Circuit for converting the sample rate of a digital signal, the circuit comprising an integer factor sample rate conversion circuit, wherein the benefits of a symmetrical or asymmetrical impulse response on the one hand and those of a polyphase realization on the other hand are combined, the circuit further comprising an input for applying said digital signal,a conversion filter having either a symmetrical or anti-symmetrical impulse response and a polyphase realization, the conversion filter implemented as a plurality of subfilters in parallel, each subfilter having a symmetrical or anti-symmetrical response derived from a combination of the conversion filter polyphase components, the combination including multiplying the digital signal only with factors of 1 and −1,combining means for combining said applied digital signal input signals of said plurality of subfilters or for combining output signals of said plurality of subfilters into a digital signal with converted sample rate, after multiplying the applied digital signal input signals of said plurality of subfilters or after multiplying the output signals of said plurality of subfilters, with factors 1 or ½,an output for outputting said digital signal with converted sample rate.

2. A circuit for converting the sample rate of a digital signal, comprising: an input for applying said digital signal,a conversion filter having either a symmetrical or anti-symmetrical impulse response and implemented as a plurality of subfilters in parallel, each subfilter having a symmetrical or anti-symmetrical response derived from components of a polyphase decomposition of said impulse response,combining means for deriving from said applied digital signal input signals of said plurality of subfilters or for combining output signals of said plurality of subfilters into a digital signal with converted sample rate, andan output for outputting said digital signal with converted sample rate,wherein said combining means are arranged for combining and interpolating output signals of said subfilters, said combining means further comprising means for adding and multiplying signals.

3. Circuit for sample rate conversion as in claim 2, whereby said combining means are arranged for decimating said input digital signal and for combining input signals to said subfilters, and combining means further comprising means for adding and multiplying signals.

4. Circuit for sample rate conversion as in claim 3, further comprising adder means for summing output signals of said subfilters.

5. An integrated circuit comprising a circuit for sample rate conversion as in claim 2.