The main voltage generator 211 receives the two external voltages VDDQ & VDD as inputs and generates the various CVDD voltages. The main voltage generator 211 down converts the external voltage VDQQ to generate various reference voltages equal to VDD multiplied by various ratios. For example, the resulting CVDD voltages generated by the main voltage generator 211 are CVDDH that is 1.2 times VDD, CVDDL that is 0.8 times VDD, CVDDLL1 that is 0.6 times VDD and CVDDLL2 that is 0.5 times VDD.
The reference voltage selector 213 selects one of these reference voltages in response to the power control signal. The power control signal can be a read/write control signal, word-line (row) decoder signal, bit-line (column) decoder signal or externally forced signal. The differential amplifier based voltage follower 216 includes two or more negative feedback differential amplifiers for generating a feedback control signal to the power control module 219 in order to maintain the output signals of the reference voltage selector 213 and the power control module 219 at the same level. The power control module 219 can be a single MOS device, combined PMOS and NMOS devices, or a single MOS device coupled with a push-pull device. The power control module 219 modulates the CVDD voltage level in response to the output of the differential amplifier based voltage follower 216. Thus the voltage management circuit 202 is able to generate CVDDH, VDD, CVDDL, CVDDLL1, or CVDDLL2 as shown in Table 1, in response to the operation mode of the SRAM core array 220.
The proposed embodiment of the present invention supplies different voltages during various modes of operation. When the SRAM is in a normal or read mode, the voltage management circuit 202 supplies the SRAM core array 220 with a voltage (CVDDH) that is always higher than SRAM periphery power supply voltage (VDD). A higher voltage makes the write operation (both accidental and intentional) very difficult, thereby improving the SNM. This, in turn, improves the stability of SRAM cell during the read operation.
The proposed embodiment of the present invention also improves the WTM. An objective of the write operation is to apply voltage to the SRAM cell that will cause its state to flip. A higher voltage makes the write operation more difficult. When the SRAM is in a write mode, the voltage management circuit 202 supplies the SRAM core array 220 with a voltage (CVDDL) that is lower than the SRAM periphery power supply (VDD), thereby resulting in an improved WTM.
The proposed embodiment of the present invention supplies a voltage VDD to SRAM core array 220 when the SRAM is in a pre-charge or standby mode, and supplies a low voltage CVDDLL1 or CVDDLL2 to the SRAM core array 220 when the SRAM is in a power-down or sleep mode. Optimizing CVDD to supply higher voltage only when required and a lower voltage that is a fraction of the VDD at other times saves power.
The SNM improvement of the present invention is graphically illustrated in
The WTM improvement of the present invention is graphically illustrated in
The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.