BRIEF DESCRIPTION OF THE DRAWINGS
A full understanding of the invention can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram in schematic form of a circuit breaker in accordance with an embodiment of the invention.
FIG. 2 is a flowchart of a routine including a foreground loop and a background loop executed by the microprocessor of FIG. 1.
FIG. 3 are plots of activity of the background loop, activity of the foreground loop, microprocessor internal clock frequency selection and line voltage versus time for the microprocessor of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
As employed herein, the term “modulation” or “modulate” or derivatives thereof means to vary (i.e., increase and decrease) the frequency of a signal (e.g., a clock signal of a processor).
The invention is described in association with a miniature circuit breaker, although the invention is applicable to a wide range of circuit interrupters.
Referring to FIG. 1, a miniature circuit breaker 2 includes separable contacts 4, an operating mechanism 6 structured to open and close the separable contacts 4, and a sensor 8 structured to sense current flowing through the separable contacts 4 between a line terminal 10 and a load terminal 12. The circuit breaker 2 also includes a processor, such as the example microcomputer (μC) 14 (e.g., without limitation, a Microchip PIC16F685 microcontroller, marketed by Microchip Technology Incorporated of Chandler, Ariz.), cooperating with the sensor 8 and the operating mechanism 6 to trip open the separable contacts 4, and a power supply 16 structured to at least power the μC 14. The power supply 16 is, for example, an alternating current (AC) to direct current (DC) (AC/DC) power supply which receives a line-to-neutral voltage 36 between a neutral terminal 18 and a common reference node 20 that is disposed between the separable contacts 4 and the sensor 8. The AC/DC power supply 16 provides a suitable DC voltage 22 to the μC 14 and, as needed, powers an analog sensing circuit, such as the example voltage and current analog sensing circuit 24.
The μC 14 includes a configurable clock circuit 26 which supplies a configurable clock 28 to a system clock input 30 of a microprocessor (μP) 32. The μP 32 includes a routine 34 structured to reduce current consumption from the power supply 16 through modulation of the configurable clock 28, as will be described.
The voltage and current analog sensing circuit 24 receives inputs of the line-to-neutral voltage 36 from the neutral terminal 18 and the load neutral terminal 38, a voltage 40 representative of the current flowing through the current sensor 8, and signals 42,44 from the secondary 46 of a current transformer (CT) 48, which detects a ground fault condition responsive to any significant difference between the line and neutral currents. The various voltage and current signals from the voltage and current analog sensing circuit 24 are input by a plural channel analog to digital converter (ADC) 50 of the μC 14 and are converted to corresponding digital values for input by the μP 32.
Responsive to one or more current conditions as sensed from the voltage 36, the voltage 40 and/or the signals 42,44, the μP 32 generates a trip signal 52 that passes through the μC 14 to output 54 to turn SCR 56 on. The SCR 56, in turn, energizes a trip solenoid 58 and, thereby, actuates the operating mechanism 6 to trip open the separable contacts 4 in response to an overvoltage, an arc fault, a ground fault or other trip condition. The trip solenoid 58 is, thus, a trip actuator cooperating with the μP 32 and the operating mechanism 6 to trip open the separable contacts 4 responsive to one of the different trip conditions from the μP 32. A resistor 60 in series with the coil of the solenoid 58 limits the coil current and a capacitor 62 protects the gate of the SCR 56 from voltage spikes and false tripping due to noise.
FIG. 2 shows one example structure of the routine 34 for the μC-based miniature circuit breaker 2 of FIG. 1. A main “foreground” loop 70 processes data that is periodically collected (e.g., acquired) in response to a periodic timer interrupt 83 from a timer 71 (FIG. 1) by a “background” loop 82. The μP system clock input 30 (FIG. 1) operates at a relatively high frequency (e.g., without limitation, about 8 MHz) only when data processing by the foreground loop 70 or data acquisition by the background loop 82 occurs. During the remainder of the time, the μP internal clock frequency is reduced (e.g., without limitation, by a factor of 64 to about 125 kHz), to minimize power supply current consumption by the μC 14.
In the main foreground loop 70, at 72, it is determined if 16 new sampling interrupts occurred. If not, then the loop 70 continues to wait at 73 before checking the test at 72. Otherwise, if 16 new sampling interrupts have occurred (e.g., flag 91 is true), then, at 74, the μP internal system clock input 30 is set to high speed (e.g., without limitation, about 8 MHz). Next, at 76, the data collected in response to the various timer interrupts by the background loop 82 (e.g., without limitation, for arc fault, ground fault, overvoltage and/or overcurrent conditions) is suitably processed using any known or suitable techniques. Before starting step 76 (e.g., as part of step 74), a flag 77 is set. Then, before starting step 78 (e.g., at the end of step 76), the flag 77 is reset. Alternatively, the flag 77 may be reset after step 78 instead of after step 76. Next, at 78, it is determined if there is a fault condition. If so, then at 79, the μP 32 trips the circuit breaker 2 by outputting the trip signal 52 (FIG. 1). If not, then, at 80, the μP internal system clock input 30 is set to low speed (e.g., without limitation, about 125 kHz) before execution resumes at 72. Lowering this frequency when the routine 34 is otherwise idle, reduces current consumption from the power supply 16 (FIG. 1). Hence, the foreground loop 70, at 76,78, determines whether a fault condition has occurred and responsively trips the circuit breaker 2 responsive to the fault condition at 79, or lowers the frequency of the μP system clock input 30 responsive to the absence of the fault condition at 80.
In response to the periodic timer interrupt 83 (e.g., without limitation, about 16 times per half-cycle of the line-to-neutral voltage) from the timer 71 (FIG. 1), the background loop 82 performs data acquisition. Thus, the timer 71 interrupts the foreground loop 70 a plurality of times per voltage half-cycle to collect the data by the background loop 82. This background loop 82 periodically collects information about the condition of the protected circuit and the circuit breaker 2. The timer interrupt 83 may occur, for example, during any of steps 70,72,73,74,76,78,80. Next, at 84, the μP internal system clock input 30 is set to high speed (e.g., without limitation, about 8 MHz). Then, steps 86, 88 and 90 respectively sample the line current, the ground current and the line-to-neutral voltage. When the background loop 82 has collected a predetermined count (e.g., without limitation, 16) of sets of samples corresponding to the same count of timer interrupts, the background loop passes a flag 91 to the foreground loop 70 to cause the foreground loop to process the data at step 76.
Next, at 92 of the background loop 82, it is determined if the timer interrupt 83 occurred while the foreground loop 70 was processing data. If the flag 77 is reset, then this test is false and the μP internal system clock input 30 is set to low speed (e.g., without limitation, about 125 kHz) at 94. Otherwise, the flag 77 is set, the test at 92 is true, and the UP internal system clock input 30 remains at high speed. In that event, or after step 94, the end of interrupt is executed at 96 and execution resumes, again, in the foreground loop 70. In this manner, the routine 34 lowers, at 80 or 94, the frequency of the internal system clock input 30 when the background loop 82 is not periodically collecting the data and when the foreground loop 70 is not processing data from the background loop 82.
FIG. 3 shows the operation of the circuit breaker routine 34 of FIG. 2 and, in particular, the activity 100 of the background loop 82 and the activity 102 of the foreground loop 70 of FIG. 2. The example timer interrupt 83 (FIGS. 1 and 2) initiates the background loop 82 sixteen times per voltage half-cycle to collect data, as shown at 104 or 106. When the background loop 82 has collected sixteen sets of samples, it passes the flag 91 telling the foreground loop 70 to process the data. The timer interrupt 83 for the background loop 82 interrupts processing by the foreground loop 70, as shown, for example, at 108, 110 or 112.
FIG. 3 also shows that when neither the foreground loop 70 nor the background loop 82 of FIG. 2 is active, the frequency of the μP internal system clock input 30 can be reduced (e.g., without limitation, from 8 MHz to 125 kHz), for example, at 114, 116 or 118, or whenever the signal 120 is low, in order to minimize the current consumption of the μC 14. In this particular example, the foreground and background loops 70,82 are active only about 50% of the time. Therefore, the μP routine 34 operates in a reduced clock frequency/reduced current consumption mode during the remaining about 50% of the time, thereby significantly lowering the average current consumed by the μC 14. This reduces the demand on the power supply 16 (FIG. 1) that supplies the μC 14, which results in less thermal dissipation and stress (e.g., without limitation, in resistor-coupled power supplies of the type used in, for example, miniature circuit breakers), higher efficiency and potentially lower component costs. Otherwise, when the signal 120 is high (e.g., at 122, 124 or 126), the μP routine 34 operates in the normal clock frequency/normal current consumption mode when either one of the loops 70,82 is active.
A significant advantage of operating the circuit breaker μP 32 at a reduced clock frequency is that it consumes relatively less power supply current. For example, the circuit breaker power supply current consumption is reduced by lowering the frequency of the μP internal system clock input 30 during any time interval when the routine 34 is idle. Reducing the current needed to power the electronics in, for example, the miniature circuit breaker 2 is critical to reducing the thermal dissipation and average losses in the circuit breaker electronics power supply 16.
While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the claims appended and any and all equivalents thereof.
Patent Application
20080010472
