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The circuit testing apparatus 200 of this embodiment comprises a signal transformation module 220, a meter 240, a logic tester 260, and a waveform generator 280. The logic tester 260 is a test machine capable of performing digital operations. Aside from circuitry for performing digital operations, the logic tester 260 further comprises a continuous built-in test (C-Bit) control unit 262. Through the C-Bit control unit 262, the logic tester 260 controls the operations of the signal transformation module 220 and the waveform generator 280 according to the test requirements. In addition, the logic tester 260 further comprises a general-purpose interface bus (GPIB) 264, which allows the logic tester 260 to receive a digital measuring result DMR from the meter 240.
The waveform generator 280 is controlled by the logic tester 260 and provides an analog input signal AIS to the DUT 110 set on the DUT board 120. The DUT 110 processes the analog input signal AIS to generate an analog output signal AOS. The signal transformation module 220 converts the analog output signal AOS into a DC signal DCS, which may be a DC voltage or a DC current. The meter 240 measures the DC signal DCS to generate a digital measuring result DMR, which digitally represents the voltage or current level of the DC signal DCS. Finally, the logic tester 260 determines a test result for the DUT 110 according to the digital measuring result DMR.
The signal transformation module 220 is responsible for converting an analog signal into a DC signal. For example, the signal transformation module 220 may comprise component(s) selected from a component group consisting of amplifiers, Notch filters, A weighting filters, high-pass filters, low-pass filters, and RMS-to-DC converters.
For example, when performing a noise test on the DUT 110, the Notch filter 320, the high-pass filter 340, and the low-pass filter 350 can be bypassed. With the amplifier 310, which is used to provide +40 dB signal amplifying, the Aweighting filter 330, and the RMS-to-DC converter 370, the DC signal DCS can be generated according to the analog output signal AOS. After the meter 240 measures the DC signal DCS to generate the digital measuring result DMR, the logic tester 260 can accordingly determine a noise test result for the DUT 110.
In another example, when performing a total harmonic distortion (THD) test on the DUT 110, the amplifier 310, the Notch filter 320, the Aweighting filter 330, the high-pass filter 340, the low-pass filter 350, and the amplifier 360 can be bypassed while only the RMS-to-DC converter 370 is used to convert the analog output signal AOS into the DC signal DCS. Assume that the digital measuring result DMR generated by the meter 240 is A under this situation. Then, the A weighting filter 330 is bypassed while the amplifier 310 is utilized to provide +20 dB signal amplifying. In addition, the Notch filter 320 is utilized to perform notch filtering with −80 dB signal amplifying and a 1 kHz notch frequency; the high-pass filter 340 is utilized to perform high-pass filtering with a 400 Hz pass band frequency; the low-pass filter 350 is utilized to perform low-pass filtering with a 30 kHz pass band frequency; the amplifier 360 is utilized to provide +40 dB signal amplifying; and the RMS-to-DC converter 370 is utilized to generate the DC signal DCS. Assume the digital measuring result DMR generated by the meter 240 is B under this situation. After the values A and B are obtained, the logic tester 260 can determine the THD (%) as follows:
When more than one channel of the DUT 110 is going to be tested, the multi-channel testing structures shown in
In the embodiment shown in
In the embodiments of the present invention, a signal transformation module is utilized to convert an analog output signal generated by a DUT into a DC signal. A meter and a logic tester can be used to determine a test result for the DUT. No mixed-signal tester is required in the embodiments of the present invention. Since the cost of the mixed-signal tester is much more expensive than that of the meter and the logic tester, the overall cost of each of the embodiments of the present invention will be much lower than that of the prior art. In addition, a lot of testing time can be saved by the testing structures proposed by the present invention.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
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095208770 | May 2006 | TW | national |