Patent Application
20240428831
This application relates to integrated circuits, and more particularly to an integrated circuit with a low-power charge-sharing light-sleep mode.
An integrated circuit embedded memory will typically have various operating modes in which a memory power supply voltage for the embedded memory is varied according to the operating mode. In a default mode (which may also be denoted as a normal mode), the memory power supply voltage is sufficiently elevated for increased memory speed. In contrast, the memory power supply voltage is decreased for a light-sleep mode or even discharged to ground during a deep-sleep mode. For example, during the deep-sleep mode, head switch transistors that intervene between a memory power supply voltage rail and the memory are switched off so that the memory is powered down. In the light-sleep mode, the head switch transistors may also be switched off so that the memory may be powered through diode-connected transistors that couple between the memory power supply voltage rail and the memory. The diode-connected transistors lower the memory power supply voltage by a threshold voltage drop. In this fashion, leakage currents are reduced during the light-sleep mode due to the reduced memory power supply voltage yet the memory may retain its binary contents and also revert back to the active mode relatively quickly.
In accordance with an aspect of the disclosure, a memory is provided that includes: a bitcell array having a first power supply node for receiving a memory power supply voltage; a voltage rail for a memory power supply voltage; an at least one first transistor having a source coupled to the voltage rail and a drain coupled to the first power supply node; and a second transistor having a source coupled to a gate of the at least one first transistor and having a drain coupled to the first power supply node.
In accordance with another aspect of the disclosure, a method of powering a circuit is provided that includes: switching on a diode-connecting transistor that couples between a gate and a drain of an at least one head switch transistor to diode connect the at least one head switch transistor during a light-sleep mode for the circuit; powering the circuit through the at least one head switch transistor while the diode-connecting transistor is switched on during the light-sleep mode for the circuit; switching off the diode-connecting transistor to return the at least one head switch transistor to a non-diode-connected state during an active mode for the circuit; and powering the circuit through the at least one head switch transistor while the diode-connecting transistor is switched off during the active mode for the circuit.
In accordance with yet another aspect of the disclosure, an integrated circuit is provided that includes: a voltage rail for a power supply voltage; a circuit having a power supply node; and an at least one head switch transistor coupled between the voltage rail and the power supply node, wherein the at least one head switch transistor is configured into a diode-connected state during a light-sleep mode for the circuit and is configured into a non-diode-connected state during an active mode for the circuit.
These and other advantageous features may be better appreciated through the following detailed description.
Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
A memory typically has several operating modes that correspond to different power supply voltage levels. In a default mode of operation, the memory power supply voltage is relatively elevated so that the memory speed is enhanced. Conversely, the memory power supply voltage is discharged in a deep-sleep mode. But in a light-sleep mode, the memory power supply voltage lies between these two extremes. In the light-sleep mode, the memory power supply voltage is sufficient for data retention but is reduced as compared to the default level. In particular, a light-sleep mode as defined herein exists when the bitcells are powered through a diode connection to a voltage rail for a power supply voltage. As compared to the power supply voltage on the voltage rail, the resulting memory power supply voltage for the bitcells during the light-sleep mode is reduced by a transistor threshold voltage drop due to the diode coupling of the bitcells to the voltage rail. During the default mode, the diode coupling is disabled such that the memory power supply voltage substantially equals the power supply voltage on the voltage rail.
To advantageously switch between the default and light sleep modes, a selectively diode-connected head switch transistor(s) is disclosed to provide a light-sleep mode of operation. During the normal mode of operation, the diode connection of the head switch transistors is open circuited. The head switch transistors conduct normally during the active mode such that they pass a memory power supply voltage to the memory with essentially no voltage drop. But the diode connection is closed during the light-sleep mode, which causes the head switch transistors to introduce a transistor threshold voltage drop in the memory power supply voltage as it passes through the head switch transistors to the memory. In a deep-sleep mode, the head switch transistors may be switched off so that the memory is powered down.
An example memory 100 with an advantageous light-sleep mode is shown in
A source of each of the head switch transistors P1, P2, P3, and P4 couples to a voltage rail for a memory power supply voltage (VDD) whereas a drain of each of these head switch transistors couples to the power supply node 140. During the active mode, the head switch transistors are not diode connected and are fully on. The bitcell array power supply voltage that powers the bitcell array 110 during the active mode is thus virtually equal to the memory power supply voltage because the parallel arrangement of the fully switched-on head switch transistors P1 through P4 introduce relatively little voltage loss. However, it will be appreciated that just one head switch transistor may be used to power bitcell array 110 in alternative implementations. Head switch transistors P1 through P4 are each an example of an at least one first transistor having a source coupled to the voltage rail and a drain coupled to the first power supply node 140. The bitcell array power supply voltage may also be denoted as a virtual power supply voltage VDD (virtual VDD) during the active mode since the bitcell array power supply voltage is virtually equal to the memory power supply voltage VDD during the active mode.
During a deep-sleep mode, the head switch transistors P1 through P4 are off. To switch these transistors off during the deep-sleep mode, an active-low deep-sleep mode signal (deep sleep n) is asserted. Since the deep-sleep mode signal is active low, the deep-sleep mode signal is asserted (having a binary true state) by being discharged to ground. An inverter 105 inverts the deep-sleep mode signal to drive a gate of each of the head switch transistors P1 through P4. An output signal of the inverter is thus charged to the memory power supply voltage during the deep-sleep mode to fully switch off the head switch transistors P1 through P4. The bitcell array 110 is then powered down during the deep-sleep mode and the bitcell array power supply voltage discharged to ground.
A PMOS transistor P5 couples between the gates of the head switch transistors P1 through P4 and the first power supply node 130 to accommodate the selective diode connection of these head switch transistors. Transistor P5 may thus also be denoted as a diode-connecting transistor. An active low light-sleep mode signal (light sleep n) on a first node drives the gate of transistor P5. Thus, when the light-sleep mode signal is asserted by being discharged to begin the light-sleep mode, the head switch transistors P1 through P4 are diode connected. Each of the head switch transistors P1 through P4 then introduces a transistor threshold voltage drop between the memory power supply voltage VDD and the bitcell array power supply voltage at the first power supply node 140. During the light-sleep mode, the bitcell array power supply voltage may thus also be denoted as a light-sleep virtual power supply voltage (light sleep VDD). This reduction in the bitcell array power supply voltage reduces leakage current losses in the bitcell array 110 during the light-sleep mode. But note that the head switch transistors P1 through P4 were not switched off during the light-sleep mode. In contrast, suppose that the head switch transistors P1 through P4 were switched off during the light-sleep mode and the bitcell array 140 powered through separate diode-connected transistors (not illustrated). As compared to the use of such separate diode-connected transistors, the selective diode connection of the head switch transistors P1 through P4 saves an appreciable amount of switching power that would otherwise be consumed with the switching off and on of the head switch transistors in the transitions between the active and light-sleep modes. Transistor P5 is an example of a second transistor having a source coupled to a gate of the at least one first transistor (head switch transistors P1 through P4) and having a drain coupled to the first power supply node 140.
During the light-sleep mode, the deep-sleep mode signal is de-asserted by being charged to the memory power supply voltage. To prevent inverter 105 from discharging the gates of the head switch transistors P1 through P4 during the light-sleep mode, the light-sleep mode signal drives a gate of an n-type metal-oxide semiconductor (NMOS) transistor M1 that couples between a ground node of the inverter 105 and ground. With the light-sleep mode signal asserted by being discharged to ground, transistor M1 is switched off to prevent inverter 105 from grounding the gates of the head switch transistors P1 through P4 during the light-sleep mode. Inverter 105 may also be denoted herein as a second inverter. Transistor M1 is an example of a sixth transistor having a first terminal coupled to a ground terminal of the second inverter (105), a second terminal coupled to ground, and a gate coupled to the first node for the light-sleep mode signal.
The SRAM periphery 115 receives a memory periphery power supply voltage through a second power supply node 145 that couples to a drain of a PMOS head switch transistor P8. Transistor P8 may also be denoted herein as a third transistor. A source of the head switch transistor P8 couples to the memory power supply voltage rail. An inverter 125 inverts the deep-sleep mode signal to control the gate of the head switch transistor P8. The inverter 125 may also be denoted herein as a third inverter. During the deep-sleep mode, the head switch transistor P8 switches off due to the inversion of the deep-sleep mode signal to cause the memory periphery 115 to power down. During the active mode (and also the light-sleep mode), the head switch transistor P8 is fully on such that the memory periphery power supply voltage is virtually equal to the memory power supply voltage VDD. The memory periphery power supply voltage may thus also be denoted as a virtual VDD or active VDD during the active and light-sleep modes. Note that in this implementation of memory 100, the memory periphery 115 does not practice the light-sleep mode. However, in alternative implementations, head switch transistor P8 may be selectively diode connected analogously as discussed for the head switch transistors P1 through P4 such that the memory periphery 115 may also have a light-sleep mode. In other alternative implementations, the head switch transistor P8 may be replaced by a plurality of head switch transistors arranged in parallel as discussed for head switch transistors P1 through P4.
The transistor threshold voltage drop in the bitcell array power supply voltage introduced by the switching on of transistor P5 may cause a delay in the transition from the light-sleep mode to the active mode. In that regard, the first power supply node 140 may have an appreciable amount of capacitance, which affects the voltage charging time. With the bitcell array power supply voltage being lower than the memory power supply voltage by a full transistor threshold voltage drop, there may be too much delay required to transition the bitcell array 110 from the light-sleep mode to the active mode. To slightly increase the bitcell array power supply voltage above a transistor threshold voltage drop from the memory power supply voltage during the light-sleep mode so as to reduce the transition time, a PMOS transistor P6 may have its source coupled to the first power supply node 140 and a drain coupled to the second power supply node 145. The light-sleep mode signal drives a gate of transistor P6 such that transistor P6 is on during the light-sleep mode and is off during the active and deep-sleep modes. Transistor P6 is relatively small compared to the head switch transistors. Recall that the second power supply node 145 is charged to the virtual VDD during the light-sleep mode (and also during the active mode). Due to the relatively small size of transistor P6, it cannot charge the first power supply node 140 to the virtual VDD during the light-sleep mode despite being fully on. Thus, the bitcell array power supply voltage during the light-sleep mode is slightly increased with respect to the threshold voltage drop from the memory power supply voltage that would otherwise exist if just transistor P5 were on without the presence of transistor P6. Since the bitcell array power supply voltage is thus only slightly increased from transistor P6 being on, leakage currents are still advantageously reduced during the light-sleep mode yet the transition delay from the light-sleep mode to the active mode may also be reduced. Transistor P6 is an example of a fourth transistor having a first terminal coupled to the second power supply node 145, a second terminal coupled to the first power supply node 140, and a gate coupled to the first node for the light-sleep mode signal.
To further reduce the transition time from the light-sleep mode back to the active mode, an inverter 120 may invert the light-sleep mode signal to drive a gate of a PMOS transistor P7 that couples in parallel with transistor P6 between the second power supply node 145 and the first power supply node 140. Transistor P7 is thus off during the light-sleep mode and on during the active mode. The virtual VDD at the second power supply node 145 may then conduct through transistor P7 at the initiation of the active mode from the light-sleep mode to charge the first power supply node 140 more quickly towards the memory power supply voltage. Transistor P7 is an example of a fifth transistor having a first terminal coupled to the second power supply node 145 and a second terminal coupled to the first power supply node 140. Similarly, the inverter 120 is an example of a first inverter having an input terminal coupled to the first node for the light-sleep mode signal and having an output terminal coupled to a gate of the fifth transistor.
An integrated circuit 200 may include the memory 100 as shown in
The selective diode connection of a head switch transistor(s) as disclosed herein is not limited to the powering of a memory. For example, a digital circuit 305 in an integrated circuit 300 may be powered by a selectively diode-connected PMOS head switch transistor P9 (it will be appreciated that more than one head switch transistor may replace head switch transistor P9 in alternative implementations). A source of the head switch transistor P9 couples to a power supply voltage rail for a power supply voltage VDD. A drain of head switch transistor P9 couples to a power supply node for the digital circuit 305. During an active mode for the digital circuit 305, transistor P9 is fully on without a diode connection. During a light-sleep mode, a diode-connecting transistor P10 switches on to diode connect a gate of the head switch transistor P9 to the drain of the head switch transistor P9 (or equivalently, to couple the gate of the head switch transistor P9 to the power supply node 315). To initiate the light-sleep mode, a controller (not illustrated) asserts an active-low light-sleep mode signal (light sleep enable) that drives a gate of the diode-connecting transistor P10 to switch the diode-connecting transistor P10 on. During the active mode or during a deep-sleep mode for the digital circuit 305, the light-sleep mode signal is de-asserted by being charged to the power supply voltage VDD.
During the deep-sleep mode, the controller asserts an active-high deep-sleep mode input signal (deep sleep n in). An inverter 305 inverts this charged state of the deep-sleep mode input signal to discharge the gate of head switch transistor P9 through a switch S1 (e.g., a transmission gate). The active low light-sleep mode signal controls switch S1 so that switch S1 is closed while the light-sleep mode signal is de-asserted by being charged to the power supply voltage VDD and so that switch S1 is open while the light-sleep mode signal is asserted by being grounded. The head switch transistor P9 is thus switched off during the deep-sleep mode to power down the digital circuit 315. But during the light-sleep mode, switch S1 opens so that the diode connection of the head switch transistor P9 is not affected by the presence of switch S1.
Note that the integrated circuit 300 may include a plurality of digital circuits (not illustrated) analogous to digital circuit 305 that are also controlled by the deep-sleep mode input signal. These additional digital circuits would each be powered by an equivalent of the selectively diode-connected head switch transistor P9 such that they may each have a light-sleep mode. These additional digital circuits may also include an equivalent of switch S1 that would close during a deep-sleep and active modes but be opened during the light-sleep mode. To allow the deep-sleep input signal to also control a deep-sleep mode in these additional digital circuits, an inverter 310 inverts the output signal from the inverter 305 to produce an active low deep-sleep mode output signal (deep sleep n out) that would function as the deep-sleep mode input signal to a subsequent one (or all) of the additional digital circuits. In this fashion, some or all of the additional digital circuits may be in a deep-sleep mode while the digital circuit 305 is in the light-sleep mode.
A method of powering a circuit through a selectively diode-connected transistor will now be discussed with reference to the flowchart of
An integrated circuit having a selectively diode-connected head switch transistor(s) may be advantageously included in a variety of electronic systems. For example, as shown in
The disclosure will now be summarized in the following series of clauses:
Clause 1. A memory, comprising:
It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular implementations illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
