Patent Application
20230223942
Wireless 5G services, cloud computing, and streaming video applications are exponentially increasing, the demand for hi her transmission capacity on communication networks and their infrastructure. The ubiquitous demand for 10 Gigabit, 100 Gigabit, 400 Gigabit, and higher transmission speeds have introduced many challenges to the Service Providers and their wired, optical, and wireless network infrastructures. Central to these challenges are the reliable transport, delivery, and integrity of these 10 Gigabit, 100 Gigabit, 400 Gigabit, and higher transmission speed communication services. The Service Providers communication network, infrastructure, and operations are extremely complex and vast, supporting many different legacy, mature, mid new communication services. The Service Providers implement many different and unique 10 Gigabit, 100 Gigabit, 400 Gigabit, and higher speed communication services for transport within their complex network and for delivery to their customers. These high speed communication services are unique in their signal types, modulations, wavelengths, symbol, and bit rates, and framing structures. Each unique framing structure reflects specific framing formats, payload encapsulation and data capacity. In addition, these unique 10 Gigabit, 100 Gigabit, 400 Gigabit, and higher speed communication services have different methods of operations, maintenance, and administration.
The 10 Gigabit, 100 Gigabit, 400 Gigabit, and higher speed communication services are also subjected to severe performance degradation, intermittent interoperability, and poor reliability. Most importantly, the Service Providers lace very complex installation, maintenance, and repair, which are subjected to installation and maintenance errors and repair delays. The Service Providers face costly decline in revenue, excessive expenses, and customer dissatisfaction. To address the Service Provider's issues on performance and reliability challenges, communication equipment use clock data recovery (CDR) circuitry to interface these high speed communication signals. The CDR circuitry extracts or creates a clock from the communication signal. This retimed clock will then be used to regenerate or recreate the communication signal to correct signal and timing impairments. This re-clocked and regenerated communication signal will be used by the communication equipment to reliably process the communication signal for connection and interlace to the network.
To address the various unique signals and structures of 10 Gigabit and higher communication services supported by the Service Providers, the communication equipment is required to specifically provision the CDR circuitry to align and lock each unique communication service bit rates or wavelengths, extract the clock, and re-clock the incoming communication signal. The CDR circuitry is typically pre-provisioned and involves manual or semi-automatic provisioning. Prior attempts to do so have thus far been inadequate.
One such example of prior art circuitry 100 is illustrated in the diagram of
There are a number of disadvantages to the prior art circuitry 100 as shown in
A second such example of prior art circuitry 102 is illustrated in the diagram of
There are a number of disadvantages to the prior art circuitry 102 as shown in
A third such example of prior art circuitry 104 is illustrated in the diagram of
There are a number of disadvantages to the prior art circuitry 104 as shown in
A fourth such example of prior art circuitry 106 is illustrated in the diagram of
There are a number of disadvantages to the prior art circuitry 106 as shown in
The following prior art references provide general background information regarding the circuitry, systems, and methods on the alignment of communication services, and each are herein incorporated by reference:
U.S. Pat. No. 6,570.915 B1 entitled DSL Auto Baud issued to Sweitzer, et al, on May 27, 2003.
U.S. Pat. No. 9,559,905 B2 entitled Type-C Retimer State Machine and a Protocol for Inband Control and Configuration issued to Chen, et al, on Dec. 24, 2014.
U.S. Pat. No. 9,160,405 B1 entitled Self-Tuning High Speed Transceiver for IC Wireline Channel issued to Vareljian, et al. on Oct. 13, 2015.
U.S. Pat. No. 9,858,234 B2 entitled System Transparent Retimer issued to Chen, et al. on Jan. 2, 2018.
Presently, there is a need to automatically align and lock the CDR circuitry to various communication service bit rates and/or wavelength without manual, remote, or coordinated provisioning, while overcoming the inadequacies and disadvantages of such prior art, The circuitry, system(s), method(s), equipment and/or devices disclosed herein fulfill such a need.
The present disclosure provides circuitry, system(s), method(s), equipment and/or devices for automatically aligning or tuning on a communication signal bit rate or wavelength or a combination of wavelength and bit rate. When the communication signal is aligned and/or tuned, the signal's timing is extracted or recovered to re-clock and regenerate the communication signal. This communication signal is then re-clocked to remove timing impairments and then regenerated to correct for any signal impairments. This re-clocked and regenerated signal will be used by other equipment circuitry to reliably and accurately process the communication signal for interfacing with other networks and communication equipment. The circuitry, system(s), method(s), equipment and/or devices of the present disclosure do not require any technical craft person to locally provision the circuitry to align with multiple communication signal bit rates, wavelengths, or both. The circuitry, system(s), method(s), equipment and/or devices of the present disclosure also do not require remote provisioning, network management administration, or communication equipment coordination to align with multiple communication signal bit rates and wavelengths. In addition, the circuitry, system(s), method(s), equipment and/or devices of the present disclosure also do not require the deconstructing and analyzing of the communication signal structure, framing encapsulation, communication protocol, or imbedded payload messages, links, or identification codes to assist in the alignment of multiple communication signal bit rates or wavelengths.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will automatically align or tune and lock to the communication signal bit rate, wavelength, or both wavelength and bit rate to re-clock or re-time, and re-generate the communication signal by way of clock data recovery (CDR) and a microprocessor (MPU) circuitries. In another embodiment, the present disclosure will automatically align or tune and lock to the communication signal bit rate, wavelength, or both wavelength and hit rate to re-clock or re-time, and re-generate the communication signal by way of CDRs, an MPU, and receiver and transmitter circuitries.
In still another embodiment, the circuitry, system(s), method(s), equipment and/or devices of the present disclosure will automatically align or tune and lock to the communication signal bit rate, wavelength, or both wavelength and bit rate to re-clock or re-time the communication signal by way CDRs, an MPU, receiver and transmitter circuitries, and port (PORT) interfaces.
Numerous features and advantages of the circuitry, system(s), method(s), equipment and/or devices of the present disclosure include the following.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure automatically align and lock to a communication signal and re-clock the communication signal bit rate.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure automatically time to a communication signal wavelength,
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure automatically tune to a communication signal wavelength and align and lock to as communication signal bit rate.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure automatically tune to a communication signal wavelength and align and lock to a communication signal bit rate, and then re-clock the communication signal.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure automatically tune to a communication wavelength, align and lock to a communication signal bit rate, and re-clock the communication signal with any different communication wavelength.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will selectively provision at least a second CDR with a first CDR settings.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will selectively provision at least a second port (PORT) interface with a first port (PORT) interface settings.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure selectively use a communication service list to minimize time to align and lock on the communication signal.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure coordinate with components, modules, devices, or equipment to tune and lock on the communication signal wavelength and change the signal wavelength.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure use qualified events to minimize time on re-alignment, tuning, and lock on the communication signal. Qualified events include power loss, device or module removal, communication service changes, and signal integrity.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will eliminate any local or remote provisioning or processes to provision the communication signal bit rate or wavelength.
The circuitry, system(s), method(s) equipment and/or devices of the present disclosure will not require any additional circuitry or equipment communication to coordinate alignment or CDR settings.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will not require additional circuitry for local car remote provisioning and coordination, which results in lower costs.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will minimize user installation errors or remote provisioning errors.
The circuitry, system(s), method(s), equipment and/or devices of the present disclosure will generate revenue quickly by eliminating installation complexities and errors.
The circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure automatically align the communication signal using at least one clock and data rate recovery (CDR) circuitry and a microprocessor (MPU). Communication services can be represented by various communication signals with unique structures and bit rates. A partial list of these unique high speed communication signals are 10GELAN, 10GEWAN, CPRI7, eCPRI, OC-192 SONET, 10GFC, 16GFC, 28GFC, 32GFC, 64GFC, 128GFC, OTNIe, OTN2, OTN2e, USB3.1., G-PON, GE-PON, 10G-EPON, XG-PON, XGS-PON, NG-PON2, 25GS-PON, 50G-EPON, 50G-GPON, 100G/200GPON, Super-PON, and others.
In a second embodiment, the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, two CDR and a MPU are connected to two receive (RCV) circuitry.
In a third embodiment, the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, two CDRs and a MPU are connected to RCV and transmit circuitry (XMT).
In a fourth embodiment, the circuitry, system(s), method(s), equipment and/or device of the present disclosure, two CDRs and a MPU are connected to two RCVs and two XMTs.
In a fifth embodiment, the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, two CDRs, and MPU circuitry, and two PORTs are interconnected.
In a sixth embodiment, the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, two CDRs, a microprocessor (MPU), two RCV, and two PORTs are interconnected.
In a seventh embodiment, the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, two CDRs, a MPU, a RCV, a XML and two PORTs are interconnected.
In an eighth embodiment, the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, two CDRs, a MPU, a two RCV, a two XMTs, and two PORTs are interconnected.
There are different CDR circuitry design architectures, methodologies and approaches. The CDR circuitry architecture, design, and implementation are determined by the communication signal, the circuitry application, cost, supply chain, and/or manufacturing. The present disclosure utilizes any CDR circuitry or architecture appropriate to the communication service and application, equipment performance and design, and costs. For example, 10G and higher GPON communication service technologies require fast CDR synchronization for upstream burst-mode. A communication service with multilevel PAM-4 signal requires a non NRZ CDR circuitry such as a baud-rate CDR with a Mueller-Mueller phase detector. A 100 Gb/s quad-lane communication service may require a phase-interpolator (PI)-based clock and data recovery (CDR) using multi-phase delay-locked loop (MDLL).
The appropriate CDR circuitry detects the communication signal hit, phase, or symbol transitions to extract or calculate a clock or timing from the signal stream or a waveform. The extracted or recovered clock is used to align or tune to the incoming or received communication signal, reference Clock, or an external clock. The CDR will then re-clock the incoming or received communication signal to reduce timing impairments such as jitter, wander, and frequency mismatches. The CDR circuitry will regenerate the communication signal during the re-clocking process. The re-clocked and regenerated communication signal provides a very accurate and quality signal for other circuitry, devices, and/or networks to reliably interface. The clock data recovery circuitry (CDR) in this embodiment can be comprised of integrated circuits (hardware), software, or a combination of analog, digital, or analog and digital hardware and software. More specifically, the CDR can be implemented with discrete integrated circuits, field programmable gate arrays (FPGA), application specific integrated circuit (ASIC), system-on-a-chip (SoC), microprocessors, microcontrollers, digital signal processors (DSP), analog signal processors (ASP), or other similar hardware circuitry, software programming, or a combination of hardware and software.
The microprocessor (MPS) can be any microprocessor or microprocessor variant such as as microcontroller (MCU), a digital signal processor (DSP), a graphics processing unit (GPU), a system on chip (SoC), a finite state machine (FSM), configurable logic devices PLD, FPGA, etc.), application specific integrated circuit (ASIC), or any other circuitry accessing memory devices (EEPROM, NVRAM, etc), that provides changes from one state to another in response to a change of state. In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the MPU will store a sequence of settings to initialize and configure the CDR. There are integrated CDRs which initialize and configure to a specific default operation. The microprocessor (MPU) with discreet and integrated CDRs will also provide settings to align the CDR to a list of communication signal bit rates. This list represents the communication signal hit rates the CDR will interface. This list is based upon the implementation and application of the CDR. The list will represent the appropriate data for the CDR to align. Due to the variations of design architectures, methodologies, and approaches, each CDR will have a specific or proprietary data type and format and process to align.
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, Connection (CXN) is defined as any medium to interface other circuitry, devices, or equipment. A Connection (CXN) can be de-fined as printed circuit board (PCB) traces on a PCB assembly or metal interconnects within an integrated circuit to interface other circuitry to process the communication signal. These other circuitries can be an electrical-to-optical conversion integrated circuit, microprocessor, crosspoint switch, retimer, digital signal processors (DSP), field programmable gate-array (FPGA), application specific integrated circuits (ASIC), or other signal interface circuitry. Connection (CXN) can also be defined as a mechanical component to interconnect and interface a PCB circuitry assembly to process the communication signal.
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the embodiments 200a-200t4 as illustrated in
In the circuitry, system(s), method(s), equipment an for device of the present disclosure, the embodiments as illustrated in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the embodiments as illustrated in
Path 1 (Version 200a) input single-ended signal 300 connects to the input of CDR1202a.
Path 2 (Version 200a) output single-ended signal 302a connects to the output of CDR1702a.
Path 3 (Version 200a) input single-ended signal 304a connects to the input of CDR2204a.
Path 4 (Version 200a) output single-ended signal 306a connects to the output of CDR2204a.
Path 1 (Version 200b) input differential signal 300b connects to the input of CDR1202b.
Path 2 (Version 200b) output single-ended signal 302a connects to the output of CDR1202b.
Path 3 (Version 200b) input differential signal 304b connects to the input of CDR2204b.
Path 4 (Version 200b) output single-ended signal 306a connects to the output of CDR2204b.
Path 1 (Version 200c) input single-ended signal 300a connects to the input of CDR1202c.
Path 2 (Version 200c) output differential signal 302b connects to the output of CDR1202c.
Path 3 (Version 200c) input single-end signal 304a connects to the input of CDR2204c.
Path 4 (Version 200c) output differential signal 306b connects to the output of CDR2204c.
Path 1 (Version 200d) input differential signal 300b connects to the input of CDR1202d.
Path 2 (Version 200d) output differential signal 302b connects to the output of CDR1202d.
Path 3 (Version 200d) input differential signal 304b connects to the input of CDR2204d.
Path 4 (Version 200d) output differential signal 306b connects to the output of CDR2204d.
A microprocessor circuitry (MPU) 206 connects to CDR1202a-202d and CDR2204a-204d through connections 400 and 402, respectively. The MPU 206 communicates a series of commands to CDR1202a-202d and CDR2204a-204d for initialization and provisioning for signal bit rate settings, signal output patterns and control, and to determine CDR and signal performance and status. The MPL1206 will determine performance and status by reading, the CDR1202a-202d and CDR2204a-204d software registers or by sensing a voltage level from the CDR1202a-202d and CDR2204a-204d circuitry pin connectors. MPU 206 may also provision CDR1202a-202d and CDR2204a-204d to output a signal with a specific pattern or disable the output to minimize signal noise or corrupted data to affect other circuitry, systems, and the network during the version 200a-200d initialization or operation. When a communication signal. 300a-300b is present on Path 1 of connection CXN1, CDR1202a-202d will attempt to align and lock to the communication signal 300a-300b bit rate. If CDR1202a-202d does not lock to the communication signal 300a-300b bit rate, CDR1202a-202d will indicated a non-locked status to the microprocessor (MPU) 206 through interface 400. The MPU 206 will communicate to CDR1202a-202d non-locked status to supervisory circuitry through interface 404. The microprocessor (MPU) 206 will then provision the CDR1202a-202d with the next sequential bit rate setting from the signal bit rate list. The CDR1202a-202d will then attempt to align and lock with the new signal bit rate. If the CDR1202a-202d 202a-202d still does not align and lock to the new signal bit rate, the MPU 206 will repeat or cycle the process and interactions with CDR1202a-202d using the next sequential bit rate setting on the list. If the CDR1202a-202d locks to the communication signal 300a-300b bit rate, CDR1202a-202d will indicate a locked status to MPU 206 through interface 400. The CDR1202a-202d will re-clock and regenerate the communication signal 302a-302b on Path 2 of connection CXN2. The MPU 206 will process and store the CDR1202a-202d locked status and the communication signal bit rate setting. The MPU 206 will communicate the CDR1202a-202d locked status to supervisory circuitry through interface 404. The MPU 206 will then automatically provision CDR2204a-204d with the CDR1202a-202d locked communication signal bit rate settings and any applicable activation and/or initialization settings, CDR2204a-204d will align to the communication signal 304a-304b from Path 3 connection 2 (CXN2). CDR 204a-204d will then re-clock, re-generate, and transmit the communication signal 306a-306b to Path 4 connection 1 (CXN1).
The processes and interactions describing the communication signal bit rate auto-alignment of among CDR1202a-202d, CDR2204a-204d, and MPV 206 are further discussed and illustrated in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the second embodiment as illustrated in
Path 1 (Version 200e) input differential signal 308 connects to the input of RCV1208a. Receive circuitry RCV1208a outputs a signal-ended signal 300a to input of CDR1202a.
Path 2 (Version 200e) output single-ended signal 302E connects to the output of CDR1202a.
Path 3 (Version 200e) input differential signal 312 connects to the input of RCV2212a. Receive circuitry RCV2212a outputs a signal-ended signal 304a to the input of CDR2204a.
Path 4 (Version 200e) output single-ended signal 306a connects to the output of CDR2204a.
Path 1 (Version 200f) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV1208b outputs a differential signal 300b to the input of CDR1202b.
Path 2 (Version 200f) output single-ended signal 302a connects to the output of CDR1202b.
Path 3 (Version 200f) input differential signal 312 connects to the input of RCV2212b. Receive circuitry RCV2212b outputs a differential signal 304b to the input of CDR2204b.
Path 4 (Version 200f) output single-ended signal 306a connects to the output of CDR2204b.
Path 1 (Version 200g) input differential signal 308 connects to the input of RCV1208a. Receive circuitry RCV1208a outputs a single-ended signal 300a to the input of CDR1202c.
Path 2. (Version 200g) output differential signal 302b connects to the output of CDR1202c.
Path 3 (Version 200g) input differential signal 312 connects to the input of RCV2212a. Receive circuitry RCV2212a outputs a single-ended signal 304a to the input of CDR2204c.
Path 4 (Version 200g) output differential signal 306b connects to the output of CDR2204c.
Path 1 (Version 200h) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV1208b outputs a differential signal 300b to the input of CDR1202d.
Path 2 (Version 200h) output differential signal 302b connects to the output of CDR1202d.
Path 3 (Version 200h) input differential signal 312 connects to the input of RCV2212b. Receive circuitry RCV2212b outputs a differential signal 304b to the input of CDR2204d.
Path 4 (Version 200h) output differential signal 306b connects to the output of CDR2204d.
A microprocessor circuitry (MPU) 206 connects to CDR1202a-202d, CDR2204a-204d, RCV1208a-208b, and RCV2212a-212b through connections 400, 402, 406, and 410 respectively. MPU 206 communicates a series of commands to CDR1202a-202d and CDR2204a-204d for initialization and provisioning communication bit rate settings, signal output patterns and control, and to determine CDRs performance and status. The MPU 206 will determine performance and status by reading the CDR1202a-202d and CDR2204a-204d software registers or by sensing a voltage level from the CDR1202a-209d and CDR2204a-204d circuitry pin connectors. MPU 206 may also provision CDR1202a-202d and CDR2204a-204d to output a signal with a specific pattern or disable the output to minimize signal noise or corrupted data to affect other circuitry, systems, and the network during the version initialization or operation. Depending upon the application, MPU 206 can communicate initialization and provisioning settings to RCV1208a-208b and RCV2212a-212b. The MPU 206 may provision RCV1208a-208b and/or RCV2212a-212b with different amplification and equalization settings. If RCV 208a-208b and RCV2212a-212b is a buffer or an amplifier with a fixed gain setting, connection 406 and 410 to MPU 206 may not be required. Furthermore, the MPU 206 may request and received performance and operational status of RCV1208a-208b and RCV2212a-212b. When a communication signal 308 is present on Path 1 of connection CAN1, RCV1208a-208b will buffer or amplify the communication signal 300a-300b. RCV1208a-208b may also equalize the communication signal 308 to remove any signal impairments and/or convert the differential communication signal to a non-differential communication signal to interface CDR1202a-202d. CDR1202a-202d will attempt to align and lock to the communication signal bit rate. If CDR1202a-202d does not align and lock to the communication signal 300a-300b bit rate, CDR1202a-202d will indicated a non-locked status to the microprocessor (MPU) 206 through connection 400. The MPU 206 will communicate the CDR1202a-202d non-locked status to supervisory circuitry through connection 404. The microprocessor (MPU) 206 will then provision the CDR1202a-202d with the next sequential bit rate setting from the communication signal bit rate list. The CDR1202a-202d will attempt again to align and lock to the communication signal bit rate from connection 300a-300b. If the CDR1202a-202d still does not align and lock to the communication signal bit rate, the process and interactions between the CDR1202a-202d and the MPU 206 will repeat using the next sequential bit rate setting. If the CDR1202a-202d aligns and locks to the communication signal bit rate, CDR1202a-202d will indicate a locked status to MPU 206 through connection 400. The CDR1202a-202d will re-clock and regenerate the communication signal 307a-302b on Path 2 of connection CXN2. The MPU 206 will process and store the CDR1202a-202d locked status and the communication signal bit rate setting. The MPU 206 will communicate the CDR1202a-202d locked status to supervisory circuitry through connection 404. The MPU 206 will then automatically provision CDR2204a-204d with the CDR1202a-202d locked communication signal bit rate settings and any applicable activation and/or initialization settings. CDR2204a-204d will align to the communication signal 304a-304b from Path 3 connection 2 (CXN2). CDR2204a-204d will then re-clock, re-generate, and transmit the communication signal 306a-306b to Path 4 connection 1 (CXN1).
The processes and interactions describing the communication signal bit rate auto-alignment of among CDR1202a-202d, CDR2204a-204d, and MPU 206 are further discussed and illustrated in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the third embodiment as illustrated in
Path 1 (Version 200i) input differential signal 308 connects to the input of RCV1208a. Receive circuitry RCV1208a outputs a signal-ended signal 300a to the input CDR1202a.
Path 2 (Version 200i) output single-ended signal 302a connects to the output of CDR1202a.
Path 3 (Version 200i) input single-ended signal 304a connects to the input of CDR2204a. Clock data recovery circuitry CDR2204a outputs a single-ended signal 306a to the input of XMT2214a.
Path 4 (Version 200i) output differential signal 314 connects to the output of XMT2714a.
Path 1 (Version 200j) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV 208b outputs a differential signal 300b to the input CDR1202b.
Path 2 (Version 200j) output single-ended signal 302a connects to the output of CDR1702b.
Path 3 (Version 200j) input single-ended signal 304a connects to the input of CDR2204b. Clock data recovery circuitry CDR2204b outputs a differential signal 306b to the input of XMT2214b.
Path 4 (Version 200j) output differential signal 314 connects to the output of XMT2214b.
Path 1 (Version 200k) input differential signal 308 connects to the input of RCV1208a. Receive circuitry RCV1208a outputs a signal-ended signal 300a to the input CDR1202c.
Path 2 (Version 200k) output differential signal 302b connects to the output of CDR1202c.
Path 3 (Version 200k) input differential signal 304b connects to the input of CDR2204c. Clock data recovery circuitry CDR2204c outputs a single-ended signal 306a to the input of XMT2214a.
Path 4 (Version 200k) output differential signal 314 connects to the output of XMT2214a.
Path 1 (Version 200l) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV1208b outputs a differential signal 300b to the input CDR1202d.
Path 2 (Version 200l) output differential signal 302b connects to the output of CDR1202d.
Path 3 (Version 200l) input differential signal 304b connects to the input of CDR2204d. Clock data recovery circuitry CDR2204d outputs a differential signal 306b to the input of XMT2214b.
Path 4 (Version 200l) output differential signal 314 connects to the output of XMT2214b.
A microprocessor circuitry (MPU) 206 connects to CDR1202a-202d , CDR2204a-204d , RCV1208a-208b and XMT2214a-214b through connections 400, 402, 406, and 412 respectively. MPU 206 communicates a series of commands to CDR1202a-202d and CDR2204a-204d for initialization and provisioning communication bit rate settings, signal output patterns and control, and to determine CDRs performance and status. The MPU 206 will determine performance and status by reading the CDR1202a-202d and CDR2204a-202d software registers or by sensing a voltage level from the CDR1202a-202d and CDR2204a-204d circuitry pin connectors. MPU 206 may also provision CDR1202a-202d and CDR2204a-204d to output a signal with a specific pattern or disable the output to minimize signal noise or corrupted data to affect other circuitry, systems, and the network during the version initialization or operation. Depending upon the application, MPU 206 can communicate initialization and provisioning settings to RCV1208a-208b. The MPU 206 may provision RCV1208a-208b with different amplification and equalization settings. If RCV1208a-208b is a buffer or area amplifier with a fixed gain setting, connection 406 to MPU 206 may not be required. Furthermore, the MPU 206 may request and received performance and operational status of RCV1208a-208b. Depending upon the application, MPL1206 can communicate initialization and provisioning settings to XMT2214a-214b. The MPU 206 may provision XMT2214a-214b with amplification, modulation, reformatting, or pre-equalization setting to interface the differential signal 314 for interfacing Path 4 connections CXN1. When a communication signal 308 is present on Path 1 of connection CXN1, RCV1208a-208b will buffer or amplify the communication signal. RCV1208a-208b may also equalize the communication signal 308 to remove any signal impairments and/or convert the differential communication signal to a non-differential communication signal to interface CDR1202a-202d. CDR1202a-202d will attempt to align and lock to the communication signal bit rate. If CDR1202a-202d does not align and lock to the communication signal 300a-300b bit rate. CDR1202a-202d will indicated a non-locked status to the microprocessor (MPU) 206 through connection 400. The MPU 206 will communicate the CDR1202a-202d non-locked status to supervisory circuitry through connection 404. The microprocessor (MPU) 206 will then provision the CDR1202a-202d with the next sequential bit rate setting from the communication signal hit rate list. The CDR1202a-202d will attempt again to align and lock to the communication signal bit rate from connection 300a-300b. If the CDR1202a-202d does not align and lock to the communication signal bit rate, the process and interactions between the CDR1202a-202d and the MPU 206 will repeat using the next sequential bit rate setting. If the CDR1202a-202d aligns and locks to the communication signal bit rate. CDR1202a-202d will indicate a locked status for MPU 206 through connection 400. The CDR1202a-202d will re-clock and regenerate the communication signal 302a-302b on Path 2 of connection CXN2. The CDR1202a-202d will also output a message to MPU 206 that CDR1202a-202d is locked. The MP 206 will process and store the CDR1202a-202d locked status and the communication signal bit rate setting. The MPU 206 will communicate the CDR1202a-202d locked status to supervisory circuitry through connection 404. The MPU 206 will then automatically provision CDR2204a-204d with the CDR1202a-202d locked communication signal bit rate settings and any applicable activation or initialization settings. CDR2204a-204d will then align and lock to the communication signal bit rate from connection 304a-304b. CDR2204a-204d will re-clock and regenerate the locked communication signal 306a-306b to XMT2214a-214b. XMT2214a-214b may perform signal amplification, buffering, format conversion, or conditioning on Path 4 of connection CXN1.
The processes and interactions describing the communication signal bit rate auto-alignment of among CDR1202a-202d, CDR2204a-204d, and MPU 206 are further discussed and illustrated in
In the circuitry, system(s), method(s), equipment ardor device(s) of the present disclosure, the fourth embodiment as illustrated in
Path 1 (Version 200m) input differential signal 308 connects to the input of RCV1208a. Receive circuitry RCV1208a outputs a signal-ended signal 300a to the input CDR1202a.
Path 2 (Version 200m) output differential signal 310 connects to the output of XMT1210a. Transmit circuitry XMT1 input single-ended signal 302a connects to the output of CDR1202a.
Path 3 (Version 200m) input differential signal 312 connects to the input of RCV2212a. Receive circuitry RCV2212a outputs a single-ended signal 304a to the input of CDR2204a.
Path 4 (Version 200m) output differential signal 314 connects to the output of XMT2214a. Transmit circuitry 214a input single-ended signal 306a connects to the output of CDR2204a.
Path 1 (Version 200n) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV1208b outputs a differential signal 300b to the input CDR1202b.
Path 2 (Version 200n) output differential signal 310 connects to the output of XMT1210a. Transmit circuitry XMT1210a input single-ended signal 302a connects to the output of CDR1202b.
Path 3 (Version 200n) input differential signal 312 connects to the input of RCV2212b. Receive circuitry RCV2212b outputs a differential signal 304b to the input of CDR2204b.
Path 4 (Version 200m) output differential signal 314 connects to the output of XMT2214a. Transmit circuitry 214a input single-ended signal 306a connects to the output of CDR2204b.
Path 1 (Version 200o) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV 208b outputs a single-ended signal 300a to the input. CDR1202c.
Path 2 (Version 200o) output differential signal 310 connects to the output of XMT1210b. Transmit circuitry XMT1210b input differential signal 302b connects to the output of CDR1202c.
Path 3 (Version 200o) input differential signal 312 connects to the input of RCV2212b. Receive circuitry RCV2212b outputs a differential signal 304b to the input of CDR2204c.
Path 4 (Version 200o) output differential signal 314 connects to the output of XMT2214b. Transmit circuitry XMT2214b input single-ended signal 306a connects to the output of CDR2204c.
Path 1 (Version 200p) input differential signal 308 connects to the input of RCV1208b. Receive circuitry RCV1208b outputs a differential signal 300b to the input CDR1202d.
Path 2 (Version 200p) output differential signal 310 connects to the output of XMT1210b. Transmit circuitry XMT1210b input differential signal 302b connects to the output of CDR1202d.
Path 3 (Version 200p) input differential signal 312 connects to the input of RCV2212b. Receive circuitry RCV2212b outputs a differential signal 304b to the input of CDR2204d.
Path 4 (Version 200p) output differential signal 314 connects to the output of XMT2214b. Transmit circuitry XMT2214b input differential signal 306b connects to the output of CDR2204d.
A microprocessor circuitry (MPU) 206 connects to CDR1202a-202d, CDR2204a-204d, RCV1208a-208b, RCV2212a-212b, XMT1210a-210d , and XMT2214a-214b through connections 400, 402, 406, 410, 408, and 412 respectively. MPU 206 interfaces CDR1202a-202d through connection 400 and CDR2204a-204d through connection 402. MPU 206 communicates a series of commands to CDR1202a-202d and CDR2204a-204d for and provisioning communication bit rate settings, signal output patterns and control, and to determine CDRs performance and status. The MPU 206 will determine performance and status by reading the CDR1202a-202d and CDR2204a-204d software registers or by sensing a voltage level from the CDR1202a-202d and CDR2204a-204d circuitry pin connectors. MPU 206 may also provision CDR1202a-202d and CDR2204a-204d to output a signal with a specific pattern or disable the output to minimize signal noise or corrupted, data to affect other circuitry, systems, and the network during the version initialization or operation, Depending upon the application, MPU 206 can communicate initialization and provisioning settings to RCV1208a-208b and RCV2212a-212b. The MPU 206 may provision RCV1208a-208b and/or RCV2212a-212b with different amplification and equalization settings. If RCV 208a-208b and RCV2212a-212b is a buffer or an amplifier with a fixed gain setting, connection 406 and 410 to MPU 206 may not be required. Furthermore, the MPU 206 may request and received performance and operational status of RCV1208a-208b and RCV2212a-212b. Depending upon the application, MPU 206 can communicate initialization and provisioning settings to XMT1210a-210b and XMT2214a-214b. The MPU 206 may provision XMT1210a-210b and/or XMT2214a-214b with amplification, modulation, reformatting, or pre-equalization setting to interface the differential signal connections of 310 and 314.
When a communication signal 308 is present on Path 1 of connection CXN1, RCV1208a-208b will buffer or amplify the communication signal. RCV1208a-208b may also equalize the communication signal 308 to remove any signal impairments and/or convert the differential communication signal to a non-differential communication signal to interface CDR1202a-202d. CDR1202a-202d will attempt to align and lock to the communication signal bit rate. If CDR1202a-202d does not align and lock to the communication signal bit rate from connection 300a-300b. CDR1202a-202d will indicate a non-locked status to the microprocessor (MPU) 206 through connection 400. The MPU 206 will communicate the CDR1202a-202d non-locked status to supervisory circuitry through connection 404. The microprocessor (MPU) 206 will then provision the CDR1202a-202d with the next sequential bit rate setting from the communication signal bit rate list. The CDR1202a-202d will attempt again to align and lock to the communication signal bit rate from connection 300a-300b. If the CDR1202a-202d does not align and lock to the communication signal bit rate, the process and interactions between the CDR1202a-202d and the MPU 206 will repeat using the next sequential hit rate setting. If the CDR1202a-202d aligns and locks to the communication signal bit rate, CDR1202a-202d will indicate a locked status for MPU 206 through connection 400. The CDR1202a-202d will re-clock and regenerate the communication signal to interface XMT1210a-210b through connection 302a-302b. XMT1210a-210b may perform signal amplification, buffering, format conversion, or conditioning on Path 2 of connection CXN2. The CDR1202a-202d will also output a message to MPU 206 that CDR1202a-202d is locked. The MPU 206 will process and store the CDR1202a-202d locked status and the communication signal bit rate setting. The MPU 206 will communicate the CDR1202a-202d locked status to supervisory circuitry through connection 404. The MPU 206 will then automatically provision CDR2204a-204d with the CDR1202a-202d locked communication signal bit rate settings and any applicable activation or initialization settings. RCV2212a-212b will equalize the communication signal 312 to remove any signal impairments from connection 312. RCV2212a will then convert the differential communication signal 312 to a non-differential communication signal 304a to CDR2204a, while RCV2212b will then convert the differential communication signal 312 to a differential communication signal 304b to CDR2204a. CDR2204a-204b will then align and lock to the communication signal hit rate from connection 304a-304b, CDR2204a-204d will re-clock and regenerate the locked communication signal 306a-306b to XMT2214a-214b, XMT2214a-214b may perform signal amplification, buffering, format conversion, or conditioning on Path 4 of connection CXN1.
The processes and interactions describing the communication signal bit rate auto-alignment of among CDR1202a-202d, CDR2204a-204d, and MPU 206 are further discussed and illustrated in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the fifth embodiment as illustrated in
A port (PORT) is defined as a communication signal and management interface to any component, module, device or equipment with tunable wavelength functionality, clock and data recovery circuitry, or both. A port (PORT) is at least one management interface addressing at least one communication signal interface. Component can be an optical tunable laser, fixed wavelength lasers, tunable ROSA, tunable TOSA, tunable wavelength filter, optical modulator, wavelength locker, waveguides, phase/symbol detector, CDR, tunable antenna, tunable bandpass filters, or wireless MEM. Modules can be an on-board or co-packaged packaged optics such as modules defined by various standards such as the COBO 8-Lane and 16-Lane On-Board Optics Specification, Release 1.1, Dec. 9, 2018, 3.2 Tb/s Copackaged Optics Optical Module, Version 1.0, Feb. 5, 2021, Co-Packaging Framework Document, OIF-Co-Packaging-FD-01.0, Feb. 3, 2022, and/or manufacturers proprietary specifications involving tunable wavelength and CDR functionality. Communication equipment can be communication convergence systems, communication transport systems, data center equipment, communication servers, communication testing and monitoring equipment, passive optical network equipment (OLT and ONU), edge access system equipment, routers, switches, media converters, panels, splitters, and other communication equipment used within the communication networks.
Device is any pluggable device, such as small form-factor pluggable (SFP) variant devices. These SFP variant devices interface communication equipment and networks through wired cables, coax cables, fiber optic cables, or wireless signals. SFP variant devices are defined as SFP, SFP+, SFP28, SFP56, SFP-DD, SFP-DD112, QSFP, QSFP+, QSFP28, QSFP-DD, QSFP-DD800, OSFP, OSFP800, and other future variants. These SFP variant devices can be a single or multiple channel or lane operation for each direction. An SFP variant device with wavelength tuning functions is used to align or tune to the receiving communication signal wavelength and transmit the same or different received communication signal wavelength. This type of SFP variant device with wavelength tuning functionality is typically referred as a tunable SFP+, tunable QSFP+, and future variants such as a tunable SFP-DD, QSFP-DD, OSFP, OSFP-DD, and other SFP variants. An SFP variant device with CDR functions can be used to align or tune to the receiving, port (PORT), comprised of an SFP cage (housing) and device connector, when SFP variant devices are used. The SFP cage and device connector must be compatible with the SFP variant device operation.
Management interface is defined as any synchronous, asynchronous, parallel, low-level control leads, or proprietary management interface. Examples of manage interface are I2C, SPI, PCIe, Ethernet, USB, Fiber Channel, RS232, RS485, CAN, and control leads. The microprocessor circuitry (MPU) will communicate with the component, device, module, or equipment management interface for information, status, and provisioning of the component, device, module, or equipment and the communication signal(s).
Embodiment 200q1 of the fifth embodiment version 1 of the present disclosure is comprised of clock data recovery circuitry CDR1202a and CDR2204a, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input single-ended signal 300a and a Path 4 representing an output single-ended signal 306a. CXN2 comprises a Path 2 representing an output single-ended signal 302a and a Path 3 representing an input single-ended signal 304a. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200q2 of the fifth embodiment, version 2 of the present disclosure is comprised of clock data recovery circuitry CDR1202b and CDR2204b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 300b and a Path 4 representing an output single-ended signal 306a. CXN2 comprises a Path 2 representing, an output single-ended signal 302a and a Path 3 representing an input differential signal 304b. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200q3 of the fifth embodiment, version 3 of the present disclosure is comprised of clock data recovery circuitry CDR1202c and CDR2204c, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input single-ended signal 300a and a Path 4 representing an output differential signal 306b. CXN2 comprises a Path 2 representing an output differential signal 302b and a Path 3 representing an input single ended signal 304a. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200q4 of the fifth embodiment, version 4 of the present disclosure is comprised of clock data recovery circuitry CDR1202d and CDR2204d, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 300b and a Path 4 representing an output differential signal 306b. CXN2 comprises a Path 2 representing an output differential signal 302b and a Path 3 representing an input differential signal 304b. Path 1-Path 4 descriptions are illustrated and described in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the fifth embodiment as illustrated in
Embodiment 200r1 of the fifth embodiment, version 1 of the present disclosure is comprised of clock data recovery circuitry CDR1202a and CDR2204a, receive circuitry RCV1208a and RCV2212a, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208a, which outputs a single-ended signal 300a going to the input of CDR1202a, and a Path 4 representing an output single-ended signal 306a. CXN2 comprises a Path 2 representing an output single-ended signal 302a and a Path 3 representing an input differential signal 312 going to the input of RCV2212a, which outputs a single-ended signal 304a going to the input of CDR2204a. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200r2 of the fifth embodiment, version 2 of the present disclosure is comprised of clock data recovery circuitry CDR1202b and CDR2204b, receive circuitry RCV1208b and RCV2212b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208b, which outputs a differential signal 300b going to the input of CDR1202b, and a Path 4 representing an output single-ended signal 306a. CXN2 comprises a Path 2 representing an output single-ended signal 302a and a Path 3 representing an input differential signal 312 going to the input of RCV2212b, which outputs a differential signal 304b going to the input of CDR2204b. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200r3 of the fifth embodiment, eversion 3 of the present disclosure is comprised of clock data recovery circuitry CDR1202c and CDR2204c, receive circuitry RCV1208a and RCV2212a, a microprocessor circuitry MPU 206, and ports PORT 216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208a, which outputs a single-ended signal 300a going to the input of CDR1202c, and a Path 4 representing an output differential signal 306b. CXN2 comprises a Path 2 representing an output differential signal 302b and a Path 3 representing an input differential signal 312 going to the input of RCV2212a, which outputs a single-ended signal 304a going to the input of CDR2204c. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200r4 of the fifth embodiment, version 4 of the present disclosure is comprised of clock data recovery circuitry CDR1202d and CDR2204d, receive circuitry RCV1208b and RCV2212b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208b, which outputs a differential signal 300b going to the input of CDR1202d, and a Path 4 representing an output differential signal 306b. CXN2 comprises a Path 2 representing an output differential signal 302b and a Path 3 representing an input differential signal 312 going to the input of RCV2212b, which outputs a differential signal 304b going to the input of CDR2204d. Path 1-Path 4 descriptions are illustrated and described in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the sixth embodiment as illustrated in
Embodiment 200s1 of the sixth embodiment version 1 of the present disclosure is comprised of clock data recovery circuitry CDR1202a and CDR2204a, a receive circuitry RCV1208a, a transmit circuitry XMT2214a, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208a, which outputs a single-ended signal 300a going to the input of CDR1202a, and a Path 4 representing an output differential signal 314 from the output of XMT2214a, which receives a single-ended signal 306a from the output of CDR2204a, CXN2 comprises a Path 2 representing an output single-ended signal 302a and a Path 3 representing an input single-ended signal 304a. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200s2 of the sixth embodiment, version 2 of the present disclosure is comprised of clock data recovery circuitry CDR1202b and CDR2204b, a receive circuitry RCV1208b, a transmit circuitry XMT2214b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208a, which outputs a differential signal 300b going to the input of CDR1202a, and a Path 4 representing an output differential signal 314 from the output of XMT2214b, which receives a differential signal 306b from the output of CDR2204b. CXN2 comprises a Path 2 representing an output single-ended signal 302a and a Path 3 representing an input single-ended signal 304a. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200s3 of the sixth embodiment, version 3 of the present disclosure is comprised of clock data recovery circuitry CDR1202c and CDR2204c, a receive circuitry RCV1208a, a transmit circuitry XMT2214a, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208a, which outputs a single-ended signal 300a going to the input of CDR1202c, and a Path 4 representing an output differential signal 314 from the output of XMT2214a, which receives a single-ended signal 306a from the, output of CDR2204c. CXN2 comprises a Path 2 representing an output differential 302b and a Path 3 representing an input differential signal 304b. Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200s4 of the sixth embodiment, version 4 of the present disclosure is comprised of clock data recovery circuitry CDR1202d and CDR2204d, a receive circuitry RCV1208b, a transmit circuitry XMT2214b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208b, which outputs a differential signal 300b going to the input of CDR1202d, and a Path 4 representing an output differential signal 314 from the output of XMT2214b, which receives a differential signal 306b from the output of CDR2204d. CXN2 comprises a Path 2 representing an output differential signal 302b and a Path 3 representing an input differential signal 304b. Path 1-Path 4 descriptions are illustrated and described in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the seventh embodiment as illustrated in
Embodiment 200t1 of the seventh embodiment, version 1 of the present disclosure is comprised of clock data recovery circuitry CDR1202a and CDR2204a, receiver circuitry RCV1208a and 212a, and transmit circuitry XMT2210a and XMT2214a, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208a, which outputs a single-ended signal 300a going to the input of CDR1202a, and a Path 4 representing an output differential signal 314 from the output of XMT2214a, which receives a single-ended signal 306a from the output of CDR2204a. CXN2 comprises a Path 2 representing an output differential signal 310 from the output of XMT1210a, which receives a single-ended signal 302a from the output of CDR1202a, and a Path 3 representing, an input differential signal 312 going to the input of RCV2212a, which outputs a single-ended signal 304a going to the input of CDR2204a. Path Path 4 descriptions are illustrated and described in
Embodiment 200t2 of the seventh embodiment, version of the present disclosure is comprised of clock data recovery circuitry CDR1202b and CDR2204b, receiver circuitry RCV1208b and 212b, and transmit circuitry XMT1210a and XMT2214a, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218. CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208b, which outputs a differential signal 300b going to the input of CDR1202b, and a Path 4 representing an output differential signal 314 from the output of XMT2214a, which receives a single-ended signal 306a from the output of CDR2204b. CXN2 comprises a Path 2 representing an output differential signal 310 from the output of XMT1210a, which receives a single-ended signal 302a from the output of CDR1202b, and a Path 3 representing an input differential signal 312 going to the input of RCV2212b, which outputs a differential signal 304b going to the input of CDR2204b, Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200t3 of the seventh embodiment, version 3 of the present disclosure is comprised of clock data recovery circuitry CDR1202c and CDR2204c, receiver circuitry RCV1208b and 212b, and transmit circuitry XMT1210b and XMT2214b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218, CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208b, which outputs a single-ended signal 300a going to the input of CDR1202c, and a Path 4 representing an output differential signal 314 from the output of XMT2214b, which receives a single-ended signal 306a from the output of CDR2304c. CXN2 comprises a Path 2 representing an output differential signal 310 from the output of XMT1210b, which receives a differential signal 302b from the output of CDR1202c, and a Path 3 representing an input differential signal 312 going to the input of RCV2212b, which outputs a differential signal 304b going to the input of CDR2204c, Path 1-Path 4 descriptions are illustrated and described in
Embodiment 200t4 of the seventh embodiment, version 4 of the present disclosure is comprised of clock data recovery, circuitry CDR1202d and CDR2204d, receiver circuitry RCV1208b and 212b, and transmit circuitry XMT1210b and XMT2214b, a microprocessor circuitry MPU 206, and ports PORT1216 and PORT2218, CXN1 comprises a Path 1 representing an input differential signal 308 going to the input of RCV1208b, which outputs a differential signal 300b going to the input of RCV1202d, and a Path 4 representing an output differential signal 314 from the output of XMT2214b, which receives a differential signal 306b from the output of CDR2204d. CXN2 comprises a Path 2 representing an output differential signal 310 from the output of XMT1210b, which receives a differential signal 302b from the output of CDR1202d, and a Path 3 representing an input differential signal 312 going to the input of RCV2212b, which outputs a differential signal 304b going to the input of CDR2204d, Path 1-Path 4 descriptions are illustrated and described in
In the circuitry, system(s), method(s), equipment and/or device(s) of the present disclosure, the embodiments 200q1-200q4, 200r1-200r4, 200s1-200s4, and 200t1-200t4 can convert the communication signal wavelength from connection CXN1 to a different wavelength on connection CXN2 by means of communicating wavelength provisioning to PORT1216 and/or PORT2218 by means of the MPU 206 provisioning a change in transmit wavelength to a component, module, device, or equipment with tunable transmit wavelength functionality. A component with an optical modulator, a module, device, or equipment with a tunable transmitter optical subassembly TOSA with the capability to change wavelength per grid spacings or channels. The following standards or agreements provide information and details on transmit and receiving wavelength tuning ITU-T G.694.1 4, 02/2012, Spectral Grids for WDM Applications: DWDM Frequency Grid, SFF-8477, Rev 1.4, Dec. 4, 2009, Specification for Tunable XFP for ITU Frequency Grid Applications, SFF-8690, Rev 1.4. Jan. 23, 2013, Tunable SFP+ Memory Map for ITU Frequencies, Rev 1.4, SFF-TA-1004, Rev 0.0.10 Jan. 23, 2018, Specification for Tunable QSFP+/QSFP28 Memory Map for ITU Frequencies, SFF-8024, Rev 4.9, May 24, 2021, Specification for SFF Module Management Reference Code Tables, SFP-DD MIS Rev 2.0, Sep. 25, 2020, SFP-DD MIS Management Interface Specification for SFP Double Density 2X Pluggable Transceiver, OIF-ITLA-MSA-01.3, Jul. 13, 2015, Integrable Tunable Laser Assembly Multi Source Agreement, OIF-MicroITLA-01.1, Jul. 13, 2015, Micro Integrable Tunable Laser Assembly Implementation Agreement, OIF-TLMSA-01.0 Multi-Source Agreement for CW Tunable Lasers, OIF-CMIS-05.2, Revision 5.2, Apr. 27, 2022, Common Management Interface Specification (CMIS). QSFP-DD Common Management Interface Specification for 8X/16X Pluggable Transceivers, Rev 3.0 Aug. 17, 2018.
Wavelength division multiplexing (WDM) is a technology used on optical communications to multiplex a number of different wavelength signals onto a single optical fiber cable or strand. WDM is a technology to increase the communication signal transmission bandwidth. There are many different variants, such as coarse wavelength division multiplexing (CWDM), dense wavelength division multiplexing (DWDM), and others. Dense Wavelength Division Multiplexing (DWDM) further increases the communication signal transmission bandwidth by multiplexing a greater number of wavelength signals using different grid spacings 0.4/0.8/1.6 nm (50/100/200 GHz grid), which enable DWDM to multiplex 40, 80, and 160 wavelength channels over a single optical fiber cable. ITU-T G.694.1 4, 02/2012, Spectral Grids for WDM Applications: DWDM Frequency Grid is an international standard on DWDM technologies.
The communication service list is determined at step 502 by the equipment design, end-user application, service provider's network, or a combination thereof. The communication service list can be comprised of communication bits rates, wavelengths, grid spacings, length channels, frequency, and bands. The communication service list can also be composed of vendor information, communication services, technology, service application and many other identifications or classifications from a component, module, device or equipment. The communication service lists are used by the CDR and/or PORTs to automatically align or tune to the communication signal bit rate, wavelength, or both wavelength and bit rate to re-clock or re-time the communication signal. Once the communication service list is established at step 502, the list may require prioritization as determined at step 504. Prioritization of the list may be required if the versions 200a-200p alignment and lock timing must be kept at a minimum. Prioritization of the list will also minimize installation, maintenance, or repair times. Minimizing the alignment or acquisition timing is critical to ensure the overall communication service latency. For example, 5G wireless service networks requires latency of 1 millisecond to ensure the operation of real-time applications. The Service Providers must ensure their 5G wireless service network equipment and infrastructure will meet the 5G latency requirement. If prioritization of the list is required, the flow chart proceeds to step 506 for the update arrangement of the list in the order of communication service application utilization, future application, and usage probability. In this example, the communication service list is comprised of communication service signal bit rates, which represent the communication services, set forth in
If the communication service does have an asymmetric line rate, the MPU 206 provisions the CDR2204a-204d with the asymmetric communication signal bit rate setting, step 544 from the communication service list. At step 546, if CDR2204a-204d does not align and lock, to the signal, CDR2204a-204d will provide non-lock indication status to MPU 206 through connection 402, step 552. If CDR2204a-204d aligns and locks to the communication signal bit rate, CDR2204a-204d will re-clock and regenerate the signal, step 548. CDR2204a-204d wilt provide lock indication status to MPU 206 through connection 402 step 550.
The MPU 206 will then analyze the communication service list or information from the component, device, module, or equipment, step 576, to determine at step 578 if the communication service is a wave-division multiplexing technology. If the communication service is a not a wave-division multiplexing technology and the component, module, device, or equipment has clock data and recovery circuitry (CDR-P1) stele 596, the MPU 206 will provision the CDR-P1 using flowchart 670 (
If the MPU 206 receives a signal, step 582 and then a non-lock wavelength status from the management interface of the component, module, device or equipment, at step 584, the MPU 206 will provide a non-lock wavelength indication status to MPU 206 through connection 400, step 592. The MPU 206 will then communicate to the component, module, device, or equipment to select and provision the next wave-division multiplexing wavelength settings, step 594. If the MPU 206 receives a lock wavelength status from the management interface communication with the component, module, device, or equipment, at step 584, then the MPU 206 will determine if the component, module, device, or equipment has clock data and recovery circuitry (CDR-P2), step 586. If the MPU206 determines that the component, module, device, or equipment does not have a CDR-P2, then transition to flowchart 530 illustrated, in
If the communication service does have an asymmetric line rate, the MPU 206 provisions the CDR-P2 with the asymmetric communication signal bit rate setting, step 684 from the communication service list or management interface communication information. At step 686, if CDR-P2 does not align and lock to the signal, CDR-P2 will provide non-lock indication status to MPU 206 through connection 402, step 692. If CDR-P2 aligns and locks to the communication signal bit rate, CDR-P2 will re-clock and regenerate the signal, step 688. CDR-P2 will provide lock indication status to MPU 206 through connection 402, step 690.
Application classification flowchart 600 and description classification flowchart 610 are illustrated in
Passive optical network (PON) is an application technology with many variants, where each variant is defined by IEEE, ITU, DOCSIS and other standards and implementation agreements. xPON variants are G-PON, GE-PON, XG-PON, XGS-PON, NG-PON2, GE-PON, 10G-EPON, 25GS-PON, and 50G-PONs. 5G/WiFi is a wireless application technology. XHAUL is an application technology for Service Providers transport or backbone network. XHAUL technology is comprised of legacy SONET, OTN, to, native Ethernet. FTTx is an optical networking application technology for fiber to the home FTTH, curb FTTC, premises FTTP, building FTTB, and others. FTTx is defined per ITU and IEEE standards. LAN is an application technology involving native Ethernet technologies.
In
SFF-8024, Rev 4.9, May 24, 2021, Specification for SFF Module Management Reference Code Tables
SFP-DD MIS Rev 2.0, Sep. 25, 2020, SFP-DD MIS Management Interface Specification for SFP Double Density 2X Pluggable Transceiver
OIF-ITLA-MSA-01.3, Jul. 13, 2015, Integrable Tunable Laser Assembly Multi Source Agreement
OIF-MicroITLA-01.1, Jul. 13, 2015, Micro Integrable Tunable Laser Assembly Implementation Agreement
OIF-TLMSA-01.0 Multi-Source Agreement for CW Tunable Lasers
OIF-CMIS-05.2, Revision 5.2, Apr. 27, 2022, Common Management interface Specification (CMIS)
OSFP-DD Common Management Interface Specification for 8X/16X Pluggable Transceivers, Rev 3.0, Aug. 17, 2018
SFF-8477, Re 1.4, Dec. 4, 2009, Specification for Tunable for XFP for ITU Frequency Grid Applications,
SFF-8690, Rev 1.4, Jan. 23, 2013, Tunable SFP+ Memory Map for ITU Frequencies, Rev 1.4
SFF-TA-1004, Rev 0.0.10 Jan. 23, 2018, Specification for Tunable QSFP+/QSFP28 Memory Map for ITU Frequencies
ITU-T-G.694.1 4, February 2012, Spectral Grids for WDM Applications: DWDM Frequency Grid
While the embodiment(s) disclosed herein are illustrative of the structure, function and operation of the exemplary method(s), circuitry, system(s), equipment and/or devices, it should be understood that various modifications may be made thereto with departing from the teachings herein. Further, the components of the method(s), circuitry, system(s), equipment an or devices disclosed herein can take any suitable form, including, any suitable hardware, software, circuitry or other components capable of adequately performing their respective intended functions, as may be known in the art. It should also be understood that all commercially available parts identified herein can be interchanged with other similar commercially available parts capable of providing the same function and results.
While the foregoing discussion presents the teachings in an exemplary fashion with respect to the disclosed method(s), circuitry, system(s), equipment, and/or devices relating to CDR circuitry for communication services, it will be apparent to those skilled in the art that the present disclosure may apply to other method(s), system(s), device(s), equipment and circuitry relating to other communication services. Further, while the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the method(s), system(s), device(s), equipment and circuitry may be applied in numerous applications, only, some of which have been described herein.
This application claims benefit to U.S. Provisional Application Ser. No. 63/298,697 entitled Circuitry, Devices(s), System(s), and Method(s) to Automatically Align and Lock CDR Circuitry, filed Jan. 12, 2023 the entire disclosure of which is herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63298697 | Jan 2022 | US |
