The present invention generally relates to circuits and methods for signal alignment and, in particular, circuits and methods for fast-settling signal alignment and DC offset removal.
In processing a received signal, the signal may have an unintended DC offset component that was not part of the original signal. This DC offset component may be introduced by a variety of sources as the signal is processed by the circuitry or in the stream. This DC offset component causes distortion and creates further undesirable effects to downstream circuitry. Thus, the removal of this undesirable DC offset component becomes an important issue in many applications. Furthermore, a received signal as is processed may also drift such that it no longer conforms to its original signal DC level. This signal will need to be re-aligned back to its original level or aligned at a desired level.
For example, zero-intermediate-frequency (Zero-IF) architectures have become very popular in radio frequency (RF) receivers due to its lower requirements on channel select filters and amplifiers. This type of architecture demands that the signal to be processed at low frequencies that are very close to zero. Hence, the removal of undesirable DC offset (at zero frequency) generated by mismatch, local oscillator (LO) leakage, or self-mixing without damaging low-frequency signal is a critical issue. Many transceivers use calibration techniques to remove DC offset. Although calibration techniques can effectively remove DC offset caused by mismatch and LO leakage, DC offset caused by self-mixing of a strong interferer and other operation-dependent sources can not be easily predicted and canceled. Calibration techniques also considerably increase circuit complexity and require close collaboration between analog and digital receiver chips.
Another method for DC offset removal is the insertion of a simple RC filter, as is illustrated in
In analyzing a simple RC filter as illustrated in
With the initial condition
Vout|
The solution is
Define cut-off frequency fT to be:
Assume that at time t=t0, the cut-off frequency is changed from fT to fT′ and the input signal can be decomposed into
If ωT=2πfT is assumed to be constant, it can be derived that
In Equation (6), it is evident that the output voltage consists of three components: the desired signal represented by the first term in the bracket; the decaying voltage caused by initial condition of output voltage; and the decaying term caused by the instantaneous input signal level at initial time. Equation (6) shows that frequency switching will introduce other DC offset voltages itself while removing DC offset changes from the input. This switching-induced DC offset is proportional to the input signal amplitude and depends on the signal level at the input and the output at the switching instant. One of the challenges here is to remove this DC offset voltage in a fast and efficient manner so that information can be extracted from the signal.
Innovative circuits and methods for fast-settling signal alignment and for removing of DC offset are therefore desired to overcome the shortcoming of prior art technologies.
It is therefore an object of the present invention to provide circuits and methods for fast-settling of a signal with a low cut-off frequency;
It is another object of the present invention to provide circuits and methods for alignment of a signal; and
It is yet another object of the present invention to provide circuits and methods for removing DC offsets from a signal.
Briefly, circuits and methods for fast settling signal alignment and for fast-settling DC offset removal are disclosed. In one preferred embodiment of the present invention, in processing an input signal, a circuit comprising a capacitor having one end connected to an input node for receiving the input signal and having a second end connected to an output node, a resistor having one end connected to said output node and a second end connected to a first bias voltage source, and an aligner having one end connected to the output node for aligning the peak level of the input signal. The aligner can be implemented in a variety of manners. In processing the input signal, the input signal is first clamped by the use of two bias voltages, then released and gradually brought down to the desired DC level. In another preferred embodiment of the present invention, in processing a differential signal pair, the signal alignment circuit of the present invention is connected in parallel to align the differential signal pair to the same DC level and in effect removes any DC offsets from the differential signal pair.
An advantage of the present invention is that it provides circuits and methods for fast-settling of a signal with a low cut-off frequency;
Another advantage of the present invention is that it provides circuits and methods for alignment of a signal; and
Yet another advantage of the present invention is that it provides circuits and methods for removing DC offsets from a signal.
a illustrates a generalized embodiment of the present invention of an AC coupling, signal alignment circuit;
b
1 illustrates a presently preferred embodiment of the present invention of an AC coupling, signal alignment circuit having a voltage dependent switch;
b
2 illustrates the resistance of SW2 as a function of Va;
c illustrates an alternative embodiment of the present invention;
d illustrates yet another alternative embodiment of the present invention;
a-3d illustrate the various states of the nodes of the circuit of
a illustrates a differential signal pair without DC offset; and
b illustrates a differential signal pair with DC offset.
When the circuit as shown in
In a presently preferred embodiment of the present invention, referring to
Here, referring to
The detailed operational states of the circuit illustrated in
In an alternative preferred embodiment of the present invention, in extending the circuits of
The circuits described herein can be implemented with NPN type BJTs with connected collector and base terminals as effective diodes. However, other type of devices with rectifying characteristics such as diodes, NMOS or PMOS devices with connected gate and drain nodes can also be used.
Other Alternative Implementations
Note that although the invention disclosed herein referred to a peak alignment method, it shall be understood that other alignment methods can be used as well including but not limited to average peak alignment, either average of positive peaks or average of both positive and negative peaks, etc. Furthermore, there are many other ways to utilize the method of signal alignment. For example, it is also possible to align the signal levels from the negative voltage levels. To do this, the output nodes need to be first discharged to a lower DC level, then pull-up diodes are used to align the negative peak. Note that the word “peak” is used in this disclosure to describe both the maximum signal level, which is typically a positive value (sometime referred to as positive peak), and the minimum signal value (sometime referred to as negative peak).
While the present invention has been described with reference to certain preferred embodiments, it is to be understood that the present invention is not to be limited to such specific embodiments. Rather, it is the inventor's contention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating and not only the preferred embodiment described herein but all those other and further alterations and modifications as would be apparent to those of ordinary skilled in the art.
Number | Name | Date | Kind |
---|---|---|---|
2892937 | Mirzwinski | Jun 1959 | A |
5579214 | Kitani et al. | Nov 1996 | A |
6154066 | Wen et al. | Nov 2000 | A |
6259300 | Yasuda et al. | Jul 2001 | B1 |
6304144 | Yamazaki et al. | Oct 2001 | B1 |
6590379 | Mercier | Jul 2003 | B2 |
Number | Date | Country | |
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20040217797 A1 | Nov 2004 | US |