Circuits and Methods for Generating a Common Voltage

Abstract

A circuit and a method for generating a common voltage, and a liquid crystal display (LCD) device including the circuit for generating a common voltage. Chip size and accumulated offset voltage of a liquid crystal display (LCD) may be reduced. The circuit for generating a common voltage includes a digital logic calculator, an input reference voltage generator, and a buffer unit. Prior to the generation of the common voltage, the digital logic calculator sets an input reference voltage corresponding to a target voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and features of exemplary embodiments of the present general inventive concept will become apparent and more readily appreciated from the following description of the exemplary embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a diagram illustrating a conventional display system;

FIG. 2 is a diagram illustrating a conventional common voltage generating circuit that is included in the power generator in FIG. 1;

FIG. 3 is a diagram illustrating a common voltage generating circuit according to an exemplary embodiment of the present invention;

FIG. 4 is a table showing examples of a first target voltage according to a bit value of a first control register;

FIG. 5 is a table showing examples of a target amplitude according to a bit value of an amplitude control register; and

FIG. 6 is a table showing examples of a second target voltage according to a bit value of a second control register.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

FIG. 3 is a diagram illustrating a common voltage generating circuit according to an exemplary embodiment of the present invention. The common voltage generating circuit in FIG. 3 may be applied to the system in FIG. 1.

FIG. 4 is a table showing examples of a first target voltage according to a bit value of a first control register.

FIG. 5 is a table showing examples of a target amplitude according to a bit value of an amplitude control register.

FIG. 6 is a table showing examples of a second target voltage according to a bit value of a second control register.

Referring to FIG. 3, a common voltage generating circuit 300 includes a digital logic calculator 310, an input reference voltage generator 320, and a buffer unit 330.

The digital logic calculator 310 outputs a value VCML[L:1] of a second control register that is set to a second target voltage of a common electrode voltage VCOM by receiving a value VCMA[m:1] of an amplitude control register that is set to a target amplitude of the common voltage. The digital logic calculator 310 calculates a value VCMA[m:1] of the amplitude control register and a value VCMH[n:1] of the first control register. As shown in FIG. 4 through FIG. 6, for example, when the first target voltage is Va, Va+Vs, Va+2Vs, . . . , Va+(2ⁿ−1)Vs according to a bit value of the first control register, and the target amplitude is Vb, Vb+Vs, Vb+2Vs, Vb+(2^m−1)Vs according to a bit value of the amplitude control register, the second target voltage is Va+(2ⁿ−1)Vs−Vb, Va+(2ⁿ−2)Vs−Vb, . . . , Va+(2^m−1)Vs−Vb according to a bit value of the second control register. When the value VCMA[m:1] of the amplitude control register is inputted, the digital logic calculator 310 stores the value. Then, the digital logic calculator 310 outputs a value VCML[L:1]. The value VCML[L:1] of a second control register is calculated according to the value VCMA[m:1] of the amplitude control register and the value VCMH[n:1] of the first control register.

The input reference voltage generator 320 generates a first input reference voltage VCMH_R and a second input reference voltage VCML_R by receiving the value VCMH[n.1] of the first control register that is set to the first target voltage of the common voltage, and the value VCML[L:1] of the second control register.

The buffer unit 330 outputs a high common electrode voltage VCOMH and a low common electrode voltage VCOML by receiving the first input reference voltage VCMH_R and the second input reference voltage VCML_R. The high common electrode voltage VCOMH and the low common electrode voltage VCOML are applied to a liquid crystal display panel by a common voltage driver 350.

The buffer unit 330 includes a first operational amplifier (op-amp) 332, a third op-amp 334, and a fourth op-amp 336. The first op-amp 332 outputs the high common electrode voltage VCOMH by receiving the first input reference voltage VCMH_R. The third op-amp 334 outputs the second input reference voltage VCML_R by receiving the second input reference voltage VCML_R. The third op-amp 334 and the fourth op-amp 336 are cascade-coupled with each other. A high buffer includes the first op-amp 332, and a lower buffer 338 includes the third op-amp 334 and the fourth op-amp 336. When an input offset voltage of the first op-amp 332 is Voff1, an input offset voltage of the third op-amp 334 is Voff3, and an input offset voltage of the fourth op-amp 336 is Voff4, the high common electrode voltage VCOMH at the node N1 may he determined by Equation 3:

VCOMH=(a+1)VCMH_—R−(a+1)Voff1   Equation 3

Comparing Equation 3 with Equation 1, because Voff2 does not appear in Equation 3, an output offset voltage may be improved by an amount of Voff2.

The low common electrode voltage VCOML at the node N2 may be determined by Equation 4:

VCOML=−b(VCML_—R)−(bVoff3+(b+1)Voff4)   Equation 4

Comparing Equation 4 with Equation 2, an output offset voltage may be improved by an amount of (a+1)Voff1+Voff2. The offset voltage of VCOMH is not accumulated. In addition, comparing the circuits in FIG. 2 and FIG. 3, the circuit in FIG. 3 does not require the buffer 224 for eliminating noise and the resistances bR2 and R2 for decreasing the current in FIG. 2. Thus, the size of the chip may be reduced.

In the conventional common voltage generating circuit, because the low common electrode voltage VCOML is outputted through an analog calculator as in the op-amp 228, the problems of an increased chip size and accumulated offset voltage may be caused. However, in exemplary embodiments the present invention, an input reference voltage corresponding to the low common electrode voltage VCOML is previously set by the digital logic calculator 310 the number of op-amps and the number of the resistors may be reduced, and the offset voltage need not be accumulated.

Hereinafter, with reference to FIGS. 3, 4, 5 and 6, a method of generating a common voltage according to an exemplary embodiment of the present invention is described.

According to the method for generating a common voltage, a first target voltage of a common voltage and a target amplitude of the common voltage are set at a first control register VCMH[n:1] and an amplitude control register VCMA[m:1], respectively. A second target voltage of the common voltage is set at a second control register VCML[L:1] by using the digital logic calculator 310.

As shown in FIG. 4 through FIG. 6, for example, the first target voltage is Va, Va+Vs, Va+2Vs, . . . , Va+(2ⁿ−1)Vs according to a bit value of the first, control register. The target amplitude is Vb, Vb+Vs, Vb+2Vs, . . . , Vb+(2^m−1)Vs according to a bit value of the amplitude control register. The second target voltage that is outputted from the digital logic calculator 310 is Va+(2ⁿ−1)Vs−Vb, Va+(2ⁿ⁻²)Vs−Vb, . . . , Va+(2^m−1)Vs−Vb according to a bit value of the second control register.

A first input reference voltage VCMH_R and a second input reference voltage VCML_R are generated by a first control register VCMH[n:1] and a second control register VCML[L:1], respectively,

A first common voltage VCOMH and a second common voltage VCOML are outputted by receiving the first input reference voltage VCMH_R and the second input reference voltage VCML_R, respectively.

The common voltage generating circuit in FIG. 3 may be applied to a display system as illustrated in FIG. 1.

If the common voltage generating circuit in FIG. 3 is applied to the system in FIG. 1, a chip size and accumulated offset voltage of a liquid crystal display (LCD) may be reduced.

As mentioned above, the common voltage generating circuit and method, and the LCD device including the common voltage generating circuit according to exemplary embodiments of the present invention may decrease the size of a chip by reducing the number of op-amps and the number of resistors. Problems of accumulated offset voltage may be reduced or eliminated. An input reference voltage corresponding to a target voltage of VCOML may be previously set by a digital logic calculator.

While the exemplary embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the invention.

Claims

1. A method of generating a common voltage comprising: setting a first control register and an amplitude control register to a first target voltage of a common voltage and a target amplitude of the common voltage, respectively;setting a second control register to a second target voltage of the common voltage based on the first target voltage and the target amplitude;generating a first input reference voltage and a second input reference voltage corresponding to the values of the first and second control registers, respectively; andoutputting a first common voltage and a second common voltage by receiving the first and second input reference voltages, respectively.

2. The method of claim 1, wherein calculating the value the second control register is set to is performed by a digital logic calculator.

3. The method of claim 2, wherein the first control register is an n-bit register, the second control register is an L-bit register, and the amplitude control register is an m-bit register, wherein n, L, m are positive integers.

4. The method of claim 3, wherein the first target voltage corresponds to one of Va, Va+Vs, Va+2Vs, . . . , or Va+(2n−1)Vs according to a bit value of the first control register.

5. The method of claim 3, wherein the target amplitude corresponds to one of Vb, Vb+Vs, Vb−2Vs, . . . , or Vb+(2m−1)Vs according to a bit value of the amplitude control register.

6. The method of claim 3, wherein the second target voltage corresponds to one of Va+(2n−1)Vs−Vb, Va+(2n−2)Vs−Vb, . . . , or Va+(2m−1)Vs−Vb according to a bit value of die second control register.

7. The method of claim 1, wherein the first common voltage is outputted by an operational amplifier (op-amp) having a gain of a+1, wherein a is a positive integer.

8. The method of claim 1, wherein the second common voltage is outputted by an op-amp having a gain of 1 and an op-amp having a gain of −b that are cascade-coupled with each other, wherein b is a positive integer.

9. The method of claim 7, wherein the first common voltage is outputted as a high common voltage.

10. The method of claim 8, wherein the second common voltage is outputted as a low common voltage.

11. A circuit for generating a common voltage comprising: a digital logic calculator configured to output a value of a second control register that is set to a second target voltage of a common voltage by receiving a value of an amplitude control register that is set to a target amplitude of the common voltage;an input reference voltage generator configured to generate a first input reference voltage and a second input reference voltage by receiving a value of a first control register that is set to a first target voltage of the common voltage and the value of the second control register; anda buffer unit configured to output a first common voltage and a second common voltage by receiving the first input reference voltage and the second input reference voltage.

12. The circuit of claim 11, further comprising: a common voltage driver configured to receive the first common voltage and the second common voltage and provide the first common voltage and the second common voltage to a common electrode.

13. The circuit of claim 11, wherein the digital logic calculator calculates the value of the amplitude control register and the value of the first control register.

14. The circuit of claim 13, wherein the first control register is an n-bit register, the second control register is an L-bit register, and the amplitude control register is an m-bit register, wherein n, L, m are positive integers.

15. The circuit, of claim 14, wherein the first target voltage corresponds to one of Va, Va+Vs, Va+2Vs, . . . , or Va+(2n−1)Vs according to a bit value of the first control register.

16. The circuit of claim 14, wherein the target amplitude corresponds to one of Vb, Vb+Vs, Vb+2Vs, . . . , or Vb+(2m−1)Vs according to a bit value of the amplitude control register.

17. The circuit of claim 14, wherein the second target voltage corresponds to one of Va+(2n−1)Vs−Vb, Va+(2n−2)Vs−Vb, . . . , or Va+(2m−1)Vs−Vb according to a bit value of the second control register.

18. The circuit of claim 12, wherein the buffer unit comprises: a high buffer configured to output the first common voltage by receiving the first input reference voltage; anda low buffer configured to output the second common voltage by receiving the second input reference voltage.

19. The circuit of claim 18, wherein the high buffer includes an op-amp having a gain of a+1, wherein a is a positive integer.

20. The circuit of claim 18, wherein the low buffer includes an op-amp having a gain of 1 and an op-amp having a gain of −b, wherein b is a positive integer.

21. The circuit of claim 20, wherein the op-amp of the low buffer having a gain of 1 and the op-amp of the low buffer having a gain of −b are cascade-coupled with each other.

22. The circuit of claim 18, wherein the first common voltage is outputted as a high common voltage and the second common voltage is outputted as a low common voltage.

23. A liquid crystal display (LCD) comprising: a liquid crystal display panel coupled to a plurality of gate lines and data lines;a gate driver configured to drive the gate lines of the liquid crystal display panel;a source driver configured to drive the data lines of the liquid crystal display panel; anda common voltage driver circuit configured to drive a common voltage that is applied to a common electrode of the liquid crystal display panel, the common voltage driver circuit comprising a common voltage generator and a common voltage driver receiving and providing the first common voltage and the second common voltage to the common electrode, the common voltage generator comprising: a digital logic calculator outputting a value of a second control register that is set to a second target voltage of a common voltage by receiving a value of an amplitude control register that is set to a target amplitude of the common voltage;an input reference voltage generator generating a first input reference voltage and a second input reference voltage by receiving a value of a first control register that is set to a first target voltage of the common voltage and the value of the second control register; anda buffer unit outputting a first common voltage and a second common voltage by receiving the first input reference voltage and the second input reference voltage.

24. The LCD of claim 23, wherein the digital logic calculator calculates the value of the amplitude control register and the value of the first control register.