The present disclosure relates to electronic circuits, and more particularly, to circuits and methods for programmable memory.
A field programmable gate array (FPGA) is a type of integrated circuit that includes programmable interconnects and programmable logic blocks. The interconnects and logic blocks are programmable after fabrication in an FPGA. In an application specific integrated circuit (ASIC), the logic circuitry and interconnects typically have substantially less configurable features after fabrication than an FPGA. In general, an ASIC can implement a larger circuit design than an FPGA, because an ASIC is designed to use die area more efficiently, but ASIC design flow is often more expensive and complex than configuring an FPGA. A structured application specific integrated circuit (ASIC) has intermediate features between a standard ASIC and an FPGA. A structured ASIC may have the same basic logic structure as an FPGA, while being mask-programmable instead of field-programmable, by configuring vias between metal layers in the integrated circuit. Each configuration bit in an FPGA can be replaced in a structured ASIC by either placing or not placing a via between metal contacts.
Many types of integrated circuits have circuit blocks of memory arrays that are used for storing data. In some integrated circuits, one or more memory arrays are used, for example, as register files. Memory array circuit blocks may be placed in different locations in an integrated circuit (IC). User designs for FPGAs and structured ASICs may require different configurations of memory arrays. For this reason, it may be inefficient to place non-configurable memory arrays in the IC, because one or more of the non-configurable memory arrays may not be placed at the correct location for a particular user design. It would be inefficient in terms of die area usage to place each of the configurations of the memory array in every location in the IC where the memory array configurations might be used by a user design.
In some conventional FPGA and structured ASIC designs, the locations of particular memory array configurations are anticipated and placed at selected locations on the IC. However, because of inaccuracies in predicting which memory array configurations are needed at particular locations in an IC, data signals may have to be routed long distances in the IC to where the correct memory configurations are placed. This technique degrades signal performance and increases power dissipation. In some user designs, there may be an insufficient number of memory array blocks of the needed configurations in the IC. The designers of these user designs have to use a larger memory array or more memory array circuit blocks than are needed by the user designs, resulting in designs that use more power, are more costly, and have lower performance.
According to some embodiments disclosed herein, a memory circuit block can be reconfigured for different user designs of an integrated circuit (IC). The memory circuit block can be used for different purposes, for example, as a register file. Resources, such as flip-flops, in the memory circuit block can be repurposed to implement different configurations for the memory circuit block without having to place additional redundant resources in the IC, such as additional flip-flops and output drivers. The repurposed resources are strategically placed to minimize inefficiencies and large changes in timing for different reconfigurations of the memory circuit block. The memory circuit block may be placed in the IC to enable the resource repurposing without causing large variations in the interconnect loading. Because the memory circuit block can be reconfigured to satisfy the needs of different user designs for an IC, it is not necessary to anticipate the particular memory configuration that is needed in each part of the IC, if the reconfigurable memory circuit block is placed at strategic locations throughout the IC.
Various embodiments disclosed herein can enable the strategic placement of one or more circuit blocks containing memory array circuits in an integrated circuit (IC). The circuit blocks can be placed in locations in the IC that enable the reconfiguration of the memory array circuits for different configurations without requiring extra overhead. These embodiments can achieve optimized signal performance, power usage, die area, and cost. The circuit blocks can be reconfigured without performance loss. Because the circuit blocks can be reconfigured for the needs of different user designs (e.g., for an FPGA or structured ASIC), a logic circuit block in the IC is more likely to be near a memory array having the configuration needed by that logic circuit block. As a result, less interconnect resources are needed to couple the logic circuit block to the memory array, which improves performance of the memory array. Also, extra memory arrays do not need to be placed in the IC to ensure that a logic circuit block is near the memory array configuration used by that logic circuit block, which reduces IC die size and cost.
Figure (
Each of the memory array circuits 101-104 may include an array of any type of memory circuit, for example, random access memory (RAM), Flash memory, volatile or non-voltage memory, EEPROM memory, flip-flop memory, etc. Each individual memory storage circuit in memory arrays 101-104 may be, for example, a memory cell that stores one or more bits. Each of the memory array circuits 101-104 may also include input driver circuits for driving input data signals to the memory cells and output driver circuits for driving output data signals from the memory cells.
During a write operation to store data in one or more of the memory array circuits 101-104, a maximum of 16 data input signals DIN[15:0] may be provided to circuit block 100. Data input signals DIN[0]-DIN[15] are provided to inputs of flip-flop circuits 140-155, respectively, as shown in Figure (
Also, during a write operation to one or more of the memory array circuits 101-104, three, four, or five write address signals WA[4:0] are provided to inputs of flip-flop circuits 148, 147, 131, 132, and 133, as shown in
Write address signals WA[0] and WA[1] are only provided to inputs of flip-flop circuits 148 and 147, respectively, during certain configurations of memory array enable circuit 120. Examples of the memory array enable circuit 120 that are configured to receive one or both of the write address signals WA[0] and WA[1] are disclosed herein with respect to
LWL enable circuits 11-14 generate write address signals wwl for memory arrays 101-104, respectively, based on the decoded global write address signals GWWL and based on the decoded local write address signals received from LWL decoder circuits 115-116. LWL enable circuits 11-14 provide the write address signals wwl to memory array circuits 101-104, respectively. Memory array circuits 101-104 select their memory cells having the addresses indicated by the set of write address signals wwl received from the respective LWL enable circuits 11-14. Memory array circuits 101-104 store the data indicated by the data input signals received from the write programmable matrix circuit 123 in the selected memory cells that have the addresses indicated by the set of write address signals wwl received from the respective LWL enable circuits 11-14. The write operation is then complete.
During a read operation to read data stored in one or more of the memory array circuits 101-104, 5 read address signals RA[4:0] are provided to circuit block 100. Three read address signals RA[4:2] are provided to GWL decoder circuit 111. GWL decoder circuit 111 decodes the values of the read address signals RA[4:2] to generate decoded global read address signals GRWL that are provided to inputs of LWL enable circuits 11-14. Read address signals RA[0] and RA[1] are provided to inputs of LWL address decoder circuits 114 and 113, respectively. LWL address decoder circuits 113-114 decode the read address signals RA[1] and RA[0] to generate decoded local read address signals. The decoded local read address signals generated by LWL address decoder circuit 113 are provided to LWL enable circuits 11-12, and the decoded local read address signals generated by LWL address decoder circuit 114 are provided to LWL enable circuits 13-14.
LWL enable circuits 11-14 generate read address signals rwl for memory arrays 101-104, respectively, based on the decoded global read address signals GRWL received from decoder 111 and based on the decoded local read address signals received from LWL address decoder circuits 113-114. LWL enable circuits 11-14 provide the read address signals rwl to memory array circuits 101-104, respectively. Memory array circuits 101-104 select their memory cells having the addresses indicated by the set of read address signals rwl received from the respective LWL enable circuits 11-14. Memory array circuits 101-104 read the data stored in the selected memory cells that have the addresses indicated by the set of read address signals rwl received from the respective LWL enable circuits 11-14. Memory array circuits 101-104 then output the data read from these selected memory cells to read programmable matrix circuit 122. Read programmable matrix circuit 122 then provides the data received from one or more of the memory array circuits 101-104 to outputs of memory circuit block 100 as 16 output data signals DO [15:0]. The read operation is then complete.
Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductors 211-212 to/from conductors 229-230. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 221 to/from conductor 212 and conductor 214. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 222 to/from conductor 211 and conductor 214. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 223 to/from conductor 212 and conductor 214. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 224 to/from conductor 211 and conductor 213. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 225 to/from conductor 212 and conductor 213. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 226 to/from conductor 211 and conductor 214. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 227 to/from conductor 212 and conductor 213. Two of the programmable vias in circuit 120 can be selectively programmed to couple or decouple conductor 228 to/from conductor 211 and conductor 213.
Inverting inputs of the AND gates 201-204 are shown as circles in
AND gate circuits 201-204 generate memory array enable signals BK0EN, BK1EN, BK2EN, and BK3EN, respectively, at their outputs by performing Boolean logic functions on their input signals. The memory array enable signals BK0EN, BK1EN, BK2EN, and BK3EN are provided through conductors in circuit block 100 to enable inputs of memory array circuits 101, 102, 103, and 104, respectively, as shown in
The first inverting input of AND gate circuit 201 at conductor 221 may be programmably coupled to receive signal DFFQ[8] through conductor 212 or ground voltage VSS through conductor 214. The second inverting input of AND gate circuit 201 at conductor 222 may be programmably coupled to receive signal DFFQ[7] through conductor 211 or ground voltage VSS through conductor 214. The inverting input of AND gate circuit 202 at conductor 223 may be programmably coupled to receive signal DFFQ[8] through conductor 212 or ground voltage VSS through conductor 214. The non-inverting input of AND gate circuit 202 at conductor 224 may be programmably coupled to receive signal DFFQ[7] through conductor 211 or supply voltage VDD through conductor 213.
The non-inverting input of AND gate circuit 203 at conductor 225 may be programmably coupled to receive signal DFFQ[8] through conductor 212 or supply voltage VDD through conductor 213. The inverting input of AND gate circuit 203 at conductor 226 may be programmably coupled to receive signal DFFQ[7] through conductor 211 or ground voltage VSS through conductor 214. The first non-inverting input of AND gate circuit 204 at conductor 227 may be programmably coupled to receive signal DFFQ[8] through conductor 212 or supply voltage VDD through conductor 213. The second non-inverting input of AND gate circuit 204 at conductor 228 may be programmably coupled to receive signal DFFQ[7] through conductor 211 or supply voltage VDD through conductor 213.
According to various embodiments, the programmable vias in the memory array enable circuit 120 of
As a specific example that is not intended to be limiting, 5 address bits may be used to decode 1 of 32 entries in a 32×8 memory array, 4 address bits may be used to decode 1 of 16 entries in a 16×8 memory array, and 3 address bits may be used to decode 1 of 8 entries in an 8×16 memory array. According to some embodiments disclosed herein, for example in
In the embodiment of
In the embodiment of
Conductive vias 303-304 connect conductors 223-224 at the inputs of AND gate 202 to conductors 214 and 213, respectively. Conductive via 303 couples the inverting input of AND gate 202 to ground voltage VSS, and conductive via 304 couples the non-inverting input of AND gate 202 to supply voltage VDD. As a result, AND gate 202 causes its output signal BK1EN to be in a logic high state. In response to enable signal BK1EN being in a logic high state, memory array circuit 102 is enabled to store data in its memory cells during a write operation, and memory array circuit 102 is enabled to read data stored in its memory cells during a read operation.
Conductive vias 305-306 connect conductors 225-226 at the inputs of AND gate 203 to conductors 213 and 214, respectively. Conductive via 305 couples the non-inverting input of AND gate 203 to supply voltage VDD, and conductive via 306 couples the inverting input of AND gate 203 to ground voltage VSS. As a result, AND gate 203 causes its output signal BK2EN to be in a logic high state. In response to enable signal BK2EN being in a logic high state, memory array circuit 103 is enabled to store data in its memory cells during a write operation, and memory array circuit 103 is enabled to read data stored in its memory cells during a read operation.
Conductive vias 307-308 connect conductors 227-228, respectively, at the inputs of AND gate 204 to conductor 213. Conductive vias 307-308 couple the non-inverting inputs of AND gate 204 to supply voltage VDD through conductor 213. As a result, AND gate 204 causes its output signal BK3EN to be in a logic high state. In response to enable signal BK3EN being in a logic high state, memory array circuit 104 is enabled to store data in its memory cells during a write operation, and memory array circuit 104 is enabled to read data stored in its memory cells during a read operation. Each of the inputs of the AND gates 201-204 is coupled to a constant voltage in
In the embodiment of
Programmable vias 311 and 313 are programmed to couple the second inverting input of AND gate 201 to the output of flip-flop circuit 147 through conductors 222, 211, and 229. Programmable vias 312-313 are programmed to couple the second non-inverting input of AND gate 202 to the output of flip-flop circuit 147 through conductors 224, 211, and 229. Programmable vias 313-314 are programmed to couple the second inverting input of AND gate 203 to the output of flip-flop circuit 147 through conductors 226, 211, and 229. Programmable vias 313 and 315 couple the second non-inverting input of AND gate 204 to the output of flip-flop circuit 147 through conductors 228, 211, and 229.
In the embodiment of
Because constant voltages VSS/VDD are provided to the first inputs of AND gates 201-204 as described above, the logic states of the enable signals BK0EN-BK3EN vary in response to changes in the logic state of signal WAQ[1] at the second inputs of AND gates 201-204, respectively. In response to signal WAQ[1] being in a logic high state (i.e., corresponding to a 1 bit), the AND gates 201 and 203 drive their output signals BK0EN and BK2EN to logic low states, and the AND gates 202 and 204 drive their output signals BK1EN and BK3EN to logic high states. In response to enable signals BK0EN and BK2EN being in logic low states, memory array circuits 101 and 103 are disabled and do not store or read data during write and read operations. In response to enable signals BK1EN and BK3EN being in logic high states, memory array circuits 102 and 104 are enabled to store and read data during write and read operations.
In response to signal WAQ[1] being in a logic low state (i.e., corresponding to a 0 bit), the AND gates 201 and 203 drive their output signals BK0EN and BK2EN to logic high states, and the AND gates 202 and 204 drive their output signals BK1EN and BK3EN to logic low states. In response to enable signals BK0EN and BK2EN being in logic high states, memory array circuits 101 and 103 are enabled to store and read data during write and read operations. In response to enable signals BK1EN and BK3EN being in logic low states, memory array circuits 102 and 104 are disabled and do not store or read data during write and read operations.
In the embodiment of
The programmable vias 311-315 in
In the embodiment of
In response to signal WAQ[1] being in a logic high state, and signal WAQ[0] being in a logic low state, the output signal BK1EN of AND gate 202 is in a logic high state, enabling write and read operations in memory array circuit 102, and the output signals BK0EN, BK2EN, and BK3EN of AND gates 201, 203, and 204 are in logic low states, disabling write and read operations in memory array circuits 101, 103, and 104, respectively. In response to signal WAQ[1] being in a logic low state, and signal WAQ[0] being in a logic high state, the output signal BK2EN of AND gate 203 is in a logic high state, enabling write and read operations in memory array circuit 103, and the output signals BK0EN, BK1EN, and BK3EN of AND gates 201, 202, and 204 are in logic low states, disabling write and read operations in memory array circuits 101, 102, and 104, respectively. Thus, in the configuration of
Referring to
The option conductors 601-612 and 621-624 are optional connections between various conductors in the write programmable matrix 123. One or more of the option conductors 601-612 and 621-624 may, for example, be formed of conductive material (e.g., metal) in a conductive layer that is deposited on the integrated circuit (IC) during fabrication of the IC and that connects adjacent conductors together. The IC may be, for example, a structured ASIC. In some embodiments, the write programmable matrix 123 is programmed during fabrication of the integrated circuit by changing the option conductors 601-612 and 621-624 to couple at least a subset of the data inputs of the write programmable matrix 123 that receive at least a subset of signals DFFQ[0]-DFFQ[15] to the data inputs of one or more of the memory array circuits 101-104. The option conductors 601-612 and 621-624 may be changed by modifying one or more masks that are used to form one or more conductive layers containing the option conductors 601-612 and 621-624. The masks are used during a photolithography process of forming the conductive layers on the integrated circuit to make selected ones of the option conductors 601-612 and 621-624 either connect or disconnect adjacent conductors. The masks may, for example, either allow conductive material to form or prevent conductive material from forming in the location of each of the option conductors 601-612 and 621-624 in the conductive layers.
Any number of the option conductors 601-612 may be formed to be conductive to connect the adjacent vertical conductors (shown as vertical lines in
In
The option conductors 701-712 and 721-724 are optional connections between various conductors in the read programmable matrix 122. One or more of the option conductors 701-712 and 721-724 may, for example, be formed of conductive material (e.g., metal) in a conductive layer that is deposited on the integrated circuit (IC) during fabrication of the IC and that connects conductors together that are adjacent to the option conductor. The IC may be, for example, a structured ASIC. In some embodiments, the read programmable matrix 122 is programmed during fabrication of the IC by changing option conductors 701-712 and 721-724 to couple the data outputs of one or more of the memory array circuits 101-104 to at least a subset of the data outputs of read programmable matrix circuit 122 that provide at least a subset of output signals DO[0]-DO[15]. The option conductors 701-712 and 721-724 may be changed by modifying one or more masks that are used to form one or more conductive layers containing the option conductors 701-712 and 721-724. The masks are used during a photolithography process of forming the conductive layers on the integrated circuit to make selected ones of the option conductors 701-712 and 721-724 either connect or disconnect adjacent conductors. The masks may, for example, either allow conductive material to form or prevent conductive material from forming in the location of each of the option conductors 701-712 and 721-724.
A selected number of the option conductors 701-712 may be formed to be conductive to connect the adjacent vertical conductors (shown as vertical lines in
In an exemplary embodiment, the configuration 800 of the write programmable matrix circuit 123 shown in
When signals WAQ[1] and WAQ[0] both have logic states of 0, memory array circuit 101 is enabled, memory array circuits 102-104 are disabled, and the data bits indicated by signals DFFQ[0]-DFFQ[3] are provided to inputs of memory array circuit 101 as signals WBL[0]-WBL[3], respectively. When signals WAQ[1] and WAQ[0] have logic states of 0 and 1, respectively, memory array circuit 103 is enabled, memory array circuits 101-102 and 104 are disabled, and the data bits indicated by signals DFFQ[0]-DFFQ[3] are provided to inputs of memory array circuit 103 as signals WBL[8]-WBL[11], respectively, through conductive vias 635-638 and 643-646 and option conductors 621-624.
In an exemplary embodiment, the configuration 900 of the read programmable matrix circuit 122 shown in
When signals WAQ[1] and WAQ[0] both have logic states of 0, memory array circuit 101 is enabled, memory array circuits 102-104 are disabled, and the data bits indicated by signals RBL[0]-RBL[3] are provided to data outputs of circuit block 100 as signals DO[0]-DO[3], respectively. When signals WAQ[1] and WAQ[0] have logic states of 0 and 1, respectively, memory array circuit 103 is enabled, memory array circuits 101-102 and 104 are disabled, and the data bits indicated by signals RBL[8]-RBL[11] are provided to data outputs of circuit block 100 as signals DO[0]-DO[3], respectively, through conductive vias 735-738 and 743-746 and option conductors 721-724.
In an exemplary embodiment, the configuration 1000 of the write programmable matrix circuit 123 shown in
Referring to configuration 1000, when address signal WA[1] has a logic state of 1, memory array circuits 101 and 103 are disabled, memory array circuits 102 and 104 are enabled, the data bits indicated by signals DFFQ[0]-DFFQ[3] are provided to data inputs of memory array circuit 102 as signals WBL[4]-WBL[7], respectively, through conductive vias 639-646, and the data bits indicated by signals DFFQ[8]-DFFQ[11] are provided to data inputs of memory array circuit 104 as signals WBL[12]-WBL[15], respectively, through conductive vias 631-638. When signal WA[1] has a logic state of 0, memory array circuits 102 and 104 are disabled, memory array circuits 101 and 103 are enabled, the data bits indicated by signals DFFQ[0]-DFFQ[3] are provided to data inputs of memory array circuit 101 as signals WBL[0]-WBL[3], respectively, and the data bits indicated by signals DFFQ[8]-DFFQ[11] are provided to inputs of memory array circuit 103 as signals WBL[8]-WBL[11] through option conductors 605-608, respectively.
In an exemplary embodiment, the configuration 1100 of the read programmable matrix circuit 122 shown in
Referring to configuration 1100, when address signal WA[1] has a logic state of 1, memory array circuits 101 and 103 are disabled, memory array circuits 102 and 104 are enabled, the data bits indicated by signals RBL[4]-RBL[7] are provided to data outputs of matrix 122 as signals DO[0]-DO[3], respectively, through conductive vias 739-746, and the data bits indicated by signals RBL[12]-RBL[15] are provided to data outputs of matrix 122 as signals DO[8]-DO[11], respectively, through conductive vias 731-738 and option conductors 705-708. When address signal WA[1] has a logic state of 0, memory array circuits 101 and 103 are enabled, memory array circuits 102 and 104 are disabled, the data bits indicated by signals RBL[0]-RBL[3] are provided to data outputs of matrix 122 as signals DO[0]-DO[3], respectively, and the data bits indicated by signals RBL[8]-RBL[11] are provided to data outputs of matrix 122 as signals DO[8]-DO[11] through option conductors 708, 707, 706, and 705, respectively.
In addition, structured ASIC 1400 has input/output elements (IOEs) 1402 for driving signals off the IC and for receiving signals from other devices. Each of the IOEs 1402 includes one or more input buffers, one or more output buffers, and one or more IO pads. Input/output elements 1402 may include parallel input/output circuitry, serial data transceiver circuitry, differential receiver and transmitter circuitry, or other circuitry used to connect one integrated circuit to another integrated circuit. As shown, input/output elements 1402 may be located around the periphery of the ASIC. If desired, ASIC 1400 may have input/output elements 1402 arranged in different ways. For example, input/output elements 1402 may form one or more columns, rows, or islands of input/output elements that may be located anywhere on the ASIC.
The structured ASIC 1400 also includes interconnect circuitry in the form of vertical routing channels 1440 (i.e., interconnects formed along a vertical axis of ASIC 1400) and horizontal routing channels 1450 (i.e., interconnects formed along a horizontal axis of ASIC 1400), each routing channel including at least one track to route at least one conductor (e.g., wire). Note that other routing topologies, besides the topology of the interconnect circuitry depicted in
Furthermore, it should be understood that embodiments disclosed herein with respect to
Structured ASIC 1400 also contains random access memory (RAM) blocks 1430. Each of the RAM blocks 1430 in ASIC 1400 may include one or more of the memory circuit blocks 100 shown in
The following examples pertain to further embodiments. Example 1 is an integrated circuit comprising: a first memory array circuit; flip-flop circuits, wherein a first one of the flip-flop circuits is coupled to store one of a first write address signal or a first data input signal, and wherein a second one of the flip-flop circuits is coupled to store one of a second write address signal or a second data input signal; and a write programmable matrix circuit coupled to receive signals stored in the flip-flop circuits, wherein the write programmable matrix circuit is coupled to provide a first subset of the signals stored in the flip-flop circuits to inputs of the first memory array circuit through first option conductors in the write programmable matrix circuit during write operations to the first memory array circuit.
In Example 2, the integrated circuit of Example 1 can optionally further comprise: a read programmable matrix circuit coupled to provide data output signals from data outputs of the first memory array circuit to data outputs of the read programmable matrix circuit through second option conductors during read operations to the first memory array circuit.
In Example 3, the integrated circuit of any one of Examples 1-2 can optionally further comprise a memory array enable circuit comprising vias and a logic gate circuit, wherein the vias are filled with conductive material to couple first conductors at inputs of the logic gate circuit to second conductors to provide control signals to the inputs of the logic gate circuit to control enabling the first memory array circuit to perform the read and write operations.
In Example 4, the integrated circuit of any one of Examples 1-3 can optionally further comprise a second memory array circuit, wherein the write programmable matrix circuit is coupled to provide a second subset of the signals stored in the flip-flop circuits to inputs of the second memory array circuit through second option conductors in the write programmable matrix circuit during the write operations.
In Example 5, the integrated circuit of Example 4 can optionally further comprise a third memory array circuit, wherein the write programmable matrix circuit is coupled to provide a third subset of the signals stored in the flip-flop circuits to inputs of the third memory array circuit through programmable vias during the write operations.
In Example 6, the integrated circuit of any one of Examples 1-3 can optionally further comprise a second memory array circuit, wherein the write programmable matrix circuit is coupled to provide a second subset of the signals stored in the flip-flop circuits to inputs of the second memory array circuit through programmable vias during the write operations.
In Example 7, the integrated circuit of any one of Examples 1-3 or 6 can optionally include, wherein the write programmable matrix circuit is programmed during fabrication of the integrated circuit to change the first option conductors to couple first inputs of the write programmable matrix circuit to the inputs of the first memory array circuit by modifying a mask that is used to form the first option conductors, and wherein the write programmable matrix circuit is programmed during fabrication of the integrated circuit to change second option conductors to decouple second inputs of the write programmable matrix circuit from the inputs of the first memory array circuit by modifying a mask that is used to form the second option conductors.
In Example 8, the integrated circuit of any one of Examples 1-7 can optionally include, wherein the write programmable matrix circuit is programmed during fabrication of the integrated circuit to change programmable vias to couple inputs of the write programmable matrix circuit to the inputs of the first memory array circuit by filling the programmable vias with conductive material, and wherein the integrated circuit is a structured application specific integrated circuit.
Example 9 is an integrated circuit comprising: a first memory array circuit; a write programmable matrix circuit coupled to receive data input signals and to provide the data input signals to data inputs of the first memory array circuit through first option conductors in the write programmable matrix circuit during write operations to the first memory array circuit; and a read programmable matrix circuit coupled to provide first data output signals from data outputs of the first memory array circuit to a first subset of data outputs of the read programmable matrix circuit through second option conductors in the read programmable matrix circuit during read operations to the first memory array circuit.
In Example 10, the integrated circuit of Example 9 can optionally further comprise a second memory array circuit, wherein the read programmable matrix circuit is coupled to provide second data output signals from data outputs of the second memory array circuit to a second subset of the data outputs of the read programmable matrix circuit through third option conductors in the read programmable matrix circuit during the read operations.
In Example 11, the integrated circuit of any one of Examples 9-10 can optionally further comprise a second memory array circuit, wherein the read programmable matrix circuit is coupled to provide second data output signals from data outputs of the second memory array circuit to a second subset of the data outputs of the read programmable matrix circuit through programmable vias in the read programmable matrix circuit during the read operations.
In Example 12, the integrated circuit of any one of Examples 9-11 can optionally further comprise flip-flop circuits that store received signals, wherein the received signals are provided from the flip-flops circuits to the write programmable matrix circuit, wherein a first one of the flip-flop circuits is coupled to receive one of a first write address signal or a first one of the data input signals as a first one of the received signals, and wherein a second one of the flip-flop circuits is coupled to receive one of a second write address signal or a second one of the data input signals as a second one of the received signals.
In Example 13, the integrated circuit of any one of Examples 9-11 can optionally further comprise a first flip-flop circuit programmed during fabrication of the integrated circuit to provide one of a first write address signal or a first one of the data input signals to the write programmable matrix circuit; and a second flip-flop circuit programmed during fabrication of the integrated circuit to provide one of a second write address signal or a second one of the data input signals to the write programmable matrix circuit.
In Example 14, the integrated circuit of any one of Examples 9-13 can optionally include, wherein the read programmable matrix circuit is programmed during fabrication of the integrated circuit to change third option conductors to decouple the data outputs of the first memory array circuit from a second subset of the data outputs of the read programmable matrix circuit by changing a mask that is used to form the third option conductors.
In Example 15, the integrated circuit of any one of Examples 9-14 can optionally include, wherein the read programmable matrix circuit is programmed during fabrication of the integrated circuit to change programmable vias to couple the data outputs of the first memory array circuit to the first subset of the data outputs of the read programmable matrix circuit by filling the programmable vias with conductive material, and wherein the integrated circuit is a structured application specific integrated circuit.
Example 16 is a method for forming a memory circuit block in an integrated circuit, the method comprising: forming in the integrated circuit a write programmable matrix circuit by forming first option conductors that couple a first subset of data inputs of the write programmable matrix circuit to data inputs of a first memory array circuit to provide data input signals to the first memory array circuit during write operations using a mask that has been modified to form the first option conductors; and forming in the integrated circuit a read programmable matrix circuit by forming second option conductors that couple data outputs of the first memory array circuit to a first subset of data outputs of the read programmable matrix circuit to provide data output signals of the first memory array circuit during read operations using a mask that has been modified to form the second option conductors.
In Example 17, the method of Example 16 can optionally further comprise: forming in the integrated circuit a memory array enable circuit comprising a logic gate circuit and vias that are filled with conductive material to couple inputs of the logic gate circuit to receive control signals for enabling the first memory array circuit to perform the read and write operations.
In Example 18, the method of any one of Examples 16-17 can optionally include, wherein forming the write programmable matrix circuit further comprises forming third option conductors that couple a second subset of the data inputs of the write programmable matrix circuit to data inputs of a second memory array circuit using a mask that has been modified to form the third option conductors to provide additional data input signals to the second memory array circuit during the write operations.
In Example 19, the method of any one of Examples 16-17 can optionally include, wherein forming the write programmable matrix circuit further comprises forming the first option conductors to couple the first subset of the data inputs of the write programmable matrix circuit to data inputs of a second memory array circuit using the mask that has been modified to form the first option conductors.
In Example 20, the method of any one of Examples 16-17 can optionally include, wherein forming the read programmable matrix circuit further comprises forming third option conductors to couple data outputs of a second memory array circuit to a second subset of the data outputs of the read programmable matrix circuit using a mask that has been modified to form the third option conductors.
While the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims. Moreover, the techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).