Circuits for amplitude demodulation and related methods

Abstract

A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately π/2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.

Description

BACKGROUND

Amplitude modulation schemes are often used in wireless communications to transmit signals between a transmitter and a receiver. An amplitude modulated signal can be generated by mixing a baseband signal with a carrier. Amplitude modulation schemes are often used in near-field communication (NFC) and in radio-frequency identification (RFID) systems.

SUMMARY

According to one aspect of the present application, an amplitude demodulator is provided. The amplitude demodulator may comprise a clock extractor configured to extract a clock signal from an input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by an amount that is approximately ±nπ/2 wherein n is an odd integer, and a sampler configured to sample the input signal with a timing controlled by the sampling signal.

According to another aspect of the present application, a method for demodulating an input signal is provided. The method may comprise extracting a clock signal from an input signal, generating a sampling signal by phase-shifting the clock signal by an amount that is approximately ±nπ/2 wherein n is an odd integer, and sampling the input signal with a timing controlled by the sampling signal.

The foregoing summary is provided by way of illustration and is not intended to be limiting.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing.

FIG. 1A is a block diagram illustrating a communication system, according to some non-limiting embodiments.

FIG. 1B is a plot illustrating a baseband signal and an amplitude-modulated signal, according to some non-limiting embodiments.

FIG. 1C is a schematic diagram illustrating a portion of a receiver including a winding and a matching network, according to some non-limiting embodiments.

FIG. 2A is a clock diagram illustrating a demodulator, according to some non-limiting embodiments.

FIG. 2B is a plot illustrating a representative characteristic of a clock extractor, according to some non-limiting embodiments.

FIG. 2C is a plot illustrating an input signal, a clock signal, a phase-shifted signal, and an output signal, according to some non-limiting embodiments.

FIG. 3 is a plot illustrating an input signal having a 100%-modulation depth, according to some non-limiting embodiments.

FIG. 4A is a block diagram of a demodulator comprising, among other components, a locking oscillator, according to some non-limiting embodiments.

FIG. 4B is a plot illustrating a sampling signal in the presence of an input signal having a 100%-modulation depth, according to some non-limiting embodiments.

FIG. 5A is a block diagram of a demodulator including, among other components, a pair of phase shifters, according to some non-limiting embodiments.

FIG. 5B is a plot illustrating an input signal, a clock signal, a pair of phase-shifted signals, and a pair of output signals, according to some non-limiting embodiments.

DETAILED DESCRIPTION

The inventors have developed circuits for amplitude demodulation in which distortion and non-linear effects are reduced without sacrificing power consumption. Some conventional amplitude demodulators, such as envelope demodulators that use signal rectifiers, suffer from distortion and non-linear effects. As a result, errors may arise in the signals received using these circuits. Other conventional amplitude demodulators utilize complicated calibration circuits configured to finely align the sampling circuit to the received modulated signal. Such circuits require substantial amounts of power. Consequently, their usability is significantly limited.

The circuits for amplitude demodulation developed by the inventors can exhibit low distortion and high linearity without sacrificing power consumption. Some embodiments relate to an amplitude demodulator comprising a clock extractor, a phase shifter and a sampler. The clock extractor may generate a clock signal from the received amplitude-modulated signal. The generated clock signal may have, at least in some embodiments, the same frequency as the carrier of the received modulated signal. The generated clock may then be phase shifted, for example by approximately π/2, by approximately −π/2, or by approximately ±nπ/2 where n is an odd integer. The term “approximately” is used herein with respect to phases to indicate a range that is within π/8 of a certain phase. For example, approximately π/2 indicates a range between π/2−π/8 and π/2+π/8, approximately −π/2 indicates a range between −π/2−π/8 and −π/2+π/8 and approximately ±nπ/2 indicates a range between nπ/2+π/8 and nπ/2−π/8 or between −nπ/2+π/8 and −nπ/2−π/8. The amount by which the phase of the clock signal is shifted may be so that the edges of the resulting signal align (or at least approximately align) with the peaks of the received amplitude-modulated signal. The phase-shifted clock signal may then be used to sample the amplitude-modulated signal. In this way, the amplitude-modulated signal may be sampled at its peak (or near its peak), thus enhancing the fidelity of the extracted data.

The circuits for amplitude demodulation described herein may exhibit one or more advantages relative to some conventional amplitude modulators. Non-limiting examples of such advantages are improved linearity, relaxed phase noise requirements, higher data rate and lower power consumption. Of course, other advantages that are not listed herein may arise.

FIG. 1A is a block diagram of a representative communication system, according to some non-limiting embodiments. Communication system 100 includes a modulator 102, a transmitter (TX) 104, a channel 106, a receiver (RX) 108, and a demodulator 110. In some embodiments, modulator 102 may modulate a carrier signal with a baseband signal. The baseband signal may be encoded with binary data in some embodiments, though analog baseband signals may be used in some embodiments. The modulation scheme may be an amplitude modulation. An example of an amplitude modulation scheme that may be used at least in some embodiments is amplitude shift keying (ASK). Of course, other types of amplitude modulation schemes may be used, such as multi-level amplitude modulation schemes.

An example of a signal modulated using an amplitude modulation scheme of the type described herein is depicted in FIG. 1B. Signal 114 represents a representative baseband modulating signal. In this example, signal 114 includes two 1s (level_H), followed by two 0s (level_L), followed by two 1s again. Of course, any suitable succession of values can be applied. Amplitude-modulated signal 116 may be obtained, at least in some embodiments, by mixing signal 114 with a carrier signal. The frequency of the carrier signal may depend on different factors, including among others the type of communication protocol being used. For example, in near-field communication (NFC), the carrier signal may have a frequency of 13.56 MHz±7 KHz (e.g., a frequency that is between 13.553 MHz and 13.567 MHz), and in radio-frequency identification (RFID) systems, a frequency in an industrial, scientific and medical (ISM) radio band may be used. Examples of ISM bands that may be used in some embodiments include 6.765 MHz-6.795 MHz, 26.957 MHz-27.283 MHz, 40.66 MHz-40.7 MHz, and 902 MHz-928 MHz. Of course, any other carrier frequency may be used.

Referring back to FIG. 1A, the amplitude-modulated signal may be provided to TX 104. TX 104 may include a filter, an amplifier, and/or means for transmitting the signal through the channel 106. For example, in the embodiments in which channel 106 is a wireless channel, TX 104 may include an antenna or a magnetic coupler, such as an inductor. In other embodiments, channel 106 may include a wired channel, such as a twisted-pair cable or a coaxial cable. In these embodiments, TX 104 may include a terminal connected to an end of the cable.

Similarly, RX 108 may include antennas, inductors, or other terminals, depending on the type of channel being used. In the embodiments in which the TX and the RX are magnetically coupled, RX 108 may include one or more windings (e.g., wire loops) serving as inductor(s). An example of a winding for RX 108 is depicted in FIG. 1C. In this case, winding 120 is coupled to matching network 122, which may be configured to provide a desired resonant frequency and an antenna load for effective power transfer. The received amplitude-modulated signal may then be demodulated using demodulator 110. Following the demodulation, a baseband signal may be obtained.

An example of a demodulator according to some non-limiting embodiments is depicted in FIG. 2A. Demodulator 200 may include automatic gain control (AGC) unit 202, clock extractor 204, phase shifter 206, sampler 210, and optionally analog-to-digital converter (ADC) 212. AGC 202 may ensure that the received signal is within a suitable dynamic range, such as the dynamic range of clock extractor 204 and/or sampler 210. As such, AGC 202 may include a signal amplifier, and/or an attenuator.

Clock extractor 204 may receive the amplitude-modulated signal, and may in response extract the clock from the amplitude modulated carrier signal. The clock signal may have, at least in some embodiments, the same frequency as the carrier of the modulated signal. In some embodiments, the clock extractor 204 may be implemented according to the input-output characteristic depicted in FIG. 2B. As shown, when the level of the input signal is greater than V_T (which may be zero in some embodiments), the level of the output signal may be equal to V_H. By contrast, when the level of the input signal is less than V_T, the level of the output signal may be equal to V_L (which may be zero in some embodiments). Of course not all embodiments need to be implemented in this manner. Circuits configured to implement the characteristic of FIG. 2B are referred to herein as “threshold circuits.”

FIG. 2C is a plot illustrating the signals appearing in demodulator 200 in a specific example. Signal 216 represents the signal appearing at the input of clock extractor 204. Signal 216 may represent the amplitude-modulated signal transmitted by TX 104. Of course, the received signal need not be an exact replica of the transmitted signal, since noise or other adverse effects may be introduced along the data path (e.g., in the channel). Clock signal 218 represents the signal generated by clock extractor 204. In this example, the clock signal exhibits edges (rising and falling edges) in correspondence with the times at which the amplitude-modulated signal has a zero crossing. In other embodiments, the edges may be slightly offset relative to the zeros of signal 216. This offset may be less than 1%, less than 5%, less than 10%, or less than 15% of the periodicity of the clock signal.

Phase shifter 206 (FIG. 2A) may shift the phase of the clock signal. In some embodiments, the phase may be shifted by an amount so that the edges (e.g., the falling edges) of the resulting signal are substantially aligned (e.g., with an offset that is less than 1%, less than 5%, less than 10%, or less than 15% of the periodicity of the clock signal) with the peaks of the amplitude-modulated signal. For example, the phase of the clock signal may be shifted by approximately π/2, by approximately −π/2, or by approximately ±π/2 where n is an odd integer.

In some embodiments, phase shifter 206 may shift the phase of the clock signal by an amount that is approximately π/2 in absolute value (e.g., the clock signal may be delayed by approximately π/2 or anticipated by approximately π/2).

In the example of FIG. 2C, phase shifter 206 produces signal 220. In this example, signal 220 is π/2-out-of-phase relative to clock signal 218. As a result, the edges of signal 220 are aligned with the peaks of signal 216. It should be appreciated that, in some of the embodiments in which the carrier signal varies in time according to a sinusoidal function, the peaks of signal 216 may fall at the midpoint between two consecutive zeros. As such, shifting the phase of the clock signal by approximately π/2 may ensure that the input signal is sampled in correspondence with (or near) its peaks.

In some embodiments, the phase shifted clock signal may be used to trigger sampler 210. That is, sampler 210 may sample the amplitude-modulated signal in correspondence with the edges (e.g., the falling edges) of the phase-shifted clock signal. As a result, the sampled signal may exhibit an amplitude that is equal to, or at least substantially equal to (e.g., within 99%, 95%, 90%, 85%, 80%, or 75%) the peaks of the amplitude-modulated signal. In the example of FIG. 2C, sampled signal 222 tracks the envelope of signal 216.

In some embodiments, the sampled signal is converted into the digital domain using ADC 212, as shown in FIG. 2A.

Modulation techniques of the types described herein may be used regardless of the modulation depth being used. The inventors have appreciated that, in some circumstances, it may be desirable to use modulation depths that are equal to, or at least close to, 100%. As such, the amplitude of the modulated signal in correspondence to a logic 0 is substantially zero (e.g., less than 100 mV, less than 10 mV, less than 1 mV, or less than 10007, or less than 1000 for the duration of the symbol. This case is illustrated in the example of FIG. 3. Signal 302 is obtained by modulating a carrier signal with the baseband signal 304. As shown, in correspondence with a logic 0, the amplitude of signal 302 is substantially zero. In this circumstance, generation of the clock signal as described above may be impaired by the absence of a time reference, since the amplitude is substantially zero for an extended duration (e.g., for one or more cycles of the input signal, a cycle being defined as the inverse of the carrier frequency of the input signal).

To that end, some embodiments of the present application are directed to circuits for demodulating signals with large modulation depths. For example, some embodiments include locking oscillators (e.g., a phase locked loop or just a voltage-controlled locking oscillator) configured to provide an oscillating signal (e.g., a clock) even when the amplitude-modulated signal is substantially zero.

One such circuit is illustrated in FIG. 4A. Relative to the demodulator of FIG. 2A, locking oscillator 208 is included. Locking oscillator 208 may implemented, for example, as a phased-locked loop (PLL) in some embodiments. Locking oscillator 208 may be implemented as a locked voltage-controlled oscillator in some embodiments. Locking oscillator 208 may be configured to support modulation depths as high as 100%. While locking oscillator 208 is illustrated as being disposed between clock extractor 204 and phase shifter 206, other arrangements are also possible. For example, a locking oscillator may be disposed between phase shifter 206 and sampler 210.

The plot of FIG. 4B illustrates how the demodulator of FIG. 4A may operate, at least in some embodiments. Amplitude-modulated signal 416 is modulated with a modulation depth of 100%. As a result, it exhibits an amplitude equal to zero between t1 and t2. Accordingly, during this period, clock signal 418 ceases to oscillate. The clock signal 418 is may be provided as input to the locking oscillator, which may in response lock to the frequency of clock signal 418 exhibited prior to t1. As a result, signal 419 may continue to oscillate even when the amplitude of signal 416 is equal to zero. As such, locking oscillator 208 may bridge the oscillation across the periods in which the amplitude of the input signal is substantially zero. It should be appreciate that circuits other than a voltage-controlled locking oscillator may be used to perform the bridging function in some embodiments. Signal 420 may be obtained by phase-shifting signal 419 as described above, and signal 422 may be obtained by sampling signal 416 with signal 420.

Some of the embodiments described above may be configured to sample only the positive peaks (or alternatively, the negative peaks) of the input signal. In other embodiments, both the positive and the negative peaks may be sampled. In this way, a differential signal is obtained and the signal-to-noise ratio may be improved.

A representative demodulator for sampling positive and negative peaks is illustrated in FIG. 5A. Demodulator 500 may include AGC 202, clock extractor 204, phase shifters 206_N and 206_P, and samplers 210_N and 210_P. The signals appearing in the demodulator of FIG. 5A are illustrated in the example of FIG. 5B. Signal 516 may be an amplitude-modulated signal having any suitable modulation depth. Signal 518 may be generated using clock extractor 204 as described above. Signals 520_P and 520_N may be generated using phase shifters 206_P and 206_N, respectively. In some embodiments, the two phase shifters may introduce phase shifts that are opposite in sign with respect to each other. For example, phase shifter 206_P may shift the phase of signal 518 by approximately nπ/2, and phase shifter 206_N may shift the phase of signal 518 by approximately mπ/2, where n and m are odd integers having opposite signs. In this manner, the falling edges (or alternatively the rising edges) of signal 520_P are substantially aligned with the positive peaks of signal 516, and the falling edges (or alternatively the rising edges) of signal 520_N are substantially aligned with the negative peaks of signal 516. Signals 522_P and 522_N, which may collectively form a differential signal, are thus obtained.

In some embodiments, sampling positive and negative peaks may be accomplished by doubling the frequency of the sampling signal relative to the case in which only one type of peaks (the positive or the negative) are sampled.

Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including”, “comprising”, “having”, “containing” or “involving” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

The use of “coupled” or “connected” is meant to refer to circuit elements, or signals, that are either directly linked to one another or through intermediate components.

Claims

1. An amplitude demodulator comprising: a clock extractor configured to extract a clock signal from an input signal;a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately ±nπ/2 wherein n is an odd integer;a sampler configured to sample the input signal with a timing controlled by the sampling signal; andan analog-to-digital converter (ADC) coupled to an output of the sampler.

2. The amplitude demodulator of claim 1, wherein the phase shifter is configured to generate the sampling signal by phase-shifting the clock signal by ±nπ/2.

3. The amplitude demodulator of claim 1, wherein the input signal is received from a wireless channel through a winding.

4. The amplitude demodulator of claim 3, wherein the input signal is modulated at a carrier frequency of 13.56 MHz±7 KHz.

5. The amplitude demodulator of claim 1, further comprising a voltage-controlled locking oscillator coupled to the clock extractor.

6. The amplitude demodulator of claim 5, wherein the voltage-controlled locking oscillator is configured to lock to a frequency of the clock signal.

7. The amplitude demodulator of claim 1, wherein the clock extractor comprises a threshold circuit.

8. The amplitude demodulator of claim 1, wherein the phase shifter is a first phase shifter, the sampling signal is a first sampling signal, the timing is a first timing and the sampler is a first sampler, and further comprising a second phase shifter and a second sampler, wherein the second phase shifter is configured to generate a second sampling signal by phase-shifting the clock signal by approximately ±mπ/2 wherein m is an odd integer and wherein n and m have opposite signs, and the sampler is configured to sample the input signal with a second timing controlled by the second sampling signal.

9. The amplitude demodulator of claim 1, further comprising an automatic gain control (AGC) unit coupled to the clock extractor.

10. A method for demodulating an input signal, the method comprising: extracting a clock signal from an input signal;generating a sampling signal by phase-shifting the clock signal by approximately ±nπ/2 wherein n is an odd integer;sampling the input signal with a timing controlled by the sampling signal; anddigitizing the sampled input signal with an analog-to-digital converter (ADC).

11. The method of claim 10, wherein the input signal is received wirelessly.

12. The method of claim 11, wherein the input signal is received through a winding.

13. The method of claim 10, wherein extracting the clock signal from the input signal comprises generating a first value when the input signal is greater than a threshold and generating a second value when the input signal is less than a threshold.

14. The method of claim 10, wherein phase-shifting the clock signal by approximately ±nπ/2 comprises phase-shifting the clock signal by ±nπ/2.

15. The method of claim 10, further comprising locking to a frequency of the clock signal and generating a locked signal having the frequency of the clock signal.

16. The method of claim 15, further comprising sampling the input signal with the locked signal when an amplitude of the input signal is substantially zero throughout at least one cycle.

17. The method of claim 15, wherein the frequency of the clock signal is 13.56 MHz±7 KHz.

18. The method of claim 10, wherein the sampling signal is a first sampling signal and the timing is a first timing, and further comprising: generating a second sampling signal by phase-shifting the clock signal by approximately ±mπ/2 wherein m is an odd integer and wherein n and m have opposite signs; andsampling the input signal with a second timing that is controlled by the second sampling signal.