Burgeoning long-range communications applications, such as satellite communication in the 45 GHz band and high data-rate wireless backhaul in the 71-76 GHz and 81-86 GHz bands, have driven the need for the development of high-power, energy-efficient long-range communication circuitry, such as power amplifiers.
However, existing power amplifier and combiner architectures do not provide a means for compact large-scale power combining in a linear manner to achieve watt-class output powers at mmWave frequencies.
Accordingly, new circuits for power-combined power amplifier arrays are desirable.
Circuits for power-combined power amplifier arrays are provided. In some embodiments, the circuits for power combined-power amplifier arrays comprise: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.
Circuits for power-combined power amplifier arrays are provided. In some embodiments, these circuits include an input splitter that splits an input signal, an array of power amplifier unit cells that each receive the split input signal and provide an output signal, and a non-isolating power combiner that receive the output signals from the power amplifier unit cells and combines these signals so that a single combined output can be provided. In some embodiments, the power amplifier unit cells are selectable so that only m of the total available unit cells are powered on at a given point in time. In some embodiments, the power combiner can include an array of spiral inductors that are each connected to an output of a corresponding power amplifier unit cell on one side the inductor and to an output of the power combiner on the other side of the inductor.
Turning to
As illustrated, circuit 100 includes an input splitter 102, an array of power amplifier unit cells 104, 106, and 108, a non-isolating power combiner 110, switches 112, 114, and 116, a digital signal processor (DSP) 120, and a load resistor 122.
As described above, input splitter 102 splits an input signal so that the input signal can be provided from a single point to the power amplifier unit cells. Input splitter 102 can be implemented in any suitable manner. For example, as described below in connection with
Each of power amplifier unit cells 104, 106, and 108 amplify the signal from the input splitter when the unit cell is turned ON. Whether a unit cells is turned ON or OFF may be controlled by a signal from DSP 120 which controls switches 112, 114, and 116. Any suitable unit cells, any suitable switches, and any suitable DSP can be used. In some embodiments, DSP 120 can also be omitted when not needed and any other suitable mechanism for controlling the switches can be provided.
Power combiner 110 receives the outputs of the ON unit cells, combines the outputs into a single signal, and drives load Rload 122. As described below, in some embodiments, power combiner may be implemented using a set of spiral inductors. Load Rload 122 can be any suitable load in some embodiments.
Turning to
As illustrated, circuit 200 includes an input splitter 202, an array of power amplifier unit cells 204, 206, and 208, a non-isolating power combiner 210, and a load resistor 122.
Input splitter 202 splits an input signal so that the input signal can be provided from a single point to the power amplifier unit cells. Input splitter 202 can be implemented in any suitable manner. For example, as described below in connection with
Each of power amplifier unit cells 204, 206, and 208 amplify the signal from the input splitter.
Power combiner 210 receives the outputs of the unit cells, combines the outputs into a single signal, and drives load Rload 222. As described below, in some embodiments, power combiner may be implemented using a set of spiral inductors. Load Rload 222 can be any suitable load in some embodiments.
Any suitable number of input splitter outputs, power amplifier unit cells, and power combiner inputs can be used in the examples of
As discussed above, in some embodiments and instances, it may be desirable to turn OFF one or more of the power amplifier unit cells, while leaving other of the power amplifier unit cells ON. In order to achieve an output amplitude that is proportional to the number of power amplifier unit cells that are ON (m) (i.e., to achieve Aout α m), the following should be true:
Based, on this, it follows that m·Punit(m) should be proportional to m2,
should be proportional to m2, and Rin(m) should be proportional to
In order to address these and other requirements, as shown in the example of
To achieve an equivalent characteristic impedance Z0 necessary for the combiner to be implemented in CMOS back end of line (BEOL) and to achieve the behavior of a quarter-wave transmission line at the desired frequency ω0, the spiral inductor can be configured to achieve an inductance of L=Z0/ω0 and a parasitic capacitance of Cp=1/(Z0ω0) on either side as seen in box 334 of
The maximum number of elements that can be combined in a single step using the quarter-wave lumped combiner, with given values for Rload and Rin, is limited by the achievable self-resonant frequency (SRF) of spirals in the BEOL and layout considerations for maintaining symmetry. For example, in some embodiments, the maximum number of elements that can be combined can be found to be sixteen when the combiner is implemented in 45 nm SOI CMOS BEOL for Rload=Rin=50Ω for which Z0=200Ω at 45 GHz Although sixteen elements may be found to be the maximum number of elements that can be combined, in some embodiments, fewer elements than that number of elements can be combined. For example, in some embodiments, eight elements can be combined for which the spirals have a Z0=141.42Ω at 45 GHz. In another example, in some embodiments, twelve elements can be combined, which requires a Z0=173.2Ω at 45 GHz.
The efficiency ηcomb of the n-way lumped quarter-wave combiner driving Rload may be expressed as:
where QL is the inductive quality factor of the spiral, QC is the quality factor of the parasitic capacitances of the spiral at ω0, and ρcomb (the ideal impedance transformation performed by the combiner) may be expressed as:
Equation (1) can also be written as follows:
where ρsec equals n·ρcomb and is the impedance transformation performed by each spiral section in the combiner.
Equations (1) and (2) assume that the currents and voltages in an ideal lossless combiner are unaffected by the resistance of the spiral being in series with the inductance of the spiral, and by the resistance of the spiral being in parallel with the capacitances of the spiral.
Based on equation (2), it can be seen that the efficiency of the combiner only depends on QL, QC and ρsec.
An example of the simulated and theoretical efficiencies of two eight-way combiners with QL=12, QC=50 and QL=25, QC=20 at 45 GHz in accordance with some embodiments are shown in
Any suitable arrangement of the lumped quarter-wave sections can be used in some embodiments. For example, as shown in
As described above, in accordance with some embodiments, one or more of the power amplifier unit cells in an array of such cells may be able to be switched OFF. In some of such embodiments, an OFF unit-cell may be configure to present a short-circuit (or near short-circuit) impedance to the corresponding combiner input. This short-circuit can then be transformed by the corresponding lumped quarter-wave section of the combiner to an open at the output of the combiner thus ensuring that no (or minimal) power is dissipated by the section of the combiner corresponding to the OFF cell. Furthermore, each ON unit-cell may see an impedance
which has the desired load modulation effect (Rin(m) α 1/m).
Turning to
The combiner is designed to have Rin(8)=25Ω for Rload=50Ω (ρcomb=2, L=353 pH, Cp=35.4 fF, Z0=100Ω at 45 GHz).
Eight digital control lines (b1 520, b2 522, b3 524, b4 526, b5 528, b6 530, b7 532, and b8 534) determine the ON/OFF state of the unit-cells and thereby determine the power amplifier array's output modulation. The lengths of these digital control lines can be equalized to minimize skew in the digital control word input to the power amplifier array during modulation in some embodiments. As shown in
The eight power amplifier unit-cells receive their input power via two eight-way input power splitters formed from transmission lines 536, 538, 540, 542, 544, 544, 546, and 548, and 550, 552, 554, 556, 558, 560, and 562. As shown, a three-stage design is implemented in which the two stages closest to each power amplifier unit-cell inputs (formed from transmission lines: 542, 544, 546, 548, and 538, 540; and 556, 558, 560, 562, and 552, 554) are designed in a current-splitting fashion and the stage furthest from the unit cell (formed from transmission lines 536 and 550) performs the necessary impedance transformation using a 3λ/4 transmission line. Transmission lines 536 and 550 should be equal in length.
In some embodiments, the OFF resistance of a unit cell (Roff) can be configured to match the equivalent source resistance of the ON power amplifier unit cells (e.g., 15Ω). For example, in some embodiments, this can be done by configuring the bias voltage applied at the drain of transistor M5 (which bias voltage is illustrated in
Turning to
The combiner is designed to have Rin(8)=50Ω for Rload=50Ω (ρcomb=1, L=500 pH, Cp=25 fF, Z0=141.42Ω at 45 GHz). In the combiner of
Unlike circuit 500 of
Like in circuit 500, in circuit 700 the eight power amplifier unit-cells receive their input power via two four-way input power splitters (which together act as one eight-way input power splitter) formed from transmission lines 736, 737, 738, 740, 742, 744, 744, 746, and 748, and 750, 751, 752, 754, 756, 758, 760, and 762. As shown in
The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects.
Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and the numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is only limited by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.
This application claims the benefit of U.S. Provisional Patent Application No. 61/948,198, filed Mar. 5, 2014, which is hereby incorporated by reference herein in its entirety.
This invention was made with government support under grant FA8650-10-1-7042 awarded by the Defense Advanced Research Projects Agency. The government has certain rights in the invention.
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Number | Date | Country | |
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20170040956 A1 | Feb 2017 | US |
Number | Date | Country | |
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61948198 | Mar 2014 | US |