Patent Application
20100302676
The present invention generally relates to controlling head movement and, more particularly, to controlling head movement responsive to a position error signal within a servo control loop.
A typical data storage disk drive includes a plurality of magnetic recording disks which are mounted to a rotatable hub of a spindle motor and rotated at a high speed. An array of read/write heads is disposed adjacent to surfaces of the disks to transfer data between the disks and a host device. The heads can be radially positioned over the disks by a rotary actuator and a closed loop servo system.
The servo system can operate in two primary modes: seeking and track following. During a seek, a selected head is moved from an initial track to a target track on the corresponding disk surface. Upon reaching the target track, the servo system enters the track following mode wherein the head is maintained over the center of the target track while data is written/read. During track following, prerecorded servo burst fields are sensed by the head and demodulated to generate a position error signal (PES), which provides an indication of the position error of the head away from a desired location along the track (e.g., the track center). The PES is then converted into an actuator control signal, which is fed back to a head actuator that positions the head.
As the areal density of magnetic disc drives increases, so does the need for more precise position control when track following, especially in the presence of vibrations which can cause repeatable and non-repeatable runout error in head positioning and variation in disk speed.
In a servo control loop, phase detection between a clock signal and servo burst fields on a movable storage media is carried out with compensation for the effect of phase error and frequency error on servo burst fields.
In some embodiments, a timing circuit detects a preamble phase angle between a clock signal and a preamble signal read from a preamble pattern on a moving storage media. The timing circuit also detects at least one postamble phase angle between the clock signal and a postamble signal read from a postamble pattern following the preamble pattern on the storage media. The timing circuit then determines values for a phase acquisition error and a frequency acquisition error in the preamble phase angle in response to the postamble phase angle.
In some other embodiments, a process for detecting phase and frequency acquisition errors in a preamble pattern on a moving storage media includes detecting a preamble phase angle between a clock signal and a preamble signal read from the preamble pattern. At least one postamble phase angle is detected between the clock signal and a postamble signal read from a postamble pattern following the preamble pattern on the storage media. Values for a phase acquisition error and a frequency acquisition error in the preamble phase angle are determined in response to the postamble phase angle.
In some other embodiments, a servo controller circuit includes a timing circuit and a servo circuit. The timing circuit detects a preamble phase angle between a clock signal and a preamble signal read by a sensor from a preamble pattern on a moving storage media, detects a position signal between the clock signal and a position pattern located after the preamble pattern, and detects at least one postamble phase angle between the clock signal and a postamble signal read from a postamble pattern on the storage media. The servo circuit determines values for a phase acquisition error and a frequency acquisition error remaining after timing acquisition of the preamble phase angle in response to the postamble phase angle, determines a position phase error that represents an effect of the determined phase and frequency acquisition errors on the position signal between the clock signal and the position pattern, adjusts the position signal to compensate for the determined position phase acquisition error, and positions the sensor responsive to the adjusted position signal.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiments of the invention. In the drawings:
Various embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art.
It will be understood that, as used herein, the term “comprising” or “comprises” is open-ended, and includes one or more stated elements, steps and/or functions without precluding one or more unstated elements, steps and/or functions. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term “and/or” and “/” includes any and all combinations of one or more of the associated listed items. In the drawings, the size and relative sizes of regions may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first region/element/value could be termed a second region/element/value, and, similarly, a second region/element/value could be termed a first region/element/value without departing from the teachings of the disclosure.
Some embodiments may be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Consequently, as used herein, the term “signal” may take the form of a continuous waveform and/or discrete value(s), such as digital value(s) in a memory or register. Furthermore, various embodiments may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium that is executable by a processor to perform functionality described herein. Accordingly, as used herein, the terms “circuit” and “module” may take the form of digital circuitry, such as computer-readable program code executed by a processor (e.g., general purpose microprocessor and/or digital signal processor), and/or analog circuitry.
Embodiments are described below with reference to block diagrams and operational flow charts. It is to be understood that the functions/acts noted in the blocks may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Although some of the diagrams include arrows on communication paths to show a primary direction of communication, it is to be understood that communication may occur in the opposite direction to the depicted arrows.
Although various embodiments of the present invention are described in the context of disk drives for purposes of illustration and explanation only, the present invention is not limited thereto. It is to be understood that the present invention can be more broadly used for any type of servo control loop having processors that take turns controlling head positioning by an actuator in response to different defined ones of sequentially occurring spaced apart servo patterns on a media that is moving relative to the head.
Write commands and associated data from a host device 100 are buffered by the data controller 52. The host device 100 can include, but is not limited to, a desktop computer, a laptop computer, a personal digital assistant (PDA), a digital video recorder/player, a digital music recorder/player, and/or another electronic device that can be communicatively coupled to store and retrieve data in the head disk assembly. The data controller 52 carries out buffered write commands by formatting the associated data into blocks with the appropriate header information, and transfers the formatted data via the read/write channel 54 to logical block addresses (LBAs) on a data storage surface of the disk 12 identified by the associated write command.
The read write channel 54 can convert data between the digital signals processed by the data controller 52 and the analog signals conducted through the heads 20. The read write channel 54 provides servo data read from servo sectors 60 on the disk 12 to the servo controller 53. The servo sectors 60 may be configured in a conventional manner that is well known in the art. The servo data can be used to detect the location of a head 20 relative to LBAs on the disk 12. The servo controller 53 can use LBAs from the data controller 52 and the servo data to seek a head 20 to an addressed track 62 and block on the disk 12 (i.e., seek mode), and to maintain the head 20 aligned with the track 62 while data is written/read on the disk 12 (i.e., track following mode).
As the head 20 moves through the servo burst pattern of
However, timing acquisition errors exist due to, for example, the effects of external disturbances, disk runout (e.g., eccentric tracks), and/or spindle motor speed variation that cause variation in the associated timing of the servo burst field components of the associated readback signals. Consequently, at the end of the preamble pattern, a phase acquisition error θi and a frequency acquisition error Δf are typically present after timing recovery is finished at the end of the preamble.
In accordance with some embodiments, a frequency and phase compensated PES module 320, which may at least partially reside in the servo controller 53 as shown in
Referring to
An illustrated disturbance 340 (D) imparts a first disturbance component 342 (e.g., vibration) that moves the head relative to a disk track, and imparts a second disturbance component 344 that moves the disk relative to the head. The second disturbance component 344 may result in, for example, disk speed variations that occur relative to the head due to disk runout (repeatable/non-repeatable runout) from eccentric disk track rotation and/or spindle motor speed variations.
The servo burst fields sensed by the head relative to a given track form components of a read signal 310 that is input to a frequency and phase acquisition compensated PES module 320. The module 320 can include a servo ID detector 322, a window and timing signal generator 324, a PES computation module 326, a filter 330, a frequency and phase acquisition error correction module 332, and a crystal (servo) clock 334. The servo ID detector 322 and the window and timing signal generator 324 trigger operation of the PES computation module 326 and the frequency compensated PES computation module 320 in response to detecting presence of the preamble and subsequent servo burst field components in the read signal 310. The read signal 310 is filtered by a filter 330 and input to the PES computation module 326 and then to a frequency and phase acquisition error correction module 332. Although various separate elements have been illustrated for the frequency and phase compensated PES module 320 for ease of explanation, it is to be understood that their functionality described herein may be combined into more or less elements.
The PES computation module 326 detects the preamble phase angle θ between the clock signal from the clock 334 and the preamble signal component of the readback signal 310, detects a first position pattern phase angle between the clock signal and the first position signal PS1, detects a second position pattern phase angle between the clock signal and the second position signal PS2, detects a first postamble phase angle θPA1 between the clock signal and the first postamble signal component, and detects a second postamble phase angle θPA2 between the clock signal and the second postamble signal component. The external disturbance 340 causes variation in the associated timing of the servo burst field components in the readback signal 310 and result in a phase acquisition error θi and a frequency acquisition error Δf at the end of the preamble pattern.
The frequency and phase acquisition error correction module 332 then uses the relative timing between the first and second postamble phase angles θPA1 and θPA2 to determine values for the phase acquisition error θi and for the frequency acquisition error Δf in the preamble phase angle θ. The module 332 can then determine the position of the head 20 relative to the first and second position patterns (PS1 and PS2) while compensating for the determined values for the phase acquisition error θi and for the frequency acquisition error Δf, which may improve the accuracy with which the head 20 is positioned relative to the servo burst patterns in the servo sectors 60.
The frequency and phase acquisition error compensated PES components are combined with a reference position 412 (desired position) for the head to generate a PES 314. The PES 314 is therefore indicative of the difference between the actual and desired positions of the head (i.e., head position error), and is provided to a servo control module 316. The servo control module 316 responds (e.g., with a transfer gain K) to the value of PES 314 to generate a servo control signal 318.
The servo control signal 318 can be converted by a DAC/power amplifier 302 into an analog signal, assuming it was a digital signal, and then amplified and provided to a head actuator motor 304. The head actuator motor 304 is connected to an actuator 306 which moves an actuator arm 308 in response to the amplified control signal supplied to the head actuator motor 304. The head is connected to the actuator arm 308 (e.g., to an end of the actuator arm 308).
In this way, the servo control loop controls the positioning of the head relative to a selected track on the disk surface during reading/writing of data along the selected track. Moreover, because the frequency and phase acquisition error compensation module 332 generates PES components that have been adjusted to at least partially remove effects of frequency and phase error on the servo burst signals in the read signal 310, the servo control loop may be able to more accurately control positioning of the head relative to a track in presence of increased data storage densities and/or disturbances.
Exemplary operations that may be carried out by the frequency and phase acquisition error correction module 332 and/or the PES computation module 326 to determine the phase acquisition error θi and the frequency acquisition error Δf and to compensate the head positioning responsive thereto are described below with regard to
When there are no errors in the timing acquired by the PES computation module 326 between the servo clock 334 and the preamble, the phase acquisition error θi is zero and the frequency acquisition error is zero. In such a case, for a NULL servo pattern, a first position pattern phase angle error θPS1, a second position pattern phase angle error θPS2 the first postamble phase angle θPA1, the and second postamble phase angles θPA2 are all zero (assuming Postamble fields are written at the same frequency and in phase with the preamble field). Conversely, when the phase acquisition error θi and/or the frequency acquisition error Δf are not zero, the first position pattern phase angle error θPS1, the second position pattern phase angle error θPS2 the first postamble phase angle θPA1 and the second postamble phase angles θPA2 are nonzero and can be used by the frequency and phase acquisition error correction module 332 to determine the phase acquisition error θi and the frequency acquisition error Δf.
The first and second postamble phase angles θPA1 and θPA2 can depend on the phase acquisition error θi, the frequency acquisition error Δf in the preamble, and the number of servo clock cycles occurring in the readback signal 310 between the preamble pattern and the second postamble pattern, as represented by the following equations:
θPA1=θi+Δf(NSAM+NGC+NPS1+NPS2+NPA1/2), and
θPA2=θi+Δf(NSAM+NGC+NPS1+NPS2+NPA1+NPA2/2)
For these two equations, the PES computation module 326 detects the first and second postamble phase angles θPA1 and θPA2 and the number of servo clock cycles in the servo address mark pattern SAM, the gray code pattern GC, the first position pattern (PS1), the second position pattern (PS2), the first postamble pattern, and the second postamble pattern are each known. Accordingly, only the phase acquisition error θi and the frequency acquisition error Δf are unknown in these two equations and can therefore be determined (i.e., solving two equations having two unknowns).
In particular, the frequency acquisition error Δf in the preamble can be determined from a ratio between 1) a difference between the first and second postamble phase angles θPA1 and θPA2 and 2) the number of servo clock cycles occurring in the readback signal 310 between the first and second postamble patterns, as represented by the following equation:
Δf=(θPA2−θPA1)/(NPA1/2+NPA2/2).
The phase acquisition error θi in the preamble can be determined from a difference between the first postamble phase angle θPA1 and a product of the frequency acquisition error Δf and the number of servo clock cycles between the preamble and the end of the second postamble pattern, as represented by the following equation:
θi=θPA1−Δf(NSAM+NGC+NPS1+NPS2+NPA1/2).
Using the above determined frequency acquisition error Δf and phase acquisition error θi in the preamble phase angle, the frequency and phase acquisition error correction module 332 can determine a first position pattern phase angle error θPS1 that represents an effect of the determined phase θi and frequency acquisition errors Δf on the acquired first position pattern phase angle PS1 between the clock signal and the first position pattern, and can similarly determine a second position pattern phase angle error θPS2 that represents an effect of the determined phase θi and frequency acquisition errors Δf on the acquired second position pattern phase angle PS2 between the clock signal and the second position pattern. The first position pattern phase angle error θPS1 can be determined based on the equation
θPS1=θi+Δf(NSAM+NGC+NPS1/2),
and the second position pattern phase angle error θPS2 can be determined based on the equation
θPS2=θi+Δf(NSAM+NGC+NPS1+NPS2/2).
After determining the first and second position pattern phase angle errors θPS1 and θPS2, the frequency and phase acquisition error correction module 332 modify the first and second position pattern phase angles (between the servo clock and PS1 and PS2) to compensate for the determined timing acquisition errors to generate corrected sine components {tilde over (S)}1 and {tilde over (S)}2 of the first and second position patterns phase angles (between the servo clock and PS1 and PS2), and to generate corrected cosine components {tilde over (C)}1 and {tilde over (C)}2 of the first and second position patterns phase angles. As explained above, these exemplary equations may be modified based on the teachings herein to compensate for other types of servo patterns, such as for servo patterns other than NULL patterns.
The frequency and phase acquisition error correction module 332 may determine the first position pattern phase error θPS1 based on adding a value of the phase acquisition error θi to a value of the frequency acquisition error Δf that is multiplied by a number of cycles occurring in the readback signal 310 from the head 20 reading a portion of the servo burst pattern including between the preamble pattern and the first postamble pattern, and may determine determines the second position pattern phase error θPS2 based on adding a value of the phase acquisition error θi to a value of the frequency acquisition error Δf that is multiplied by a number of cycles occurring in the readback signal 310 from the head 20 reading a portion of the servo burst pattern including between the preamble signal and the second postamble pattern.
It is to be understood that the servo null pattern is used for simplicity of explanation without limitation to the invention. The embodiments herein may be applied to any servo pattern.
In some embodiments, the frequency and phase acquisition error correction module 332 can determine the corrected sine {tilde over (S)}1 and cosine {tilde over (C)}1 components of the first position patterns phase angle based on the equation
and can determine the corrected sine {tilde over (S)}9 and cosine {tilde over (C)}2 components of the second position patterns phase angle based on the equation
The servo controller 53 can then control positioning of the head 20 during track following and/or seeking in response to the corrected sine {tilde over (S)}1, {tilde over (S)}2 and cosine {tilde over (C)}1, {tilde over (C)}2 components of the first and second position pattern phase angles (between the servo clock and PS1 and PS2).
The frequency and phase acquisition error correction module 332 may combine the corrected sine {tilde over (S)}1 and cosine {tilde over (C)}1 components of the first position pattern PS1 to generate a first position value, similarly combine the corrected sine {tilde over (S)}2 and cosine {tilde over (C)}2 components of the second position pattern PS2 to generate a second position value, and generate a sensed head position value based on a ratio of the first and second position values.
The sensed head position value can be combined with a position reference signal 312 to generate a position error signal PES that can be provided to the servo control module 316. The position error signal PES is therefore indicative of the difference between the sensed and desired positions of the head (i.e., head position error). The servo control module 316 responds to the value of the position error signal PES to generate an actuator control signal that is converted by a digital-to-analog (DAC)/power amplifier 302 into an analog signal that regulates movement of the head actuator motor 304. As described above with regard to
The position reference signal 312 may be a constant, such as zero, during a track following operation and may be varied through a range of values over time according to a defined profile to provide a desired seek profile during a seek operation.
Although exemplary embodiments have been described that use at least two postamble patterns to determine the phase and frequency acquisition errors θi and Δf in some other embodiments, the servo controller 52 can be configured to determine the phase acquisition error θi using the readback signal from the preamble pattern. For example, the PES computation module 326 may be configured to detect timing between the servo clock signal and the preamble pattern using a phase detection module.
The servo controller 52 can then use the determined phase acquisition error θi from the preamble and a phase angle between the servo clock signal and the readback signal from a single postamble pattern to determine the frequency acquisition error Δf in the preamble. The frequency acquisition error Δf may be determined based on a ratio of 1) a difference between the preamble phase angle and the postamble phase angle to 2) a number of cycles occurring in the readback signal from the preamble pattern and the postamble pattern. The phase acquisition error θi from the preamble may be determined based on a difference between a value of the preamble timing and a value of the determined frequency error multiplied by a number of cycles occurring in the readback signal from the preamble pattern and the postamble pattern.
Accordingly, when the servo controller 52 is configured to determine the phase acquisition error θi using the readback signal from the preamble pattern, the frequency acquisition error Δf of the preamble can then be determined using a single postamble pattern, although more than one postamble pattern may be used and which may increase the accuracy of the determined preamble phase acquisition error θi and/or frequency acquisition error Δf.
Once θi and Δf are determined, the phase errors corresponding to the burst fields can be determined using the exemplary equations describe above. Once the phase errors for each burst field are determined, the burst signal can be compensated as described above for compensation of a NULL pattern. For other servo burst patterns, the equations may be modified based on the teachings herein.
The particular equations in the above exemplary operations may change as a function of the radial location of the head, skew angle of the head, and/or other head to disk interface characteristics. Therefore, in some embodiment, a regression technique may be used to compute the equation coefficients at different radial locations across the disk and/or at different skew angles. The equation coefficients may be stored in a lookup table and/or a parametric equation for reference during operation of the disk drive.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
