Circular register arrays of a computer

Abstract

A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram depicting a general layout of a stack computer;

FIG. 2 is a data stack according to the present invention;

FIG. 3 is a more detailed view of a single register of a stack;

FIG. 4 is a return stack according to the present invention;

FIG. 5 is a diagrammatic view of a computer array, according to the present invention; and

FIG. 6 is a detailed diagram showing a subset of the computers of FIG. 5 and a more detailed view of the interconnecting data buses of FIG. 5.

Claims

1. A stack computer processor, comprising: a data stack, comprising at least one data register; anda return stack, comprising at least one return register; wherein:each of said data stack and said return stack can accommodate an 18 bit instruction word.

2. The processor of claim 1, wherein said at least one data register comprises a top of stack (T) register.

3. The processor of claim 2, wherein said at least one data register further comprises a second position on the stack (S) register.

4. The processor of claim 1, wherein said at least one return register comprises a top register (R).

5. The processor of claim 1, wherein said data stack further comprises an array of hardware registers.

6. The processor of claim 1, wherein said return stack further comprises an array of hardware registers.

7. The processor of claim 5, wherein said array functions in a circular pattern.

8. The processor of claim 6, wherein said array functions in a circular pattern.

9. A method of manipulating a computer processor, comprising: inputting a plurality of instruction words into a corresponding plurality of instruction cells of said processor; andprocessing said plurality of instruction words, wherein:there is no overflow or underflow of instructions as a result of said inputting and said processing.

10. The method of claim 9, wherein said inputting comprises filling all available instruction cells.

11. The method of claim 10, wherein said inputting further comprises inputting additional instruction words after all available instruction cells have been filled.

12. The method of claim 11, wherein said inputting and said processing occur without using a software implemented pointer.

13. The method of claim 9, wherein said processing comprises repeatedly reusing said plurality of instruction words without reloading said plurality of instruction words.

14. A computer processor, comprising: an array of registers; anda shift register, wherein:said shift register comprises a plurality of one bit shift registers which are interconnected by electrical wires, and wherein said plurality of one bit shift registers is equal in number to a number of registers in said array of registers.

15. The processor of claim 14, further comprising at least one register positioned above said array of registers.

16. The processor of claim 14, wherein said array of registers further comprises a read bus and a write bus interconnecting said array.

17. The processor of claim 14, wherein said array of registers functions in a circular pattern.

18. The processor of claim 14, wherein said array of registers are stacked.

19. The processor of claim 18, wherein said one bit shift registers are interconnected by said electrical wires in an alternating pattern.

20. The processor of claim 14, wherein said processor is a data stack.

21. The processor of claim 20, wherein said array of registers comprises eight data registers.

22. The processor of claim 20, wherein said array of registers comprises a multiple of four data registers.

23. The processor of claim 14, wherein said processor is a return stack.

24. The processor of claim 23, wherein said array of registers comprises eight return registers.

25. The processor of claim 23, wherein said array of registers comprises a multiple of four return registers.

26. A computer processor, comprising: an array of registers; anda bidirectional shift register hardwired to said array of registers, further comprising a plurality of one bit shift registers which are interconnected by electrical wires, and wherein said plurality of one bit shift registers is equal in number to a number of registers in said array of registers.

27. The processor of claim 26, further comprising at least one register positioned above said array of registers.

28. The processor of claim 26, wherein said shift register functions as a hardware pointer to said array of registers.

29. The processor of claim 26, further comprising a read bus and a write bus.

30. The processor of claim 26, wherein each of said plurality of one bit shift registers corresponds to an associated register of said array of registers.

31. The processor of claim 30, wherein only one shift register of said plurality of one bit shift registers is activated at one time.

32. The processor of claim 26, wherein said array of registers further comprises a read bus and a write bus interconnecting said array.

33. The processor of claim 26, wherein said plurality of one bit shift registers are interconnected by electrical wires such that a size of a driver and buffering are minimized.

34. The processor of claim 26, wherein all of said electrical wires extend between a maximum of three adjacent one bit shift registers.

35. The processor of claim 34, wherein said array of registers comprises eight registers.

36. The processor of claim 26, wherein said processor is a data stack.

37. The processor of claim 26, wherein said processor is a return stack.