This patent application is a continuation-in-part patent application of U.S. patent application Ser. No. 09/713,702, filed Nov. 15, 2000, entitled INTERCONNECT MECHANICS FOR ELECTROMAGNETIC COUPLER, which is a continuation in part patent application of U.S. patent application Ser. No. 09/318,287, filed May. 25, 1999, entitled HIGH-SPEED SPEED DIGITAL DISTRIBUTION SYSTEM.
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Entry |
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U.S. patent application No. 09/318,287, filed May 25, 1999, entitled High-Speed Digital Distribution System, by Thomas F. Knight, Jr. and Nandu J. Marketkar. |
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Osaka, Hideki, High Performance Memory Interface for DDR-SDRAM II: XTL (Crosstalk Transfer Logic), Hitachi Ltd., Systems Development Laboratory, pp. 1-20 (Sep. 15, 2000). |
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XTL Evaluation System, Hitachi Ltd., Systems Development Laboratory, pp. 1-14 (Sep. 15, 2000). |
Yang, Chih-Kong Ken, et al., “A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, pp. 713-722 (May 1998). |
U.S. patent application No. 09/713,702, filed Nov. 15, 2000, entitled Interconnect Mechanics for Electromagnetic Coupler, by Nandu J. Marketkar, Thomas F. Knight, Jr., John R. Benham, Mark E. Naylor and John L. Critchlow. |
U.S. patent application No. 09/751,527, filed Dec. 29, 2000, entitled Electromagnetic Coupler Socket, by Nandu J. Marketkar, Thomas F. Knight, Jr., Mark E. Naylor and John L. Critchlow. |
U.S. patent application No. 09/751,526, filed Dec. 29, 2000, entitled Electromagnetic Coupler Alignment, by Nandu J. Marketkar and Thomas F. Knight, Jr. |
Number | Date | Country | |
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Parent | 09/713702 | Nov 2000 | US |
Child | 09/751442 | US | |
Parent | 09/318287 | May 1999 | US |
Child | 09/713702 | US |