Claims
- 1. A method of class network routing in a network to allow a compute processor in a network of compute processors located at nodes of the network to multicast a message to a plurality of other compute processors in the network comprising:
dividing a message into one or more message packets which pass through the network; adding a class value to a message packet; at each switch in the network, using the class value as an index to at least one table whose stored values, or as an input to an algorithm whose generated values, determine actions performed by the switch on the message packet.
- 2. The method of claim 1, including providing a class value determining a switch action of path-based multidrop message passing for multiphase multicasting of a message packet through the network, to determine if a local node should deposit a copy of the message packet at the local node.
- 3. The method of claim 2, including:
providing a class-value to implement multidrop message passing; providing each switch with a table to determine if a copy of the message packet is to be deposited at the local node.
- 4. The method of claim 1, including providing a class value determining a switch action of multidestination message passing of a message packet to multiple destination nodes in the network.
- 5. The method of claim 1, wherein a switch duplicates an incoming packet onto multiple outgoing links.
- 6. The method of claim 5, including providing a class routing table with different values on different incoming links.
- 7. The method of claim 4, wherein the message packet is multicast to an entire row or surface of the network.
- 8. The method of claim 1, including:
performing dense matrix inversion algorithms on a network of distributed memory parallel computers with hardware class function multicast capability, wherein the hardware class function multicast capability simultaneously stores into memory a message packet that arrives and immediately sends the message packet to one or more other nodes while that message packet is being stored into memory, such that the communication patterns of the dense matrix inversion algorithms are served by the hardware class function multicast capability to minimize communication delays.
- 9. The method of claim 1, wherein the network comprises a network of distributed-memory parallel computers;
providing each node of the computer network with one or more processors that operate on local memory; coordinating the actions of multiple nodes of the computer by using class routing to pass messages between the multiple nodes.
- 10. The method of claim 9, including:
pairing each node with a switch of the network; connecting the switches to form a three dimensional torus wherein each switch is linked to six other switches, the links are coupled to a switch in a positive direction and also to a switch in a negative direction in each of the three dimensions; identifying each; switch by an x, y, z logical address on the torus, wherein each node has the address of its switch; including a field value for the logical address in the packet header, to enable the packet to identify a destination node.
- 11. The method of claim 1, including using a D-phase multicast from an origin node to all nodes of a D-dimensional cube wherein, in a first phase the origin node sends a multidrop message to all other nodes in one of the rows of the sending node, in a second phase each of the recipients of the first phase and the sender of the first phase simultaneously send a multidrop message to all other nodes in a row orthogonal to the row of the first phase, in a third phase each of the recipients of the second phase and the senders of the second phase simultaneously send a multidrop message to all other nodes in a row orthogonal to the rows of the first and second phases, and so on in further phases such that all node of the cube receive the broadcast message after all the phases.
- 12. The method of claim 1, including providing each switch with a table with associated class values which determine if a copy of a message packet is to be deposited at a destination node.
- 13. The method of claim 1, for a D-dimensional network, including providing 2{circumflex over ( )}D class values for multicast in each of the 2{circumflex over ( )}D directions to allow each node in the network to use 2{circumflex over ( )}D multicasts to effectively broadcast a packet to all other nodes in the mesh.
- 14. The method of claim 1, including providing a class value determining a switch action of a unicast of a message packet through the network to a single destination node.
- 15. The method of claim 1, including providing a class value to enable a node to acquire and store information packets passing through its switch to provide information on the performance of the network.
- 16. The method of claim 11, including providing class values to determine if a copy of the message packet is to go out on an X link or not, and out on a Y link or not, and out on a Z link or not and so on for the other links of the D dimensions.
- 17. The method of claim 1, including providing different tables and providing priorities for different tables to enable a switch to decide between conflicting actions indicated by different tables.
- 18. The method of claim 1, including using a class value as an input to an algorithm for determining a switch action of the switch.
- 19. The method of claim 1, including using class-based multicasting to create other classes, such that the contents of a table for a particular class value is determined by using another class value.
CROSS-REFERENCE
[0001] The present invention claims the benefit of commonly-owned, co-pending US. Provisional Patent Application Serial No. 60/271,124 filed Feb. 24, 2001 entitled MASSIVELY PARALLEL SUPERCOMPUTER, the whole contents and disclosure of which is expressly incorporated by reference herein as if fully set forth herein. This patent application is additionally related to the following commonly-owned, co-pending United States Patent Applications filed on even date herewith, the entire contents and disclosure of each of which is expressly incorporated by reference herein as if fully set forth herein. U.S. patent application Ser. No. (YOR920020027US1, YOR920020044US1 (15270)), for “Class Networking Routing”; U.S. patent application Ser. No. (YOR920020028US1 (15271)), for “A Global Tree Network for Computing Structures”; U.S. patent application Ser. No. (YOR920020029US1 (15272)), for ‘Global Interrupt and Barrier Networks”; U.S. patent application Ser. No. (YOR920020030US1 (15273)), for ‘Optimized Scalable Network Switch”; U.S. patent application Ser. No. (YOR920020031US1, YOR920020032US1 (15258)), for “Arithmetic Functions in Torus and Tree Networks’; U.S. patent application Ser. No. (YOR920020033US1, YOR920020034US1 (15259)), for ‘Data Capture Technique for High Speed Signaling”; U.S. patent application Ser. No. (YOR920020035US1 (15260)), for ‘Managing Coherence Via Put/Get Windows’; U.S. patent application Ser. No. (YOR920020036US1, YOR920020037US1 (15261)), for “Low Latency Memory Access And Synchronization”; U.S. patent application Ser. No. (YOR920020038US1 (15276), for ‘Twin-Tailed Fail-Over for Fileservers Maintaining Full Performance in the Presence of Failure”; U.S. patent application Ser. No. (YOR920020039US1 (15277)), for “Fault Isolation Through No-Overhead Link Level Checksums’; U.S. patent application Ser. No. (YOR920020040US1 (15278)), for “Ethernet Addressing Via Physical Location for Massively Parallel Systems”; U.S. patent application Ser. No. (YOR920020041US1 (15274)), for “Fault Tolerance in a Supercomputer Through Dynamic Repartitioning”; U.S. patent application Ser. No. (YOR920020042US1 (15279)), for “Checkpointing Filesystem”; U.S. patent application Ser. No. (YOR920020043US1 (15262)), for “Efficient Implementation of Multidimensional Fast Fourier Transform on a Distributed-Memory Parallel Multi-Node Computer”; U.S. patent application Ser. No. (YOR9-20010211US2 (15275)), for “A Novel Massively Parallel Supercomputer”; and U.S. patent application Ser. No. (YOR920020045US1(15263)), for “Smart Fan Modules and System“.
PCT Information
Filing Document |
Filing Date |
Country |
Kind |
PCT/US02/05573 |
2/25/2002 |
WO |
|