This invention broadly relates to computing machines and computers. This invention also demonstrates embodiments of this new computer that compute cryptographic machines and hence protect the privacy of information and also protect the execution of the computation.
The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also be inventions
Physical implementations of digital computers began in the latter half of the 1930's and early designs were based on various implementations of logic gates [1, 7, 30, 35, 36] (e.g., mechanical switches, electro-mechanical devices, vacuum tubes). The transistor was conceptually invented [21, 22] in the late 1920's, but the first working prototype [3, 27] was not demonstrated until 1947. Transistors act as building blocks for logic gates when they operate above threshold [23] (page 39). When a transistor operates above threshold, it essentially acts as a switch which has two states on or off. The transistor enabled the invention of the integrated circuit [18, 26], which is the physical basis for modern digital computers [16, 17].
This invention presents and describes a new computational machine, called a clock machine, that is a novel alternative to computing machines (computers) based on logic gates [28, 31]. This invention describes how to perform computation using one or more clock machines. In some embodiments, the number of time states of a clock is a prime number. For example, as shown in
In some alternative embodiments, a clock machine may have a composite number of time states. For example, a clock machine may have a number of time states that is a power of 2 even though 2n when n>1 is not prime. For example, 128 time states is 28 and 65536 time states is 216 and 18446744073709551616 time states is 264. The invention described herein combines a finite collection of clock machines to construct a clock computing machine. In some embodiments, clock computing machines may be constructed without using gates or switches.
In some embodiments, a new computational machine (computer) is invented based on the prime numbers and clocks. Consider the prime number 2 and the clock machine [2, 0]. The 2 means that the clock machine has two states {0, 1} and the 0 means that the clock machine starts ticking from time state 0 at time 0. At the next moment of time (i.e., at time 1), clock machine [2, 0] moves to time state 1 and then back to time state 0. Thus, the clock machine [2, 0] ticks 0, 1, 0, 1, and so on. Prime clock [2, 0] machine 102 is shown in
Expressed as the ⊕ operator machine in
A collection of clock machines generate a commutative group, whereby the associative and commutative properties of prime clock sums enable clock machines to perform a computation in parallel. This simple mathematical property has significance because gates do not preserve the associative property. For example, ¬(x∧y)≠(¬x)∧y, where operator ¬ represents a NOT gate and ∧ represents an OR gate because ¬(0∧0)=1 while (¬0)∧0=0. In practice, this means that the OR gate computation ∧ must be performed either before the negation (NOT gate) is applied or after the negation is applied. This means the computation with gates is inherently a serial computation.
In an embodiment, this specification describes how to implement an arbitrary Boolean function with a finite collection of clock machines. As the computation of a digital computer can computed by one or more Boolean functions, the specification describes a new computer based on clocks instead of gates.
In an embodiment, this specification shows how to implement the a cryptographic cipher Midori with only a few prime clock machines. Using the first 8 prime numbers, the Midori cipher is executed with random prime clock machines so that a physical instantiation on each processor chip is unique. In some embodiments, each execution of a cryptographic cipher may have a unique physical instantiation in terms of the clock machine instructions that are executing the cryptographic cipher.
The uniqueness of the physical instantiation follows a biological principle whereby a population that exhibits diversity can be far more challenging for predators or a sentient manipulator of that population. As an example, bacteria organisms are typically able to develop antiobiotic resistance due at least in part to the fact that each bacteria organism of the same species is still unique in the enzymes (proteins) it can build in order to help disable an antibiotic. As another example of population diversity, the variability of the retrovirus (in particular, AIDS) and its ability to quickly evolve has made it far more difficult for scientists to construct a comprehensive vaccine for the AIDS virus.
By using a different set of clock machines to execute the same procedure, each execution of a procedure looks different to the hacker, who may be attempting to reverse engineer the procedure. In the cybersecurity world, digital computer programs are typically compiled to a sequence of machine instructions so that the sequence of machine instructions are identical on two different instances of the same computer chip. In order for a hacker to infect a computer with malware, it is much easier for the hacker to accomplish this when the sequence of machine instructions are identical or similar on two different instances of a chip or virtual machine. This weakness in current computing systems creates huge vulnerabilities in our Internet infrastructure.
In the recent Mirai attack, malware was able to shut down most of the Internet on the East coast for a substantial part of the day [24]. The Mirai attack and other recent cyber attacks have triggered an urgent alarm that developing new machines, methods and procedures resistant to malware infection is a critical issue for industry and for U.S. infrastructure such as air traffic control, the electrical grid and the Internet.
The uniqueness of the random clock machines helps obfuscate the execution of the cryptographic algorithm and helps break up potential timing patterns in the execution of the cipher. Based on extensive mathematical analysis and computational experiments and tests, the clock computing machines have promising capabilities, particularly for highly nonlinear Boolean functions that are desired in cryptography.
The clock machines, described herein, have an important mathematical property that has practical utility. Covered in section 6.15, theorem 8 states: for every natural number n, every Boolean function ƒ: {0, 1}n→{0, 1} can be computed with a finite prime clock sum machine that lies inside an infinite abelian group (, ⊕). Overall, prime clock machines can act as computational building blocks for clock computing machines—instead of gates [31, 28] used in the prior art. Adding is computationally fast and easy to build in hardware. Another favorable computing property is that prime clock machine addition ⊕ is associative and commutative.
These two group properties enable prime clock machines to compute in parallel, while computers built from gates do not have this favorable property. For example, ¬(x∧y)≠(¬x)∧y because ¬(0∧0)=1 while (¬0)∧0=0. In the prior art, the unary gate—and the binary gates A, V form a Boolean algebra [14], so circuits built from gates must have a depth. This means that the gate-based computers used in the prior art have physical and mathematical limitations on the extent to which the prior art gate-based computers can be parallelized.
To better understand the disparity between the parallelization of prime clock sums versus the circuit depth of gates, consider the prime clock sum [7, 3]⊕[13, 6]. A [7, 3] prime clock and a [13, 6] prime clock are shown in
This disparity is further exacerbated for bit strings x0x1 . . . xn-1 of length n (i.e., x0x1 . . . xn-1 lies in {0, 1}n) as n increases. Informally Shannon's theorem [28] implies that most functions ƒ: {0, 1}n→{0, 1}require on the order of
gates. More precisely, let β(⊕, n) be the number of distinct functions ƒ: {0, 1}n→{0, 1} that can be computed by circuits with at most
gates built from the NOT, AND, and OR gates. Shannon's theorem states for any ϵ>0, then
Let the gates of a circuit be labeled as {g1, g2, . . . , gm} where m is about
The graph connectivity of the circuit specifies that the output of gate g1 connects to the input of gate gk
Even small prime numbers can help construct a huge number of Boolean functions. Using the first 559 prime numbers, finite prime clock sum machines, (i.e., all primes≤4051, where 4051 can be represented with 12 bits) can compute any function ƒ20: {0, 1}20→{0, 1}, even though there are 22
Suppose a cryptographic application requires a function g: {0, 1}20→{0, 1}20, where g=(g0, g1, . . . , g19). For some functions, in the prior art, more than 1 million gates could be required to directly implement g in hardware, since
Boolean functions with good crytographic properties are highly nonlinear [10], so they usually require about
gates. In our experimental computational tests, we observe that random prime clock machines which compute the Midori64 S-box S0 and the Midoril28 S-box S1 have average complexity (definition 4) slightly larger than the affine functions Aa
In the following figures, although they may depict various examples of the invention, the invention is not limited to the examples depicted in the figures.
In this specification, the term “location” may refer to geographic locations and/or storage locations. A particular storage location may be a collection of contiguous and/or noncontiguous locations on one or more machine readable media. Two different storage locations may refer to two different sets of locations on one or more machine-readable media in which the locations of one set may be intermingled with the locations of the other set.
In this specification, the term “machine-readable medium” refers to any non-transitory medium capable of carrying or conveying information that is readable by a machine. One example of a machine-readable medium is a computer-readable medium. Another example of a machine-readable medium is paper having holes that are detected that trigger different mechanical, electrical, and/or logic responses. The term machine-readable medium also includes media that carry information while the information is in transit from one location to another, such as copper wire and/or optical fiber and/or the atmosphere and/or outer space.
In this specification, the term “process” refers to a series of one or more operations. In an embodiment, “process” may also include operations or effects that are best described as non-deterministic. In an embodiment, “process” may include some operations that can be executed by a digital computer program and some physical effects that are non-deterministic, which cannot be executed by a digital computer program and cannot be performed by a finite sequence of processor instructions.
In this specification, the term “procedure” refers to a sequence of one or more instructions, executed by a machine. A procedure typically is executed by a finite machine that executes a finite number of instructions with finite memory.
In this specification, machine-implemented procedures and processes execute algorithms and combine non-deterministic processes with a machine. The formal notion of “algorithm” was introduced in Turing's work [29] and refers to a finite machine that executes a finite number of instructions with finite memory. In other words, an algorithm can be executed with a finite number of machine instructions on a processor. “Algorithm” is a deterministic process in the following sense: if the finite machine is completely known and the input to the machine is known, then the future behavior of the machine can be determined. In contrast, there is hardware that can measure quantum effects from photons (or other physically non-deterministic processes), whose physical process is non-deterministic. The recognition of non-determinism produced by quantum randomness and other quantum embodiments is based on decades of experimental evidence and statistical testing. Furthermore, the quantum theory—derived from the Kochen-Specker theorem and its extensions [19, 8]—predicts that the outcome of a quantum measurement cannot be known in advance and cannot be generated by a Turing machine (digital computer program). As a consequence, a physically non-deterministic process cannot be generated by an algorithm: namely, a sequence of operations executed by a digital computer program.
Some examples of physically non-deterministic processes are as follows. In some embodiments that utilize non-determinism, photons strike a semitransparent mirror and can take two or more paths in space. In one embodiment, if the photon is reflected by the semitransparent mirror, then it takes on one bit value b∈{0, 1}; if the photon passes through by the semitransparent mirror, then the non-deterministic process produces another bit value 1-b. In another embodiment, the spin of an electron may be sampled to generate the next non-deterministic bit. In still another embodiment, a protein, composed of amino acids, spanning a cell membrane or artificial membrane, that has two or more conformations can be used to detect non-determinism: the protein conformation sampled may be used to generate a non-deterministic value in {0, . . . n−1} where the protein has n distinct conformations. In an alternative embodiment, one or more rhodopsin proteins could be used to detect the arrival times of photons and the differences of arrival times could generate non-deterministic bits. In some embodiments, a Geiger counter may be used to sample non-determinism.
In this specification, the term “photodetector” refers to any type of device or physical object that detects or absorbs photons. A photodiode is an embodiment of a photodetector. A phototransistor is an embodiment of a photodetector. A rhodopsin protein is an embodiment of a photodetector.
The emission times of the photons emitted by the LED experimentally obey the energy-time form of the Heisenberg uncertainty principle. The energy-time form of the Heisenberg uncertainty principle contributes to the non-determinism of non-deterministic process 542 or 552 because the photon emission times are unpredictable due to the uncertainty principle. In
In
A photodiode is a semiconductor device that converts light (photons) into electrical current, which is called a photocurrent. The photocurrent is generated when photons are absorbed in the photodiode. Photodiodes are similar to standard semiconductor diodes except that they may be either exposed or packaged with a window or optical fiber connection to allow light (photons) to reach the sensitive part of the device. A photodiode may use a PIN junction or a p-n junction to generate electrical current from the absorption of photons. In some embodiments, the photodiode may be a phototransistor.
A phototransistor is a semiconductor device comprised of three electrodes that are part of a bipolar junction transistor. Light or ultraviolet light activates this bipolar junction transistor. Illumination of the base generates carriers which supply the base signal while the base electrode is left floating. The emitter junction constitutes a diode, and transistor action amplifies the incident light inducing a signal current.
When one or more photons with high enough energy strikes the photodiode, it creates an electron-hole pair. This phenomena is a type of photoelectric effect. If the absorption occurs in the junction's depletion region, or one diffusion length away from the depletion region, these carriers (electron-hole pair) are attracted from the PIN or p-n junction by the built-in electric field of the depletion region. The electric field causes holes to move toward the anode, and electrons to move toward the cathode; the movement of the holes and electrons creates a photocurrent. In some embodiments, the amount of photocurrent is an analog value, which can be digitized by a analog-to-digital converter. In some embodiments, the analog value is amplified before being digitized.
In an embodiment, the sampling of the digitized photocurrent values may converted to threshold times as follows. A photocurrent threshold θ is selected as a sampling parameter. If a digitized photocurrent value i1 is above θ at time t1, then t1 is recorded as a threshold time. If the next digitized photocurrent value i2 above θ occurs at time t2, then t2 is recorded as the next threshold time. If the next digitized value i3 above θ occurs at time t3, then t3 is recorded as the next threshold time.
After three consecutive threshold times are recorded, these three times can determine a bit value as follows. If t2−t1>t3−t2, then the non-deterministic process produces a 1 bit. If t2−t1<t3−t2, then the non-deterministic process produces a 0 bit. If t2−t1=t3−t2, then NO bit information is produced. To generate the next bit, non-deterministic process 542 or 552 continues the same sampling steps as before and three new threshold times are produced and compared.
In an alternative sampling method, a sample mean μ is established for the photocurrent, when it is illuminated with photons. In some embodiments, the sampling method is implemented as follows. Let i1 be the photocurrent value sampled at the first sampling time. i1 is compared to μ. ϵ is selected as a parameter in the sampling method that is much smaller number than μ. If it is greater than μ+ϵ, then a 1 bit is produced by the non-deterministic process 542 or 552. If i1 is less than μ−ϵ, then a 0 bit is produced by non-deterministic process 542 or 552. If it is in the interval [μ−ϵ, μ+ϵ], then NO bit is produced by non-deterministic process 542 or 552.
Let i2 be the photocurrent value sampled at the next sampling time. i2 is compared to μ. If i2 is greater than μ+ϵ, then a 1 bit is produced by the non-deterministic process 542 or 552. If i2 is less than μ−ϵ, then a 0 bit is produced by the non-deterministic process 542 or 552. If i2 is in the interval [μ−ϵ, μ+ϵ], then NO bit is produced by the non-deterministic process 542 or 552. This alternative sampling method continues in the same way with photocurrent values i3, i4, and so on. In some embodiments, the parameter ϵ is selected as zero instead of a small positive number relative to μ.
Some alternative hardware embodiments of a non-deterministic process are described below. In some embodiments that utilize non-determinism to produce random clock machines, a semitransparent mirror may be used. In some embodiments, the mirror contains quartz (glass). The photons that hit the mirror may take two or more paths in space. In one embodiment, if the photon is reflected, then the non-deterministic process creates the bit value b∈{0, 1}; if the photon is transmitted, then the non-deterministic process creates the other bit value 1-b. In another embodiment, the spin of an electron may be sampled to generate the next non-deterministic bit. In still another embodiment of generating random clock machines, a protein, composed of amino acids, spanning a cell membrane or artificial membrane, that has two or more conformations can be used to detect non-determinism: the protein conformation sampled may be used to generate a value in {0, . . . n−1} where the protein has n distinct conformations. In an alternative embodiment, one or more rhodopsin proteins could be used to detect the arrival times t1<t2<t3 of photons and the differences of arrival times (t2−t1>t3−t2 versus t2−t1<t3−t2) could generate non-deterministic bits that produce random values.
In some embodiments, the seek time of a hard drive can be used as random values as the air turbulence in the hard drive affects the seek time in a non-deterministic manner. In some embodiments, local atmospheric noise can be used as a source of random values. For example, the air pressure, the humidity or the wind direction could be used. In other embodiments, the local sampling of smells based on particular molecules could also be used as a source of non-determinism.
In some embodiments, a Geiger counter may be used to sample non-determinism and generate random values. In these embodiments, the unpredictability is due to radioactive decay rather than photon emission, arrivals and detection.
A one-way hash function Φ, has the property that given an output value z, it is computationally intractable to find an information element mz such that Φ(mz)=z. In other words, a one-way function Φ is a function that can be easily computed, but that its inverse Φ−1 is computationally intractable to compute [9]. A computation that takes 10101 computational steps is considered to have computational intractability of 10101.
More details are provided on computationally intractable. In an embodiment, there is an amount of time T that encrypted information must stay secret. If encrypted information has no economic value or strategic value after time T, then computationally intractable means that the number of computational steps required by all the world's computing power will take more time to compute than time T. Let C(t) denote all the world's computing power at the time t in years.
Consider an online bank transaction that encrypts the transaction details of that transaction. Then in most embodiments, the number of computational steps that can be computed by all the world's computers for the next 30 years is in many embodiments likely to be computationally intractable as that particular bank account is likely to no longer exist in 30 years or have a very different authentication interface.
To make the numbers more concrete, the 2013 Chinese supercomputer that broke the world's computational speed record computes about 33,000 trillion calculations per second [12]. If T=1 one year and we can assume that there are at most 1 billion of these supercomputers. (This can be inferred from economic considerations, based on a far too low 1 million dollar price for each supercomputer. Then these 1 billion supercomputers would cost 1,000 trillion dollars.). Thus, C(2014)×1 year is less than 109×33×1015×3600×24×365=1.04×1033 computational steps.
As just discussed, in some embodiments and applications, computationally intractable may be measured in terms of how much the encrypted information is worth in economic value and what is the current cost of the computing power needed to decrypt that encrypted information. In other embodiments, economic computational intractability may be useless. For example, suppose a fusion power plant wants to keep its codes and infrastructure unbreakable to cyber terrorists. Suppose T 2000 years because it is about twice the expected lifetime of the power plant. Then 2000 years×C(4017) is a better measure of computationally intractable for this application. In other words, for critical applications that are beyond an economic value, one should strive for a good estimate of the world's computing power.
One-way functions that exhibit completeness and a good avalanche effect or the strict avalanche criterion [32] are preferable embodiments: these properties are favorable for one-way hash functions. The definition of completeness and a good avalanche effect are quoted directly from [32]:
A hash function, also denoted as Φ, is a function that accepts as its input argument an arbitrarily long string of bits (or bytes) and produces a fixed-size output of information. The information in the output is typically called a message digest or digital fingerprint. In other words, a hash function maps a variable length m of input information to a fixed-sized output, Φ(m), which is the message digest or information digest. Typical output sizes range from 160 to 512 bits, but can also be larger. An ideal hash function is a function Φ, whose output is uniformly distributed in the following way: Suppose the output size of Φ is n bits. If the message m is chosen randomly, then for each of the 2n possible outputs z, the probability that Φ(m)=z is 2−n. In an embodiment, the hash functions that are used are one-way.
A good one-way hash function is also collision resistant. A collision occurs when two distinct information elements are mapped by the one-way hash function Φ to the same digest. Collision resistant means it is computationally intractable for an adversary to find colllisions: more precisely, it is computationally intractable to find two distinct information elements m1, m2 where m1≠m2 and such that Φ(m1)=Φ(m2).
A number of one-way hash functions may be used to implement one-way hash function 148. In an embodiment, SHA-512 can implement one-way hash function 148, designed by the NSA and standardized by NIST [25]. The message digest size of SHA-512 is 512 bits. Other alternative hash functions are of the type that conform with the standard SHA-384, which produces a message digest size of 384 bits. SHA-1 has a message digest size of 160 bits. An embodiment of a one-way hash function 148 is Keccak [6]. An embodiment of a one-way hash function 148 is BLAKE [2]. An embodiment of a one-way hash function 148 is Gr∅stl [13]. An embodiment of a one-way hash function 148 is JH [33]. Another embodiment of a one-way hash function is Skein [11].
The symbol ¬ represents the unary NOT gate. ¬(0)=1 and ¬(1)=0. The symbol V represents the binary OR gate. 0∨0=0 and 0∨1=1 ∨0=1∨1=1. The binary AND gate is represented with ∧. 1 ∧1=1 and 0∧1=1 ∧0=0 ∧0=0. In the prior art, gates are typically implemented with transistors.
A bit has two states 0 or 1. In some embodiments, a bit is represented with voltage. In another embodiment, a bit may be represented with the polarization of a photon. The expression {0, 1}n represents the set of all n-bit strings. There are 2n different n-bit strings. The expression {0, 1}4 represents the all 4-bit strings. 0101 is a 4-bit string. There are 16 different 4-bit strings
Symbol denotes the integers and the non-negative integers. For any n∈ such that n≥2 and a∈ such that 0≤a≤n−1, consider the equivalence class [a]{a+kn: k∈} that is a subset of . Let n={[0], [1], . . . , [n−1]}. mod is the modulo function and a mod n is the remainder when a is divided by n. In the standard manner, (n, +n) is an abelian group, where binary operator+n is defined as [a]+n [b][(a+b) mod n]. For clarity, the brackets are sometimes omitted and [a]∈n is represented with the integer a, satisfying 0≤a≤n−1. The field i is the two elements {0, 1}, where + is addition modulo 2 and multiplication * is equal to ∧ (AND).
The least common multiple of positive integers a and b is 1 cm(a, b). The greatest common divisor of a and b is gcd(a, b). Let p1=2, p2=3, p3=5, p4=7 . . . where the nth prime number is pn. Let p be an odd prime. p is called a 3 mod 4 prime if
is odd. p is called a 1 mod 4 prime if
is even. log2(n) is the logarithm base 2 of n. ┌x┐=the smallest integer l such that l≥x.
This section provides specifications and procedures related to prime clocks executing in one or more prime clock machines.
Let p be a prime number. Let t∈ such that 0≤t≤p−1. Define prime clock machine [p, t]: → as [p, t](m)=(m+t) mod p. Prime clock machine [p, t] is called a p-clock machine and is a computational machine that starts ticking (i.e., starts changing its time state) with its hand pointing to t; this is another of saying that its time state starts at t. The number p is the total number of time states that the clock [p, t] has.
In some embodiments, p is a composite number. Herein the expression clock [p, s] always assumes that the starting time state s satisfies 0≤s≤p−1. Thus, if p≠q or s≠t, then prime clock [p, s] is not equal to prime clock [q, t]; equivalently, if p=q and s=t, then [p, s]=[q, t]. If p≠q, the clock [p, s] has a different number of time states than clock [q, t]. If s≠t, the clock [p, s] has a different starting time state than clock [q, t].
In machine specification 1, the phrase clock machine was chosen because p-clock machines have some similarities to traditional 12-clocks common in some homes. It is important to recognize that clock machine [p, t] is a computational machine that has different physical instantiations, depending on the hardware or software embodiment.
In some software embodiments, the clock machine is a virtual machine. A virtual machine means the clock machine may be implemented in C source code or Python source code or another suitable programming language. The source code implementation of the clock machine is compiled to execute on a standard operating system such was Windows, Linux, or Apple OS.
A clock machine should not be confused with a CPU clock that is built from transistor gates and uses a crystal to provide the voltage oscillations and voltage changes in the transistor gates.
Another notable difference is that CPU clocks typically tick based on a power of 2; that is, 2n where n is a positive integer. Clock machines tick (i.e., changes its time state) usually based on clocks that use prime numbers as the number of states in the clock. In a 7-clock, the prime clock machine ticks based on 7 distinct states {0, 1, 2, 3, 4, 5, 6} before it repeats.
For the nth prime pn, let {[pn, 0], [pn, 1], . . . , [pn, pn−1]} be the distinct pn-clocks. The collection of all prime clocks is defined as
For n≥2, let Ωn=. Define Πn:→Ωn as the projection of each p-clock machine into Ωn where Πn([p, t](m))=[p, t](m) mod n.
Let n∈ such that n≥2. On the collection of clock machines, define the binary operator machine ⊕n as ([p, s]⊕n[q, t])(m)=([p, s](m)+[q, t](m)) mod n, where + is computed in . Observe that the prime clock machine [p, s]⊕n [q, t] computes in Ωn.
Similarly, with prime clock machines [q1, t1], [q2, t2] . . . and [qL, tL], a new machine [q1, t1]⊕n[q2, t2] . . . ⊕n[qL, tL]:→n can be constructed. From a mathematics perspective of how the machine behaves, [q1, t1]⊕n[q2, t2] . . . ⊕n+[qL, tL] is sometimes called a function. For each m∈, define ([q1, t1]⊕n[q2, t2]⊕n . . . ⊕n[qL, tL])(m)=([q1, t1](m)+[q2, t2](m)+ . . . +[qL, tL](m)) mod n, where + is computed in . [q1, t1]⊕n[q2, t2] . . . ⊕n+[qL, tL] is called a finite prime clock sum machine in Ωn.
In some embodiments, the binary operation machine ⊕n builds prime clock sum machines from prime clock machines (i.e., 306 of
In
In some hardware embodiments, the hardware uses semiconductor materials such as silicon and doping elements such as boron (3 valence electrons) and phosphorus (5 valence electrons). In some embodiments, these semiconductor materials be used to implement transistors that act as components in a flip flop. In some embodiments, these semiconductor materials are used to build D-type flip flops. A D-type flip flop is shown in
In
In
A [p, s] clock machine, where 0<s<p, can be constructed in a similar way to the clock machine [p, 0], by translating the waveform of P, shown in
In some embodiments, elements such as aluminum, indium and arsenic, and antimony are used to build the semiconductor hardware that executes one or more clock machines. In some embodiments, these semi-conductor materials are used to build flip flops that help implement a clock machine, similar to the one shown in
Prime Clock Sum Complexity
The complexity map C is defined as C([p,t])=2┌log2┐(p)┌ if p>2 and C([2, t])=4. The complexity of [q1, t1]⊕n[q2, t2] . . . ⊕n[qL, tL] is
Let r1, . . . rk be k prime numbers and q1, . . . qr be r prime numbers. Let ƒ=[r1, s1]⊕n [r2, s2] . . . ⊕n [rk, sk]. Let g=[q1, t1]⊕n[q2,t2] . . . ⊕n [qL, tL]. Define ƒ ⊕n g in Ωn as (ƒ ⊕n g) (m)=ƒ(m)+n g(m), where +n is the binary operator in the group (n, +n).
Machine specification 5 is well-defined with respect to machine specification 3. In particular, ƒ ⊕n g [r1, s1]⊕n [r2, s2] . . . ⊕n [rk, sk]⊕n [q1, t1]⊕n [q2, t2] . . . ⊕n [qL, tL] because (m1+m2) mod n=((m1 mod n)+(m2 mod n)) mod n for any m1, m2 ∈. (See remark 1 in the appendix.)
The binary operator machine ⊕n can be extended to all of Ωn. For any ƒ, g ∈Ωn, define (ƒ ⊕n g) (m)=ƒ(m)+n g(m). The associative property (ƒ ⊕n g) ⊕n h=ƒ ⊕n (g ⊕n h) follows immediately from the fact that +n is associative. The zero function
Let Q be a collection of the prime clock machines . Using the projection Πn, of Π into Ωn, define SΠ={H:H⊇Πn(Π) and H is a subgroup of Ωn}. Q generates a subgroup
of machines computing over (Ωn, ⊕n).
In some computing applications and embodiments, such as cryptography, the ciphers such as Midori [4] are computed with Boolean functions, so the specification sometimes refers to subgroups of Ω2, generated by a finite number of prime clocks. Consequently, the symbol ⊕ throughout the patent specification represents the symbol ⊕2. In other embodiments, the prime clock machine may compute over subgroups of Ω256 or subgroups over Ω2
Let Fn denote the set of all Boolean functions in n variables. Mathematically, Fn={ƒn|ƒn: {0, 1}n→{0, 1}}, so Fn contains 22
Consider clock machine [p, s]⊕[q, t] in Ω2. The first 2n elements of [p, s]⊕[q, t] refer to the bit string ([p, s]⊕[q, t])(0), ([p, s]⊕[q, t])(1), . . . , ([p, s]⊕[q, t])(2n−1) of length 2n. The first 2n elements of [p, s]⊕[q, t] represent a Boolean function ƒn ∈Fn. In some embodiments with q1, . . . , qL as primes, the first 2n elements of [q1, t1]⊕[q2, t2] ⊕ . . . ⊕[qL, tL] represent a Boolean function ƒn∈Fn.
Consider clock machine [q1, t1]⊕[q2, t2] ⊕ . . . ⊕[qL, tL] whose first 2n elements represent a truth table in Fn; this truth table is a bit string with length 2n. Machine procedure 1 shows how [q1, t1]⊕[q2, t2] ⊕ . . . ⊕[qL, tL] computes the Boolean function [q1, t1]⊕[q2, t2]⊕ . . . ⊕[qL, tL]: {0, 1}n→{0, 1} in L steps, where L is the number of clocks. The input is stored in the variable x, which takes up n bits of memory 256, shown in
The output y is called a bit output because y is 0 or 1. Output y is produced, by combining the output from the L clock machines [q1, t1], [q2, t2], . . . [qL, tL]. In some embodiments, machine procedure 1 is coded in a programming language such as C, Python, JAVA, Haskell, LISP or Ruby and executes as a virtual machine on a standard operating system such as Apple OS, Linux, Unix, or Windows. In other embodiments, machine procedure 1 can be coded in a programming language such as C or Python and then compiled to execute on a field programmable gate array (FPGA). In other embodiments, machine procedure 1 can be implemented directly in hardware with flip flops.
In some embodiments, machine procedure 1 executes the two instructions set e=(tk+x) mod qk and set e=e mod 2, inside the while loop, in parallel with L prime clock devices implemented in hardware. In some embodiments, the prime clock devices are implemented in semiconductor hardware. In some semiconductor embodiments, the prime clock machines are constructed with counters that reset after a prime number of state changes. In these embodiments, the mod 2 operator is implemented by selecting the least significant of the counter. In other semiconductor hardware embodiments, the output of a single prime clock machine is stored in a table in memory 256, shown in
The output y is called a bit output. The ith element of ([q1, t1]⊕[q2, t2]⊕ . . . ⊕[qL, tL])'s truth table is stored in the variable y when machine procedure 2 halts. The execution of machine procedure 2 is presented in a serial form. Nevertheless, the computation of the L instructions set rk=(tk+i) mod qk, where 1≤k≤L, can be executed in parallel when there is a separate physical device for each of these L prime clocks [q1, t1], [q2, t2] . . . [qL, tL]. Subsequently, the parity of y can be determined in a second computational step that executes a parallel add of r1+r2+ . . . +rL, followed by setting y to the least significant bit of the sum r1+r2+ . . . +rL.
In an embodiment, clock machine 302 in
are represented by Adding Instructions 308 and Modulo Instructions 310 in
In some embodiments, machine procedure 2 is coded in a programming language such as C, Python, JAVA, Haskell, LISP or Ruby and executes as a virtual machine on an operating system such as Android, Apple OS, Linux, Unix, or Windows. In other embodiments, machine procedure 2 can be coded in a programming language such as C or Python and then compiled to execute on an field programmable gate array (FPGA). FPGA hardware has the computational capability to execute one or more clock machines in parallel.
An n-bit exclusive-OR on n bits b1, b2, . . . bn is denoted as b1⊕b2⊕ . . . bn. Furthermore, if an even number of these n-bits are 1, then b1⊕b2⊕ . . . bn=0; if an odd number of these n-bits are 1, then b1⊕b2⊕ . . . bn=1.
As an alternative implementation of machine procedure 2, when there is a more suitable physical device for prime clocks, the kth clock can compute the kth bit bk=((tk+i) mod qk) mod 2 and then an L-bit exclusive-or can be applied in parallel [34] to the bits b1, b2, . . . , bL.
This example demonstrates 2-bit multiplication with prime clock sums, computed with machine procedure 2. In
One can verify that the function 0: {0, 1}2×{0, 1}2→{0, 1} can be computed with the prime clock sum [2, 0]⊕[7, 3]⊕[7, 4]⊕[7, 5]⊕[11, 10], according to machine procedure 2. Similarly, the Boolean function 1 can be computed with the prime clock sum [2, 0]⊕[2, 1]⊕[3, 0]⊕[5, 2]⊕[11, 0]⊕[11, 1], according to machine procedure 2. The Boolean function 2 can be computed with the prime clock sum [5, 0]⊕[7, 0]⊕[7, 2]⊕[11, 4]. Lastly, the function 3 can be computed with the prime clock sum [2, 1]⊕[5, 0]⊕[11, 1]⊕[11, 6]. □
As described in machine specifications 1, 2, 3 and 5 and as shown in
In an embodiment, clock machine 302 in
are represented by Adding Instructions 308 and Modulo Instructions 310 in
Similar to
In an embodiment, clock machine 302 in
are represented by Adding Instructions 308 and Modulo Instructions 310 in
The machine specification for periodic machine (p, i):→{0, 1} is as follows: (p, i)(t)=1 whenever (p+t−i) mod p=0; (p, i)(t)=0 whenever (p+t−i) mod p≠0. In
The purpose of δ is to indicate the time duration of the high output, indicating the digital output of 1. In some embodiments, the output is a voltage. For example, flip-flops (
A finite number of periodic machines can be “summed” to construct a computing machine. “Summed” means computing the logical OR (maximum) of the output of all periodic machines at a particular input time state. m periodic machines (p1, i1), (p2, i2), . . . , (pm, im) can be summed to perform a computation as follows. For time state t that serves as the input, the sum [(p1, i1)+(p2, i2)+ . . . +(pm, im)](t)=0 if (pk, ik)(t)=0 for every k satisfying 1≤k≤m. Otherwise, if there is some k such that (pk, ik)(t)=1, then [(p1, i1)+(p2, i2)+ . . . +(pm, im)](t)=1. Thus, we can construct a 2-input OR gate as (4, 1)+(4, 2)+(4, 3).
In general, a periodic machine computation is executed according to machine procedure 5, where each periodic machine (pk, ik) can compute its output in parallel. The output of this computation is not dependent on the order shown in the while loop. Every computation yk=(pk, ik)(t) may be performed simultaneously with hardware that implements the periodic machine (pk, ik).
In machine procedure 5, max means take the maximum of all outputs y1, Y2, . . . ym, which in some embodiments is computed by an m-bit logical OR of these outputs. In other embodiments, more than one logical OR may be used to compute the maximum. Similar to theorem 8, any Boolean function ƒ: {0, 1}n→{0, 1} can be computed from a finite number of periodic machines, according to machine procedure 5. As an example, in
This section of the specification demonstrates how to execute the lightweight cipher Midori [4] with random prime clock machines. In some embodiments, clock machines can execute directly in semiconductor hardware.
The purpose of randomly generating the clock machines is to help provide greybox protection. In this specification, the greybox model assumes that the adversary Eve can observe the electromagnetic signal emitted from the processor chip executing the computer instructions and Eve knows the cryptographic algorithm executed (e.g., Midori cipher). In some embodiments, Eve does not have realtime, direct access to the prime clock machines executing a cryptographic algorithm. In some embodiments, greybox protection can help make key recovery attacks more difficult for the adversary.
Midori consists of two different block ciphers: Midori64 and Midori128. Both use 128-bit keys. Midori64 has block size n=64. In function notation, Midori64: {0, 1}64×{0, 1}128→{0, 1}64. The set {0, 1}64 represents 64-bit blocks selected from the message space and {0, 1}128 is the key space. Midori128 has block size n=128, where Midori128: {0, 1}128×{0, 1}128→{0, 1}128. The first set {0, 1}128 in the Cartesian product represents the 128-bit blocks selected from the message space and the second set {0, 1}128 is the key space.
Midori is a variant of a Substitution-Permutation Network cipher that has an S-layer, a P-layer and has a 4×4 data structure as the state:
Each element (cell) si of the state is 4 bits in Midori64 and 8 bits in Midori128. Before Midori64 encrypts a 64-bit block, the 64-bit plaintext M is stored in the state. Similarly, before Midori128 encrypts a 128-bit block, the 128-bit plaintext M is stored in the state. After the ith round, the output state is Sz. The 0th state S0=M since no rounds have been computed when i=0.
Next, this section describes how Midori64 and Midori128 compute their nonlinear operations. Midori64 uses the bijective 4-bit S-box S0: {0, 1}4→{0, 1}4 which is defined in
Similarly, Midori128 uses the bijective 4-bit S-box S1: {0, 1}4→{0, 1}4 which is defined in
The concatenation operation II on two strings can be extended to functions. Define the concatenation operator ∥ on S1 where S1∥S1: {0, 1}8→{0, 1}8 is defined as S1∥S1(x0x1x2x3x4x5x6x7)=S1(x0x1x2x3)∥S1(x4x5x6x7). Since (S1∥S1) ∘ (S1∥S1)=(S1 ∘ S1)∥(S1 ∘ S1), this implies S1∥S1 is also an involution.
Midori128 uses four 8-bit substitution boxes 0, 1, 2, and 3, where each i: {0, 1}8→{0, 1}8. For each i∈{0, 1, 2, 3}, the substitution box i is computed as i=σi−1 ∘ (S1∥S1) ∘ σi, where S1 is defined in
Lastly, in order to compute the round function, the following matrix is needed
The round function is comprised of an S-layer SubCell: {0, 1}m→{0, 1}n a P-layer ShuffleCell and MixColumn: {0, 1}n→{0, 1}n and a key-addition layer KeyAdd: {0, 1}n×{0, 1}n→{0, 1}n. Each of these layers updates the n-bit state S according to the following 4 steps.
For Midori64, the 128-bit secret key K is denoted as the concatenation of two 64-bit keys K0 and K1, where K=K0∥K1. The 64-bit key W=K0 ⊕K1 and the 64-bit round key Ri=K(i mod 2) ⊕αi where 0≤i≤14. Note that αi=βi for 0≤i≤14, where the round constants βi are defined in
For Midori128, the 128-bit key W=K and the 128-bit round key Ri=K⊕βi, for 0≤i≤18. In
As discussed above, the S-box S0 and the S-box S1 are fundamental building blocks for the nonlinear operations in Midori64 and Midori128, respectively.
Prime clock sum [2, 1]⊕[3, 2]⊕[5, 2]⊕[17, 16] is located in the last row and last column of
As another example of a prime clock machine execution, in
The prime clock sums in
Next we turn to the linear operations used in Midori64 and Midori128. First, observe that the other three layers ShuffleCell(S), MixColumn(S), and KeyAdd(S) can be constructed from affine Boolean functions.
ShuffleCell(S) is a permutation τ of the state S, where τ=(s1 s7 s12 s10)(s2 s14 s4 s5)(s3 s9 s8 s15)(s6 s11). In Midori64, τ: {0, 1}64→{0, 1}64, where τ(x)=(τ0(x), τ1(x), . . . , τ63(x)) and each τi: {0, 1}64→{0, 1} is an affine function. In Midori128, τ: {0, 1}128→{0, 1}128, where τ(x)=(τ0(x), . . . τ127(x)) and each τi: {0, 1}128→{0, 1} is an affine function.
In MixColumn(S), each row×column multiplication in the matrix multiplication is a dot product on the vector space over 2. For example, the first row of M corresponds to the affine map A0111,0, which is defined in
In KeyAdd(S, Ri), each Ri is built from a different constant from
Overall, the Midori cipher can be executed with prime clocks chosen from the first 8 primes. Of the first 8 primes, {5, 13, 17} are the 1 mod 4 primes. Define function α4 on the primes as follow. If (p>16) then α4(p)=16. If p<16 and p is a 1 mod 4 prime then α4(p)=p−1. If p<16 and p is a 3 mod 4 prime or p=2, then α4(p)=p. There are 22
In section 6.15, machine lemma 3 and machine corollaries 5 and 7 imply that for each ƒ: {0, 1}4→{0, 1}, there are 256 different prime clock sums, constructed from the first 8 primes, that compute ƒ. Note 256>1016. Thus, each processor chip could be programmed with a unique collection of random prime clock sums that compute the Midori cipher such that the probability of two distinct processor chips computing the Midori cipher with identical random prime clock sums over the primes {p1, p2, . . . , p8} is substantially less than 10−9. A unique computational footprint for each chip can substantially obfuscate the execution of the Midori cipher and also break up any type of timing patterns during the cipher's execution.
This section describes machine procedure 6 that uses randomness for finding a clock machine that computes ƒ: {0, 1}n→{0, 1}. In an embodiment, random clock machines are chosen, using non-deterministic process 542 in
Some parameters are passed into the probabilistic machine and also a computable representation as either a software or hardware embodiment of Boolean function ƒ. The purpose is to be able to compute ƒ(x) on every input x∈{0, 1}n. A distance metric H, computed as a machine, between 2 functions is also needed.
Let Q be a prime clock sum machine. Let ƒ be a computable representation of Boolean function ƒ: {0, 1}n→{0, 1}. The function ƒ ⊕Q: {0, 1}n→{0, 1} is defined as ƒ(x)⊕Q(x). Define the Hamming distance between these two functions as H(Q, ƒ)=|(ƒ⊕Q)−1{1}|, where inverse image (ƒ⊕Q)−1 {1}={x∈{0, 1}n: ƒ(x)⊕Q(x)=1}. If H(Q, ƒ)=0, then Q(x)=ƒ(x) for every x in {0, 1}n.
The first parameter passed in is a positive integer u. u is an upper bound on the index of the primes to use for selecting prime clocks. For example, if u=6, then machine procedure 6 builds clock machines from the primes {2, 3, 5, 7, 11, 13}.
The second and third parameters passed in are rlb and rub such that rlb≤rub, which create a range of values for the number of random prime clocks to use to build prime clock machine Q. The fourth parameter passed in is s, which is the number of different random prime clocks machines to build for each value of r in {rlb, rlb+1, . . . , rub}. The fifth parameter passed in is n.
In an embodiment, non-deterministic process 542 or non-deterministic process 552 in
The search process time for machine Qbest can be substantially reduced by passing in a small s; and then exiting machine 6 with prime clock machine Qbest and then repairing Qbest at Z such that Qbest(x)⊕ƒ(x)=1. As an example, for n=4, suppose that the computation Qbest(12)⊕ƒ(12)=1, then repair machine Qbest by updating it to prime clock sum machine [2, 0]⊕[2, 1]⊕[17, 6]⊕[17, 7]⊕Qbest. If Qbest(i)⊕ƒ(i)=1 at i=10 and i=11, then update Qbest to [17, 5]⊕[17, 7]⊕Qbest. A similar repair machine can be used for larger n with a prime p>2n.
In an alternative embodiment, periodic machines (shown in
The purpose of this section is to better understand timing differences that occur when different instances of machine procedures 1 are executed. It is well-known in the prior art that timing differences can be exploited to capture a key from a cryptographic cipher and break the cryptography. (See [5, 20].) In the prior art, standard digital computers often have timing differences due to branch instructions. There are two places in the execution of machine procedure 1 where timing differences could occur:
1. The size of r is the number of clocks in the prime clock sum.
2. The two instructions set e=(tk+x) mod qk and set e=e mod 2 depend upon qk, tk and x.
The other instructions such as set y (y+e) mod 2 should exhibit no timing differences because both y and e store 0 or 1 and y {circumflex over ( )}=e; is the C source code for this mathematical operation.
For these reasons, the Intel timestamp instruction RDTSC [17] was called to measure timing differences with b−a, as shown in the following C source code. The value b−a is the number of Intel CPU clock cycles that occur during the CPU's execution of the two instructions e=(t+x) % p; and e &=1;
A 2.5 GHz Intel Core i5 CPU executed for these timing tests. Our timing results were measured on the first 100 primes p; on each prime clock ticking time t such that 0≤t<p; and all 16-bit input values x. For a fixed triplet (p, t, x), the CPU clock cycles timing difference b−a was measured on 1000 samples.
In
In some embodiments, timing tests for prime clock machines executing in semiconductor hardware suggest that the number of clocks (parameter r in algorithm 1) in the sum is the primary influence on execution time. In some embodiments, prime clocks execute in parallel to help eliminate timing differences.
An alternative embodiment varies the number of clocks for each random prime clock sum machine instantiation in hardware: in the greybox model, Eve would not know for a particular processor chip how many prime clocks are used to implement the S0 or S1 S-boxes or the number of clocks used to implement one of the affine maps that compose the ShuffleCell(S), MixColumn(S) or KeyAdd(S) layers.
This section provides further specifications, properties and proofs about prime clock machines and in particular finite prime clock machines executing in Ω2. The intermediate results work toward the theorem 8, stated in the introduction: For any positive integer n, for each of the 22
First, a remark is proven that was cited in section 6.5.
(mi+m2) mod n=((mi mod n)+(m2 mod n)) mod n.
PROOF. Euclid's division algorithm implies that m1=k1n+r1 and m2=k2n+r2, where 0≤r1, r2<n. Now (m1+m2) mod n=((k1+k2)n+r1+r2) mod n=(r1+r2) mod n=((m1 mod n)+(m2 mod n)) mod n □
The following equivalence relation on N induced by a function ƒ∈Ωn helps characterize prime clock sums.
For any ƒ∈Ωn, define the relation on such that if and only if for all m∈, ƒ(m)=ƒ(m+|y−x|).
Trivially, is reflexive and symmetric. Next, transitivity of is verified. Suppose and W.L.O.G., suppose x≤y≤z. (The other orderings of x, y and z can be handled by permuting x, y and z in the following steps.) This means for all m∈, ƒ(m+y−x)=ƒ(m); and for all k∈, ƒ(k)=ƒ(k+z−y). This implies that for all m∈, ƒ(m+z−x)=ƒ(m+z−y+y−x)=ƒ(m+y−x)=ƒ(m).
is an equivalence relation.
Periodic Functions
ƒ∈Ωn is a periodic function if there exists a positive integer b such that for every m∈, then ƒ(m)=ƒ(m+b). Furthermore, if a is the smallest positive integer such that ƒ(m)=ƒ(m+a) for all m∈, then a is called the period of ƒ. After k substitutions of m+a for m, this implies for any m∈ that ƒ(m)=ƒ(m+ka) for all positive integers k.
As shown in
When ƒ is periodic with period a, each equivalence class is of the form [k]={k+ma: m∈}, where 0≤k<a. Thus, ƒ has period a implies there are a distinct equivalence classes on N with respect to
If a is the period of ƒ and b is a positive integer such that ƒ(m)=ƒ(m+b) for all m∈, then a divides b.
PROOF. First, verify that By the definition of period, a≤b and for all m∈, then ƒ(m+b−a)=ƒ(m+a+b−a)=ƒ(m+b)=ƒ(m). From the prior observation, a lies in [0] and b also lies in [0]. Thus, b=ma for some positive integer m. □
If ƒ, g∈Ωn are periodic, then ƒ⊕n g is periodic. Further, if the period of ƒ is a and the period of g is b, then ƒ⊕n g has a period that divides 1 cm(a, b).
PROOF. Let a be the period of ƒ and b the period of g. Let la,b=1 cm(a, b). la,b=ia and la,b=jb for positive integers i, j. For any m∈N, (ƒ⊕n g)(m)=ƒ(m)+n g(m)=ƒ(m+ia)+n g(m+jb)=ƒ(m+la,b)+n g(m+la,b)=(ƒ⊕n g)(m+la,b). Thus, ƒ ⊕n g is periodic and remark 3 implies its period divides la,b. □
In regard to lemma 1, if g=−ƒ, then the period of ƒ ⊕n g is 1.
There are na distinct periodic functions ƒ∈Ωn whose period divides a.
PROOF. Since ƒ is periodic and its period divides a, the values of ƒ(0), ƒ(1), . . . , ƒ(a−1) uniquely determine ƒ. There are n choices for ƒ(0). There are n choices for ƒ(1), and so on. □
Periodic functions with prime periods are straightforward to count.
Suppose p is prime. There are np−n distinct periodic functions ƒ∈Ωn with period p.
PROOF. Consider a finite sequence c0, c1, . . . cp−1 of length p where each ci∈n This sequence uniquely determines a periodic ƒ such that ƒ(m+p)=ƒ(m) for all m∈. In particular, ƒ(0)=c0, ƒ(1)=c1, . . . , ƒ(p−1)=cp−1. There are np periodic functions with a period that divides p. If the period of ƒ is less than p, then remark 3 implies ƒ has period 1 since p is prime. There are n distinct, constant (period 1) functions in Ωn Thus, the remaining np−n periodic functions have period p. □
The prime clock [p, t], projected into Ωn, has period p.
PROOF. Since p is prime, this follows immediately from remark 3. □
Finite Prime Clock Sums are Periodic
Any finite sum of prime clock machines [q1, t1]⊕n [q2, t2]⊕n . . . ⊕n[q1, t1] is periodic.
PROOF. Use induction and apply remark 6 and lemma 1. □
The following statements are restricted to Ω2.
Machine Remark 7. [p, t]⊕[p, t]
Per definition 2, ([p, k]⊕[p, k])(m)=([p, k](m)+[p, k](m)) mod 2=0 in 2.
Let ƒ∈Ωn. If ƒ is a constant function where ƒ(m)=c for all m∈, then the expression ƒ=
Let p be an odd prime. If p is a 3 mod 4 prime, then prime clock machine [p, 0]⊕[p, 1]⊕ . . . ⊕[p, p−1]=
PROOF. ([p, 0]⊕[p, 1]⊕ . . . ⊕[p, p−1])(0)=(0+1+ . . . +p−1) mod 2=½(p−1)p mod 2. For each m>0, ([p, 0]⊕[p, 1]⊕ . . . ⊕[p, p−1])(m) is a permutation of the sum inside (0+1+ . . . +p−1) mod 2. □For the special case p=2, observe that [2, 0]⊕[2, 1]=
A finite sum [q1, t1]⊕[q2, t2]⊕ . . . ⊕[q1, t1] machine of prime clocks is non-repeating if i≠j implies [qi, ti] is not equal to [qj, tj].
Any finite sum [q1, t1]⊕[q2, t2]⊕ . . . ⊕[ql, tl] of prime clock machines in Ω2 can be reduced to a non-repeating finite sum [qi
Since (Ω2, ⊕2) is abelian, if necessary, rearrange the order of [q1, t1]⊕[q2, t2]⊕ . . . ⊕[ql, tl], so that the prime clocks are ordered using the dictionary order. If two or more adjacent prime clocks are equal, then the associative property and remark 7 enables the cancellation of even numbers of equal prime clocks. This reduction can be performed a finite number of times so that the resulting sum is non-repeating. □
Let p be a prime. A finite sum of prime clock machines [p, t1]⊕[p, t2]⊕ . . . [p, tl-1]⊕[p, tl] is called a p-clock sum of length l if for each 1≤i≤l, the clock [p, ti] is a p-clock machine and the sum is non-repeating. The non-repeating condition implies l≤p.
Let p be a prime. A p-clock machine sum with length p has period 1. A p-clock machine sum with length l such that 1≤l<p has period p.
PROOF. When p=2, the 2-clock sum [2, 0] has period 2 and the 2-clock sum [2, 1] also has period 2. Recall that [2, 0]⊕[2, 1]=
Let [p, t1]⊕[p, t2]⊕ . . . [p, tl-1]⊕[p, tl] be a p-clock sum. When l=p, remark 8 implies that [p, t]⊕[p, t2]⊕ . . . [p, tl-1]⊕[p, tl] has period 1. Lemma 1 and remark 6 imply that [p, t1]⊕[p, t2]⊕ . . . [p, tl-1]⊕[p, tl] has period p or period 1. The rest of this proof shows that 1≤l≤p−1 implies that the p-clock sum cannot have period 1.
Thus, it suffices to show that 1≤l<p implies that ([p, t1]⊕[p, t2]⊕ . . . ⊕[p , tl])(m)≠([p, t1]⊕[p, t2]⊕ . . . ⊕[p, tl]) (m+1) for some m∈. If needed, the p-clock sum may be permuted so that [p, s1]⊕[p, s2]⊕ . . . ⊕[p, sl]=[p, t1]⊕[p, t2]⊕ . . . ⊕[p, t] and the si are strictly increasingly. Strictly increasing means 0≤s1<s2 . . . sl-1<st≤p−1.
Case A. l is odd. If sl<p−1, then
because l is odd.
Otherwise, sl=p−1. Set s0=0. (The auxiliary index s0=0 handles the case sk+1−sk for all k such that 1≤k≤l.) Set m=max {k∈: sk+1−sk≥2 and 0≤k<l}. Since s0=0 and 1≤l<p the pigeonhole principle implies m exists. Before the mod 2 step, the difference between
equals l. Thus, ([p, s1]⊕[p, s2]⊕ . . . ⊕[p, sl])(l−m)≠([p, s1]⊕[p, s2]⊕ . . . ⊕[p, sl])(l−m+1).
Case B. l is even. Set j=(p−1)−sl. Before the mod 2 step, the sum
differs from the
by an odd number. Thus, ([p, s1]⊕ . . . ⊕[p, sl])(j)≠([p, s1]⊕ . . . ⊕[p, sl])(j+1). □.
Let p be prime. The p-clock machine sum [p, s1]⊕ . . . ⊕[p, sl] is distinct from the p-clock machine sum [p, t1]⊕ . . . ⊕[p, tm] if l≠m or if for some i, prime clock [p, si] machine is not an element of the set of machines {[p, t1], [p, t2], . . . [p, tm]}.
7-clock sum [7, 2]⊕[7, 3] is distinct from [7, 2]⊕[7, 3]⊕[7, 4]. 7-clock sum [7, 0]⊕[7, 2]⊕[7, 3] is distinct from [7, 1]⊕[7, 2]⊕[7, 3].
For any 3 mod 4 prime p, if two p-clock sums are distinct, then they are not equal in Ω2. The theorem also holds for p=2.
PROOF. The special case p=2 is verified by examining columns 2 and 3 of
Let p be a 3 mod 4 prime. Assume p-clock sum [p, s1]⊕ . . . ⊕[p, sl] is distinct from p-clock sum [p, t1]⊕ . . . ⊕[p, tm]. By reductio absurdum, suppose
[p,s1]⊕ . . . ⊕[p,sl]=[p,t1]⊕ . . . ⊕[p,tm]. (6.2)
For each si ∈{t1, . . . , tm}, the operation ⊕[p, si] in Ω2 can be applied to both sides of equation 6.2. Similarly, for each tj ∈{s1, . . . , sl}, the operation ⊕[p, tj] can be applied to both sides of equation 6.2. Since (Ω2, ⊕) is an abelian group, equation 6.2 can be simplified to [p, s1]⊕ . . . ⊕[p, sL]=[p, t1]⊕ . . . ⊕[p, tM] such that {s1, . . . , sL}∩{t1, . . . , tM}=∅ and M+L≤p.
Set ƒ=[p, s1]⊕ . . . ⊕[p, sL]. Apply ƒ⊕ to both sides of [p, s1]⊕ . . . ⊕[p, sL]=[p, t1]⊕ . . . ⊕[p, tM]. This simplifies to ƒ⊕[p, t1]⊕ . . . ⊕[p, tM]=
Let St be the set of all p-sums of length l, where 1≤l≤p. There are (lp) distinct p-sums in each set Sl. Set
For any ƒ, g∈Gp, remark 7 implies ƒ⊕g−1 in Gp. Thus, (Gp, ⊕) is an abelian subgroup of Ω2.
Set Bp={0, 1}p. For any a1 . . . ap ∈Bp and b1 . . . bp∈Bp, define a1 . . . ap+2 b1 . . . bp=c1 . . . cp, where ci=(ai+bi) mod 2. (Bp, +2) is an abelian group with 2p elements.
When p is a 3 mod 4 prime, define the group isomorphism ϕ: Gp→Bp where ϕ(
Let p be a 3 mod 4 prime. The subgroup Gp of χ2, generated by the p-clocks [p, 0], [p, 1], . . . [p, p−1] has order 2p and is isomorphic to (Bp, +2).
PROOF. Theorem 4 implies ϕ is a group isomorphism.
Theorem 4 does not hold when p is a 1 mod 4 prime. For example, [5, 0]⊕[5, 1] equals [5, 2]⊕[5, 3]⊕[5, 4].
For any 1 mod 4 prime p, if two p-clock sums are distinct and their lengths are both ≤
then they are not equal in Ω2.
PROOF. The proof is almost the same as the proof in theorem 4, except the additional condition that
and reduction [p, s1]⊕ . . . ⊕[p, sL]⊕[p, t1]⊕ . . . ⊕[p, tM]=
Let p be a 1 mod 4 prime. Let ƒ=[p, s1]⊕ . . . ⊕[p, sl] for some 1≤l≤½(p−1). Set T={0, 1, . . . , p−1}−{s1, . . . , sl}. Now T {t1, . . . tm}, where l+m=p. Set g=[p, t1]⊕ . . . ⊕[p, tm]. Then ƒ=g in Ω2.
PROOF. Since p is a 1 mod 4 prime,
in 2. When k>1, the sum of the elements of ƒ⊕g before projecting into Ω2 is a permutation of the elements {0, 1, . . . , p−1}. Thus, for all k>1, (ƒ⊕g) (k)=0 in 2. This means g=ƒ−1. Lastly, ƒ=ƒ−1 in Ω2, so ƒ=g in Ω2. □
Let p be a 1 mod 4 prime. Set
Observe that
To verify that (Hp−1, ⊕) is a subgroup of (Ω2, ⊕), let ƒ, g∈Hp−1. Since g=g−1 in (Ω2, ⊕), it suffices to show that ƒ⊕g lies in Hp−1. If ƒ or g equals
Similar to the group isomorphism ϕ, define ψ: Hp−1→Bp−1 such that ψ(
Let p be a 1 mod 4 prime. The subgroup Hp−1 of Ω2, generated by the p-clock machines [p, 0], [p, 1], . . . [p, p−1] has order 2p-1 and is isomorphic to (Bp−1, +2).
Let n be a positive integer. For any of the 22
PROOF. This theorem follows immediately from corollaries 5 and 7 along with Euclid's second theorem [15] that the number of primes is infinite. □
Furthermore, finding a finite prime clock machine that computes ƒ can be computed with efficient computational procedures because there are efficient computable algorithms that can decide whether a natural number n is prime.
This application claims priority benefit of U.S. Provisional Patent Application Ser. No. 62/357,191, entitled Prime Clock Computers, filed Jun. 30, 2016, which is incorporated herein by reference. This application is a continuation-in-part of U.S. Non-provisional patent application Ser. No. 15/629,149 entitled Clock Computing Machines, filed Jun. 21, 2017, which is incorporated herein by reference.
Number | Date | Country | |
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Parent | 15629149 | Jun 2017 | US |
Child | 16700803 | US |