CLOCK CONDITIONING CIRCUIT

Abstract

A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.

Description

BACKGROUND

1. Field

The present invention relates to electronic circuits which down convert the frequency of a signal.

2. Related Art

Some electronic circuits operate as signal processing systems which condition, receive and transmit signals. One type of signal processing system utilizes code division multiple access (CDMA), which is a channel access method for signal processing. By contrast, time division multiple access (TDMA) divides access by time, while frequency-division multiple access (FDMA) divides access by frequency. Wideband Code Division Multiple Access (WCDMA) is a wideband spread-spectrum channel access method that utilizes the direct-sequence spread spectrum method of asymmetric code division multiple access to achieve higher speeds and support more signals compared to TDMA systems.

Signal processing systems which implement CDMA or WCDMA methods often include a sigma-delta modulator, which provides a digital output signal in response to receiving an analog input signal. A sigma-delta modulator oversamples the analog input signal with a sampling signal having a sampling frequency f_Sample that is greater than the analog input signal bandwidth B. A signal is oversampled when it is sampled at a rate greater than the Nyquist rate f_N. The Nyquist rate is the minimum sampling rate required to avoid aliasing, and is equal to two times the highest frequency of the analog input signal (f_N=2×B). The analog input signal is oversampled so that the digital signal is a more accurate representation thereof.

Sampling frequency f_Sample is typically related to a reference frequency f_REF of a reference clock signal S_REF. In some signal processing systems, reference frequency f_REF is about 1248 MegaHertz (MHz) and 1456 MHz. However, it is sometimes desirable to have sampling frequency f_Sample be much lower than reference frequency f_REF. For example, it is often desirable to have a sampling frequency of 104 MHz (1248 MHz/12=104 MHz), 96 MHz (1248/13=96 Mhz) and 97.067 MHz (1456/15=97.067 MHz) at a 50% duty cycle. Hence, it is desirable to down convert reference frequency f_REF to provide a sampling signal with a frequency that is a fractional value of reference frequency f_REF (i.e. ⅙, 1/13, 1/15).

Some methods disclose providing sampling frequency f_Sample by dividing reference frequency f_REF by two different integer values to generate two sub-frequencies, and then averaging the two sub-frequencies. Other methods disclose providing several phase-shifted reference signals, each having frequency f_REF, and then selecting desired high-to-low and low-to-high transitions to provide the sampling signal. However, both of these methods generate jitter in the sampling signal, which refers to random variations in sampling frequency f_Sample. The jitter can introduce noise into the digital output signals being provided by the sigma-delta modulator, which reduces the accuracy thereof.

Some methods disclose increasing reference frequency f_REF to reduce jitter, and then down converting the increased reference frequency f_REF to the desired sampling frequency f_Sample. However, increasing reference frequency f_REF requires an increase in the power consumed by the signal processing system.

It is also desirable to provide sampling signals that have a desired phase difference between them. The phase difference between the sampling signals define time points at which the analog input signal is sampled. The phase difference between sampling signals can randomly change in response to the sampling signals traveling a distance. The phase difference between sampling signals can randomly change because the sampling signals are randomly skewed in response to traveling the distance. The random change in the phase difference between the sampling signals in response to skew is often uncontrollable and can cause jitter, which reduces the accuracy of the digital output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of a clock conditioning circuit, which receives an encoded clock signal S_ECLK and provides clock signals S_QCLK and S_DCLK in response.

FIG. 2 shows a graph of one example of clock signals S_QCLK and S_DCLK, wherein clock signals S_QCLK and S_DCLK are provided by the clock conditioning circuit of FIG. 1.

FIGS. 3 and 4 are graphs of other examples of clock signal S_QCLK, wherein clock signal S_QCLK is provided by the clock conditioning circuit of FIG. 1.

FIG. 5 is a graph of a complementary encoded clock signal S_ECLK, which has the opposite polarity of the encoded clock signal S_ECLK of FIG. 1.

FIGS. 6, 7 and 8 show timing diagrams having graphs, which illustrate that the period of and phase difference between clock signals S_QCLK and S_DCLK can be adjusted by clock conditioning circuit of FIG. 1 in response to receiving encoded clock signal S_ECLK.

FIGS. 9 and 10 show timing diagrams having graphs, which illustrate that the duty cycles of clock signals S_QCLK and S_DCLK can be adjusted by clock conditioning circuit of FIG. 1 in response to receiving encoded clock signal S_ECLK.

FIGS. 11 and 12 are circuit diagrams of embodiments of clock conditioning circuit of FIG. 1.

FIG. 13 is a timing diagram having graphs, which illustrate that the phase of clock signals S_QCLK and S_DCLK is adjustable in response to a synchronization signal S_SYNC1.

FIGS. 14, 15 and 16 are block diagrams of one embodiment of a signal conditioning system, which includes a modulator driven by the clock conditioning circuit of FIG. 1, wherein the clock conditioning circuit is driven by an encoded clock generator that provides encoded clock signal S_ECLK.

FIG. 17 is a block diagram of a circuit without a clock conditioning circuit, where a clock generator is providing phase adjusted clock signals S_QCLK and S_DCLK.

FIGS. 18, 19, 20 and 21 are methods of providing a conditioned clock signal.

DETAILED DESCRIPTION

A clock conditioning circuit provides two or more down converted and phase-shifted clock signals, which can be used to drive another circuit, such as a signal conditioning circuit. The clock signals are provided in response to an encoded clock signal provided to the clock conditioning circuit. The encoded clock signal includes information corresponding to a characteristic of the clock signals. The characteristic can be of many different types, such as the period, frequency, phase, symmetry and duty cycle of the clock signals. In general, the encoded clock signal includes the characteristics of multiple clock signals. However, in some embodiments, multiple encoded clock signals are provided to the clock conditioning circuit, wherein the multiple encoded clock signals include the characteristics of multiple clock signals.

The frequency of a signal is related to its period (T) by the well-known relation f=1/T. The signal is periodic when it repeats its values at regular intervals. A local period of a digital signal includes one HI state and one LO state per local clock period. A global period of the digital signal includes one or more of its local periods, which are repeated at regular intervals. It should be noted that some of the signals discussed herein have time varying periods, wherein period T varies as a function of time. The time varying period can be the local period and/or global period.

The encoded clock signal has a time varying period, wherein its local period changes with time between being equal to and unequal to its global period. Hence, the local period of encoded clock signal can be the same as the global period of encoded clock signal during one time interval. Further, the local period of the encoded clock signal can be different from the global period of the encoded clock signal during a different time interval. It should be noted that the global period of a reference clock signal discussed herein is equal to its local period. Hence, the reference clock signals discussed herein do not have a time varying period, wherein its local period changes between being equal to and unequal to its global period.

The clock conditioning circuit disclosed herein includes less complicated and less expensive circuitry to better control the frequency of the clock signals, as well as the phase difference between them. The clock conditioning circuit is capable of providing the desired clock signals with a reduced amount of jitter. Further, the clock conditioning circuit is capable of providing the desired clock signals without requiring an increase in frequency f_REF to reduce the amount of jitter. In this way, the clock conditioning circuit provides the desired clock signals without increasing the amount of power consumed by the signal processing system.

Examples of signal conditioning circuits include analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). An ADC converts an analog signal to a digital signal, and a DAC converts the digital signal to the analog signal. The ADC samples the analog signal at a sampling rate f_Sample, which determines the accuracy with which the analog signal is resolved and represented by the digital signal.

A sigma-delta modulator is another type of signal conditioning circuit. In one example, the sigma-delta modulator includes a quantizer which samples an analog input signal S_Input at sampling rate f_Sample of a first clock signal, and provides a corresponding digital output signal S_Output. The sigma-delta modulator includes a DAC which converts digital output signal S_Output at the sampling rate f_Sample of a second clock signal, and provides a converted analog input signal S_Converter in response. The sigma-delta modulator combines and filters signals S_Input and S_Converter, and provides the resultant signal to the quantizer so that it is sampled at sampling rate f_Sample. In general, digital output signal S_Output is a more accurate representation of analog input signal S_Input as the difference between signals S_Input and S_Converter decreases. Further, digital output signal S_Output is a less accurate representation of analog input signal S_Input as the difference between signals S_Input and S_Converter increases.

The quantizer samples analog input signal S_Input at sampling rate f_Sample, and the difference between signals S_Input and S_Converter depends on the phase difference between the first and second clock signals. Sampling rate f_Sample and the phase difference between the first and second clock signals determine the accuracy with which analog input signal S_Input is resolved and represented by digital output signal S_Output. In this way, the clock conditioning circuit drives the sigma-delta modulator.

The clock conditioning circuit disclosed herein is capable of providing the first and second clock signals with frequency f_Sample by down converting reference frequency f_REF. Further, the clock conditioning circuit is capable of adjusting the first and second clock signals by adjusting sampling rate f_Sample, as well as the phase difference between them. The clock conditioning circuit is capable of providing first and second clock signals having an asymmetric duty cycle, as well as providing first and second clock signal having a symmetric duty cycle.

The clock signal(s) provided by the clock conditioning circuit are related to a reference clock signal S_REF by an encoded clock signal S_ECLK. For example, the clock signal(s) provided by the clock conditioning circuit have a frequency (f) that is related to the frequency f_REF of reference clock signal S_REF by a fractional multiple N, wherein the fractional multiple is determined by encoded clock signal S_ECLK. The relationship between the frequencies of the clock signal and the reference clock signal S_REF is given by f=N×f_REF. The clock signal(s) provided by the clock conditioning circuit have a period that is related to the period T_REF of reference clock signal S_REF by the fractional multiple N. The relationship between the periods of the clock signal and the reference clock signal S_REF is given by T_REF=T×N.

In some signal processing systems, the available reference clock signals are at frequencies f_REF of 1248 MHz and 1456 MHz. Reference clock signals with frequencies f_REF of 1248 MHz and 1456 MHz are useful in telecommunications systems, such as cell phone networks. The clock conditioning circuit provides a clock signal having a frequency f that is related to frequency f_REF by the relationship f=N×f_REF. In one particular example, f_REF=1248 MHz and N= 1/12 so that f=104 MHz (1248 MHz/12=104 MHz). In another particular example, f_REF=1248 MHz and N= 1/13 so that f=96 MHz (1248/13=96 MHz). In one example, f_REF=1456 MHz and N= 1/15 so that f=97.067 MHz (1456/15=97.067 MHz). As discussed in more detail below, the reference clock signal provided to the signal processing system can be changed between reference clock signals having different reference frequencies.

The phase difference of the clock signal(s) provided by the clock conditioning circuit are related to reference clock signal S_REF by encoded clock signal S_ECLK. For example, the clock signal(s) provided by the clock conditioning circuit have a phase difference φ that is related to period T_REF of reference clock signal S_REF by fractional multiple N. Hence, the clock conditioning circuit is capable of adjusting the phase difference between the clock signals in response to an adjustment of encoded clock signal S_ECLK.

It should be noted that the clock signals discussed herein are digital signals which alternate between HI and LO states. For simplicity and ease of discussion, the digital signals each have one HI state and one LO state per local clock signal period, wherein the HI state corresponds with a logic ‘1’ and the LO state corresponds with a logic ‘0’. The digital signals each have one HI state and one LO state per local clock signal period so that there is one rising edge and one falling edge per local clock signal period. Hence, the local period of a digital signal begins at about its rising edge and terminates at about the next rising edge. It should also be noted that the clock conditioning circuit can be responsive to the rising or falling edges of the digital signal. For simplicity and ease of discussion, the clock conditioning circuit discussed herein is responsive to the rising edge of a digital signal. Some of the clock signals discussed herein have time varying periods. In general, the duration of the HI and LO states of clock signals having time varying periods vary from one local period to another.

FIG. 1 is a block diagram of one embodiment of a clock conditioning circuit 100. In this embodiment, clock conditioning circuit 100 receives encoded clock signal S_ECLK, and provides clock signals S_QCLK and S_DCLK in response. Clock signals S_QCLK and S_DCLK are related to reference clock signal S_REF by encoded clock signal S_ECLK, and can be used to drive another circuit, such as the sigma-delta modulator described above. For the sigma-delta modulator, clock signals S_QCLK and S_DCLK are provided to a quantizer and DAC, respectively, as discussed in more detail below with FIG. 16. The frequencies of clock signals S_QCLK and S_DCLK are the sampling frequency discussed above. In this way, clock signals S_QCLK and S_DCLK are used to sample an analog input signal at sampling rate f_Sample so that a corresponding digital output signal is provided in response.

As discussed in more detail below, clock conditioning circuit 100 is capable of adjusting a characteristic of clock signals S_QCLK and S_DCLK in response to receiving encoded clock signal S_ECLK. For example, clock conditioning circuit 100 is capable of adjusting the frequency and period of clock signals S_QCLK and S_DCLK in response to receiving encoded clock signal S_ECLK. Further, clock conditioning circuit 100 is capable of adjusting the duty cycles of clock signals S_QCLK and S_DCLK in response to receiving encoded clock signal S_ECLK. Clock conditioning circuit 100 is also capable of adjusting the phase difference between clock signals S_QCLK and S_DCLK in response to receiving encoded clock signal S_ECLK. Clock conditioning circuit 100 is capable of adjusting the symmetry of clock signals S_QCLK and S_DCLK in response to receiving encoded clock signal S_ECLK. In this way, encoded clock signal S_ECLK is encoded with information regarding the period, frequency, phase, symmetry and duty cycle of clock signals S_QCLK and S_DCLK.

Encoded clock signal S_ECLK is encoded so that clock signals S_QCLK and S_DCLK are related to reference clock signal S_REF. For example, the periods of clock signals S_QCLK and S_DCLK are related to the period of reference clock signal S_REF by encoded clock signal S_ECLK. Encoded clock signal S_ECLK has local periods with durations which correspond to a predetermined number of periods of reference clock signal S_REF. The number of periods of reference clock signal S_REF that correspond to the duration of a local period of encoded clock signal S_ECLK is adjustable. Adjacent local periods of encoded clock signal S_ECLK can have durations which correspond to a different number of periods of reference clock signal S_REF. In this way, adjacent local periods of encoded clock signal S_ECLK have durations which are adjustable relative to each other. Clock conditioning circuit 100 adjusts the periods of clock signals S_QCLK and S_DCLK in response to an adjustment of the period of encoded clock signal S_ECLK. The periods of clock signals S_QCLK and S_DCLK can be defined in many different ways. However, as mentioned above, each clock signal S_QCLK and S_DCLK has one HI state and one LO state per corresponding local clock signal period T.

FIG. 2 shows a graph 105 of one example of clock signals S_QCLK and S_DCLK verses time. In FIG. 2, the HI and LO states of clock signals S_QCLK and S_DCLK each have a duration of T/2. Further, each clock signal S_QCLK and S_DCLK has one HI state and one LO state per corresponding local clock signal period T. Each clock signal S_QCLK and S_DCLK has one HI state and one LO state per local clock signal period T so that there is one rising edge and one falling edge per local clock signal period T. Clock signals S_QCLK and S_DCLK are digital signals which alternate between HI and LO states.

Clock conditioning circuit 100 adjusts the periods of clock signals S_QCLK and S_DCLK in response to a change in the period of encoded clock signal S_ECLK. Clock conditioning circuit 100 increases the periods of clock signals S_QCLK and S_DCLK in response to an increase in the period of encoded clock signal S_ECLK. Further, clock conditioning circuit 100 decreases the periods of clock signals S_QCLK and S_DCLK in response to a decrease in the period of encoded clock signal S_ECLK. It should be noted that clock conditioning circuit 100 adjusts the frequency of clock signals S_QCLK and S_DCLK in response to an adjustment of the frequency of encoded clock signal S_ECLK because, as mentioned above, the frequency of a signal is related to its period (T) by the well-known relation f=1/T. More information regarding adjusting the periods of clock signals S_QCLK and S_DCLK in response to an adjustment of the period of encoded clock signal S_ECLK is provided below with FIGS. 6, 7 and 8.

The duty cycle of clock signals S_QCLK and S_DCLK are related to the period of encoded clock signal S_ECLK. The duty cycle of a signal can be defined in many different ways. For the signals discussed herein, the duty cycle is defined as the ratio of the duration of the HI state of the signal to the corresponding local signal period. In other situations, the duty cycle is defined as the ratio of the duration of the LO state of the signal to the corresponding local signal period. In FIG. 2, clock signals S_QCLK and S_DCLK each have a 50% duty cycle because clock signals S_QCLK and S_DCLK each have HI and LO states with durations of T/2, and the corresponding local signal period is T.

FIGS. 3 and 4 are graphs 106 and 107, respectively, of another example of clock signal S_QCLK verses time. In FIG. 3, clock signal S_QCLK has a duty cycle that is greater than 50% because its HI state has a duration greater than T/2 and its LO state has a duration less than T/2. In FIG. 4, clock signal S_QCLK has a duty cycle that is less than 50% because its HI state has a duration less than T/2 and its LO state has a duration greater than T/2.

Clock conditioning circuit 100 adjusts the duty cycle of clock signals S_QCLK and S_DCLK in response to a change in the local period of encoded clock signal S_ECLK. The change in the local period of encoded clock signal S_ECLK is a time-varying change, wherein the duration of each adjacent local period T_ECLKA and T_ECLKB of encoded clock signal S_ECLK is different. As mentioned above, a signal with a time varying period has adjacent local periods having HI and LO states with different durations. More information regarding an encoded clock signal S_ECLK with a non time-varying period is provided below with FIGS. 6, 7 and 8. More information regarding an encoded clock signal S_ECLK with a time-varying period is provided below with FIGS. 9 and 10.

Clock conditioning circuit 100 increases the duty cycle of clock signal S_QCLK in response to an increase in the ratio of local periods T_ECLKA to T_ECLKB (i.e. T_ECLKA/T_ECLKB increases), as discussed in more detail with FIG. 9. Further, clock conditioning circuit 100 decreases the duty cycle of clock signal S_QCLK in response to a decrease in the ratio of local periods T_ECLKA to T_ECLKB (i.e. T_ECLKA/T_ECLKB decreases), as discussed in more detail with FIG. 10.

It should be noted that a symmetric signal has a duty cycle that is equal to 50%, and an asymmetric signal has a duty cycle that is not equal to 50%. Hence, clock conditioning circuit 100 adjusts the symmetry of clock signals S_QCLK and S_DCLK in response to an adjustment of the local period of encoded clock signal S_ECLK. For example, the symmetry of clock signal S_QCLK can be changed from being symmetric to asymmetric in response to increasing and decreasing the difference between local periods T_ECLKA and T_ECLKB. Further, the symmetry of clock signal S_QCLK can be changed from being asymmetric to symmetric in response to driving the difference between local periods T_ECLKA and T_ECLKB to zero. As discussed in more detail below, local periods T_ECLKA and T_ECLKB are generally changed by increments equal to period T_REF of reference clock signal S_REF.

FIG. 5 is a graph 108 of complementary encoded clock signal S_ECLK, which has the opposite polarity of encoded clock signal S_ECLK. Complementary encoded clock signal S_ECLK has the opposite polarity of encoded clock signal S_ECLK because encoded clock signal S_ECLK has its HI state when encoded clock signal S_ECLK has its LO state, and encoded clock signal S_ECLK has its LO state when encoded clock signal S_QCLK has its HI state. Complementary encoded clock signal S_ECLK has the opposite polarity of encoded clock signal S_ECLK because encoded clock signal S_ECLK has a rising edge when encoded clock signal S_ECLK has a falling edge, and encoded clock signal S_ECLK has a falling edge when encoded clock signal S_ECLK has a rising edge. It should be noted that complementary encoded clock signal S_ECLK can be provided by providing encoded clock signal S_ECLK to the input of an inverter, as discussed in more detail with FIGS. 11 and 12.

Clock conditioning circuit 100 can be responsive to the rising or falling edges of the digital signal. However, in this embodiment, clock conditioning circuit 100 is responsive to a rising edge of a digital signal. Hence, it is useful to provide complementary encoded clock signal S_ECLK when it is desirable to have clock conditioning circuit 100 respond to a falling edge of encoded clock signal S_ECLK, such as when providing clock signal S_DCLK. Providing clock signal S_DCLK in response to a falling edge of encoded clock signal S_ECLK will be discussed in more detail with FIGS. 6, 7 and 8, as well as FIGS. 9 and 10.

The phase difference between clock signals S_QCLK and S_DCLK is shown in FIG. 2. In FIG. 2, clock signals S_QCLK and S_DCLK each have period T, and the phase difference between clock signals S_QCLK and S_DCLK is denoted as φ. The phase of clock signals S_QCLK and S_DCLK is typically determined relative to a reference clock signal, such as reference clock signal S_REF.

In general, the phase difference between clock signals S_QCLK and S_DCLK is related to the duration of the HI state of encoded clock signal S_ECLK. The phase difference between clock signals S_QCLK and S_DCLK is adjusted by clock conditioning circuit 100 in response to an adjustment of the duration of the HI state of encoded clock signal S_ECLK. For example, clock conditioning circuit 100 increases the phase difference between clock signals S_QCLK and S_DCLK in response to an increase in the duration of the HI state of encoded clock signal S_ECLK. Further, clock conditioning circuit 100 decreases the phase difference between clock signals S_QCLK and S_DCLK in response to a decrease in the duration of the HI state of encoded clock signal S_ECLK. Clock conditioning circuit 100 adjusts the phase of clock signal S_DCLK in response to a change in the phase of clock signal S_QCLK relative to the reference clock signal.

It should be noted that, in some situations, the phase difference between clock signals S_QCLK and S_DCLK is adjusted by clock conditioning circuit 100 in response to an adjustment of the duration of the LO state of encoded clock signal S_ECLK. In these situations, the clock conditioning circuit is responsive to the falling edge of the digital signal so that the phase difference between clock signals S_QCLK and S_DCLK is adjusted in response to an adjustment of the duration of the LO state of encoded clock signal S_ECLK. However, as mentioned above, the clock conditioning circuits discussed herein are responsive to the rising edge of the digital signal so that the phase difference between clock signals S_QCLK and S_DCLK is adjusted in response to an adjustment of the duration of the HI state of encoded clock signal S_ECLK.

It should also be noted that the phase difference φ between two signals corresponds to a time difference between them. For example, in FIG. 2, clock signal S_DCLK is shifted by a time T_Shift relative to clock signal S_QCLK. Hence, clock conditioning circuit 100 adjusts time T_Shift between clock signals S_QCLK and S_DCLK. Clock conditioning circuit 100 adjusts time T_Shift by delaying clock signal S_DCLK to drive the phase difference between clock signals S_QCLK and S_DCLK to a desired phase difference φ_Desired. Some examples of signals S_REF, S_ECLK, S_QCLK, S_DCLK and S_SYNC, as well as their relationship with one another, will be discussed in more detail presently.

FIG. 6 shows a timing diagram 110 having graphs 110a, 110b, 110c and 110d. Graph 110a shows reference clock signal S_REF verses time, wherein reference clock signal S_REF is periodic with period T_REF and frequency f_REF. Reference clock signal S_REF is a digital signal which has one HI state and one LO state per reference clock period T_REF. Reference clock signal S_REF has one rising edge and one falling edge per reference clock period T_REF. Hence, reference clock signal S_REF alternates between HI and LO states. Reference clock signal S_REF can have many different frequencies. For example, in some signal processing systems, frequency f_REF is 1248 MHZ or 1456 MHZ. However, frequency f_REF can have other frequency values, if desired.

Graph 110b shows one example of encoded clock signal S_ECLK1, wherein encoded clock signal S_ECLK1 is periodic with a local period T_ECLK1 and frequency f_ECLK1. In this embodiment, encoded clock signal S_ECLK1 is a digital signal which has one HI state and one LO state per encoded clock period T_ECLK1. Encoded clock signal S_ECLK1 has one rising edge and one falling edge per reference clock period T_ECLK1. Hence, encoded clock signal S_ECLK1 alternates between HI and LO states.

The duration of the HI and LO states of encoded clock signal S_ECLK1 correspond to a predetermined number of periods of reference clock signal S_REF. For example, in graph 110b, the HI state of encoded clock signal S_ECLK1 corresponds to three periods of reference clock signal S_REF because the HI state of encoded clock signal S_ECLK1 has a duration of 3×T_REF. Further, the LO state of encoded clock signal S_ECLK1 corresponds to three periods of reference clock signal S_REF because the LO state of encoded clock signal S_ECLK, has a duration of 3×T_REF. In this way, encoded clock signal S_ECLK1 is related to reference clock signal S_REF. It should be noted that the period T_ECLK1 of encoded clock signal S_ECLK1 is 6×T_REF because, as mentioned above, encoded clock signal S_ECLK1 has one HI state and one LO state per encoded clock period T_ECLK1.

It should also be noted that, in graph 110b, encoded clock signal S_ECLK1 is symmetric because its HI and LO states have the same number of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK1 of graph 110b correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 3×T_REF and the duration of the LO state is 3×T_REF.

Encoded clock signal S_ECLK1 has a non time-varying period because local period T_ECLK1 does not vary as a function of time. For example, as shown in graph 110b, encoded clock signal S_ECLK1 has HI and LO states with a duration of T_ECKLA, and HI and LO states with a duration of T_ECLKB. Further, the LO state of period T_ECKLA and the HI state of period T_ECLKB have a duration of T_ECLKC. The LO state of period T_ECKLB and the HI state of the next period have a duration of T_ECLKD. Encoded clock signal S_ECLK1 has a non time-varying period because local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD are equal to each other. It should be noted that local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD are each equal to local period T_ECLK1 for encoded clock signal S_ECLK1. It should also be noted that the global period of encoded clock signal S_ECLK1 is equal to its local period T_ECLK1.

Graphs 110c and 110d show clock signals S_QCLK1 and S_DCLK1, respectively, which are provided by clock conditioning system 100 (FIG. 1) in response to receiving encoded clock signal S_ECLK1. The HI and LO states of clock signals S_QCLK1 and S_DCLK1 correspond to the HI and LO states of encoded clock signal S_ECLK1. For example, the HI state of clock signal S_QCLK1 corresponds with local period T_ECLKA of encoded clock signal S_ECLK1. As mentioned above, local period T_ECLKA of encoded clock signal S_ECLK1 is 6×T_REF. Hence, the HI state of clock signal S_QCLK1 has a duration of 6×T_REF.

Further, the LO state of clock signal S_QCLK1 corresponds with local period T_ECLKB of encoded clock signal S_ECLK1. As mentioned above, local period T_ECLKB of encoded clock signal S_ECLK1 is 6×T_REF. Hence, the LO state of clock signal S_QCLK1 has a duration of 6×T_REF, and the period of clock signal S_QCLK1 is 12×T_REF. In this way, the HI and LO states of clock signals S_QCLK corresponds to the HI and LO states of encoded clock signal S_ECLK1, and clock signal S_QCLK1 is related to reference clock signal S_REF by encoded clock signal S_ECLK1.

It should be noted that, in graph 110c, clock signal S_QCLK1 is symmetric because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. Further, clock signal S_QCLK1 has a 50% duty cycle because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. The HI and LO states of clock signal S_QCLK1 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 6×T_REF and the duration of the LO state is 6×T_REF.

In graph 110d, the HI state of clock signal S_DCLK1 corresponds with local period T_ECLKC of encoded clock signal S_ECLK1. As mentioned above, local period T_ECLKC of encoded clock signal S_ECLK1 is 6×T_REF. Hence, the HI state of clock signal S_DCLK1 has a duration of 6×T_REF.

Further, the LO state of clock signal S_DCLK1 corresponds with local period T_ECLKD of encoded clock signal S_ECLK1. As mentioned above, local period T_ECLKD of encoded clock signal S_ECLK1 is 6×T_REF. Hence, the LO state of clock signal S_DCLK1 has a duration of 6×T_REF, and the period of clock signal S_DCLK1 is 12×T_REF. In this way, the HI and LO states of clock signals S_DCLK1 corresponds to the HI and LO states of encoded clock signal S_ECLK1, and clock signal S_DCLK1 is related to reference clock signal S_REF by encoded clock signal S_ECLK1.

It should be noted that, in graph 110d, clock signal S_DCLK1 is symmetric because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. Further, clock signal S_DCLK1 has a 50% duty cycle because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. The HI and LO states of clock signal S_DCLK1 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 6×T_REF and the duration of the LO state is 6×T_REF.

It should also be noted that clock signals S_QCLK1 and S_DCLK1 are phase shifted relative to each other so that the phase difference φ is non-zero. The phase difference φ between clock signals S_QCLK1 and S_DCLK1 corresponds with time shift T_Shift, as shown in FIG. 2. In this example, the value of time shift T_Shift corresponds with encoded clock signal S_ECLK1 because, as mentioned above, T_Shift corresponds with the HI state of encoded clock signal S_ECLK1. Time shift T_Shift corresponds with the HI state of encoded clock signal S_ECLK1 because T_Shift is equal to 3×T_REF and the HI state of encoded clock signal S_ECLK1 corresponds with 3×T_REF. The phase difference between clock signals S_QCLK1 and S_DCLK1 of FIG. 6 is 90° because encoded clock signal S_ECLK1 has a period of 6×T_REF and period T_Shift is equal to 3×T_REF, which is one-quarter of the local period of clock signals S_QCLK1 and S_DCLK1.

As mentioned above, the periods of clock signals S_QCLK and S_DCLK are related to the period of reference clock signal S_REF by encoded clock signal S_ECLK. The periods of clock signals S_QCLK and S_DCLK are related to the period of reference clock signal S_REF by encoded clock signal S_ECLK because clock conditioning circuit 100 adjusts the periods of clock signals S_QCLK and S_DCLK in response to an adjustment of the period of encoded clock signal S_ECLK. For example, clock conditioning circuit 100 increases the local periods of clock signals S_QCLK and S_DCLK in response to increasing the local period of encoded clock signal S_ECLK, as will be discussed with FIG. 7. Further, clock conditioning circuit 100 decreases the local periods of clock signals S_QCLK and S_DCLK in response to decreasing the local period of encoded clock signal S_ECLK, as will be discussed with FIG. 8.

FIG. 7 shows a timing diagram 112 having graphs 110a, 112b, 112c and 112d, which illustrate that the local periods of clock signals S_QCLK2 and S_DCLK2 are increased by clock conditioning circuit 100 in response to an increase of the local period of encoded clock signal S_ECLK1 of graph 110b. Graph 112b shows an encoded clock signal S_ECLK2, wherein encoded clock signal S_ECLK2 is periodic with a local period T_ECLK2 and frequency f_ECLK2. In graph 112b, the HI state of encoded clock signal S_ECLK2 corresponds to four periods of reference clock signal S_REF because the HI state of encoded clock signal S_ECLK2 has a duration of 4×T_REF. Further, the LO state of encoded clock signal S_ECLK2 corresponds to four periods of reference clock signal S_REF because the LO state of encoded clock signal S_ECLK2 has a duration of 4×T_REF. In this way, encoded clock signal S_ECLK is related to reference clock signal S_REF. It should be noted that the local period of encoded clock signal S_ECLK2 is 8×T_REF because, as mentioned above, encoded clock signal S_ECLK2 has one HI state and one LO state per encoded clock period T_ECLK. Hence, encoded clock signal S_ECLK2 has a period that is larger than encoded clock signal S_ECLK1 because period T_ECLK2 is larger than T_ECLK1.

It should also be noted that, in graph 112b, encoded clock signal S_ECLK2 is symmetric because its HI and LO states have the same number of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK2 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 4×T_REF and the duration of the LO state is 4×T_REF.

Encoded clock signal S_ECLK2 has a non time-varying period because local period T_ECLK2 does not vary as a function of time. For example, as shown in graph 112b, encoded clock signal S_ECLK2 has HI and LO states with a duration of T_ECKLA, and HI and LO states with a duration of T_ECLKB. Further, the LO state of period T_ECKLA and the HI state of period T_ECLKB have a duration of T_ECLKC. The LO state of period T_ECKLB and the HI state of the next period have a duration of T_ECLKD. Encoded clock signal S_ECLK2 has a non time-varying period because local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD are equal to each other. It should be noted that local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD are each equal to local period T_ECLK2 for encoded clock signal S_ECLK2. It should also be noted that the global period of encoded clock signal S_ECLK2 is equal to its local period T_ECLK2.

Graphs 112c and 112d show clock signals S_QCLK2 and S_DCLK2, respectively, which are provided by clock conditioning system 100 (FIG. 1) in response to receiving encoded clock signal S_ECLK2. The HI and LO states of clock signals S_QCLK2 and S_DCLK2 correspond to the HI and LO states of encoded clock signal S_ECLK2. For example, the HI state of clock signal S_QCLK2 corresponds with local period T_ECLKA of encoded clock signal S_ECLK2. As mentioned above, local period T_ECLKA of encoded clock signal S_ECLK2 is 8×T_REF. Hence, the HI state of clock signal S_QCLK2 has a duration of 8×T_REF.

Further, the LO state of clock signal S_QCLK2 corresponds with local period T_ECLKB of encoded clock signal S_ECLK2. As mentioned above, local period T_ECLKB of encoded clock signal S_ECLK2 is 8×T_REF. The LO state of clock signal S_QCLK2 has a duration of 8×T_REF, and the period of clock signal S_QCLK2 is 16×T_REF. Hence, the HI and LO states of clock signals S_QCLK2 corresponds to the HI and LO states of encoded clock signal S_ECLK2, and clock signal S_QCLK2 is related to reference clock signal S_REF. In this way, the period of clock signal S_QCLK is increased by clock conditioning circuit 100 in response to an increase of the local period of encoded clock signal S_ECLK.

It should be noted that, in graph 112c, clock signal S_QCLK2 is symmetric because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. Further, clock signal S_QCLK2 has a 50% duty cycle because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. The HI and LO states of clock signal S_QCLK2 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 8×T_REF and the duration of the LO state is 8×T_REF.

In graph 112d, the HI state of clock signal S_DCLK2 corresponds with local period T_ECLKC of encoded clock signal S_ECLK2. As mentioned above, local period T_ECLKC of encoded clock signal S_ECLK2 is 8×T_REF. Hence, the HI state of clock signal S_DCLK2 has a duration of 8×T_REF.

Further, the LO state of clock signal S_DCLK2 corresponds with local period T_ECLKD of encoded clock signal S_ECLK2. As mentioned above, local period T_ECLKD of encoded clock signal S_ECLK2 is 8×T_REF. The LO state of clock signal S_DCLK2 has a duration of 8×T_REF, and the period of clock signal S_DCLK2 is 16×T_REF. Hence, the HI and LO states of clock signals S_DCLK2 corresponds to the HI and LO states of encoded clock signal S_ECLK2, and clock signal S_DCLK2 is related to reference clock signal S_REF. In this way, the period of clock signal S_DCLK is increased by clock conditioning circuit 100 in response to an increase of the local period of encoded clock signal S_ECLK.

It should be noted that, in graph 112d, clock signal S_DCLK2 is symmetric because its HI and LO states correspond to the same number of periods of encoded clock signal S_ECLK2. Further, clock signal S_DCLK2 has a 50% duty cycle because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. The HI and LO states of clock signal S_DCLK2 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 8×T_REF and the duration of the LO state is 8×T_REF.

FIG. 8 shows a timing diagram 114 having graphs 110a, 114b, 114c and 114d, which illustrate that the local periods of clock signals S_QCLK and S_DCLK are decreased by clock conditioning circuit 100 in response to a decrease of the local period of encoded clock signal S_ECLK. Graph 114b shows an encoded clock signal S_ECLK3, wherein encoded clock signal S_ECLK3 is periodic with a local period T_ECLK3 and frequency f_ECLK3. In graph 114b, the HI state of encoded clock signal S_ECLK3 corresponds to two periods of reference clock signal S_REF because the HI state of encoded clock signal S_ECLK3 has a duration of 2×T_REF. Further, the LO state of encoded clock signal S_ECLK3 corresponds to two periods of reference clock signal S_REF because the LO state of encoded clock signal S_ECLK3 has a duration of 2×T_REF. In this way, encoded clock signal S_ECLK3 is related to reference clock signal S_REF. It should be noted that the local period of encoded clock signal S_ECLK3 is 4×T_REF because, as mentioned above, encoded clock signal S_ECLK3 has one HI state and one LO state per encoded clock period T_ECLK3.

It should also be noted that, in graph 114b, encoded clock signal S_ECLK3 is symmetric because its HI and LO states have the same number of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK3 of graph 114b correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 2×T_REF and the duration of the LO state is 2×T_REF.

Encoded clock signal S_ECLK3 has a non time-varying period because local period T_ECLK3 does not vary as a function of time. For example, as shown in graph 114b, encoded clock signal S_ECLK3 has HI and LO states with a duration of period T_ECKLA, and HI and LO states with a duration of period T_ECLKB. Further, the LO state of period T_ECKLA and the HI state of period T_ECLKB have a duration of T_ECLKC. The LO state of period T_ECKLB and the HI state of the next period have a duration of T_ECLKD. Encoded clock signal S_ECLK3 has a non time-varying period because local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD are equal to each other. It should be noted that local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD are each equal to local period T_ECLK3 for encoded clock signal S_ECLK3. It should also be noted that the global period of encoded clock signal S_ECLK3 is equal to its local period T_ECLK3.

Graphs 114c and 114d show clock signals S_QCLK3 and S_DCLK3, respectively, which are provided by clock conditioning system 100 (FIG. 1) in response to receiving encoded clock signal S_ECLK3. The HI and LO states of clock signals S_QCLK3 and S_DCLK3 correspond to the HI and LO states of encoded clock signal S_ECLK3. For example, the HI state of clock signal S_QCLK3 corresponds with local period T_ECLKA of encoded clock signal S_ECLK3. As mentioned above, local period T_ECLKA of encoded clock signal S_ECLK3 is 4×T_REF. Hence, the HI state of clock signal S_QCLK3 has a duration of 4×T_REF.

Further, the LO state of clock signal S_QCLK3 corresponds with local period T_ECLKB of encoded clock signal S_ECLK3. As mentioned above, local period T_ECLKB of encoded clock signal S_ECLK3 is 4×T_REF. The LO state of clock signal S_QCLK3 has a duration of 4×T_REF, and the period of clock signal S_QCLK3 is 8×T_REF. Hence, the HI and LO states of clock signals S_QCLK3 corresponds to the HI and LO states of encoded clock signal S_ECLK3, and clock signal S_QCLK3 is related to reference clock signal S_REF. In this way, the period of clock signal S_QCLK is decreased by clock conditioning circuit 100 in response to a decrease of the period of encoded clock signal S_ECLK.

It should be noted that, in graph 114c, clock signal S_QCLK3 is symmetric because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. Further, clock signal S_QCLK3 has a 50% duty cycle because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. The HI and LO states of clock signal S_QCLK3 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 4×T_REF and the duration of the LO state is 4×T_REF.

In graph 114d, the HI state of clock signal S_DCLK3 corresponds with local period T_ECLKC of encoded clock signal S_ECLK3. As mentioned above, local period T_ECLKC of encoded clock signal S_ECLK3 is 4×T_REF. Hence, the HI state of clock signal S_DCLK3 has a duration of 4×T_REF.

Further, the LO state of clock signal S_DCLK3 corresponds with local period T_ECLKD of encoded clock signal S_ECLK3. As mentioned above, local period T_ECLKD of encoded clock signal S_ECLK3 is 4×T_REF. The LO state of clock signal S_DCLK3 has a duration of 4×T_REF, and the period of clock signal S_DCLK3 is 8×T_REF. Hence, the HI and LO states of clock signals S_DCLK3 corresponds to the HI and LO states of encoded clock signal S_ECLK3, and clock signal S_DCLK3 is related to reference clock signal S_REF. In this way, the local period of clock signal S_DCLK is decreased by clock conditioning circuit 100 in response to a decrease of the local period of encoded clock signal S_ECLK.

It should be noted that, in graph 114d, clock signal S_DCLK3 is symmetric because its HI and LO states correspond to the same number of periods of encoded clock signal S_ECLK3. Further, clock signal S_DCLK3 has a 50% duty cycle because its HI and LO states correspond to the same number of periods of reference clock signal S_REF. The HI and LO states of clock signal S_DCLK3 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 4×T_REF and the duration of the LO state is 4×T_REF.

Thus, FIGS. 6, 7 and 8 illustrate that the local periods of clock signals S_QCLK and S_DCLK can be increased and decreased by clock conditioning circuit 100 in response to an increase and decrease, respectively, of the local period of encoded clock signal S_ECLK. In this way, encoded clock signal S_ECLK is encoded with information regarding the period of clock signals S_QCLK and S_DCLK.

As mentioned above, the phase difference between clock signals S_QCLK and S_DCLK is related to the duration of the HI state of encoded clock signal S_ECLK. The phase difference between clock signals S_QCLK and S_DCLK is adjusted by clock conditioning circuit 100 in response to an adjustment of the duration of the HI state of encoded clock signal S_ECLK. The adjustment of the duration of the HI state of encoded clock signal S_ECLK corresponds with an adjustment of time T_Shift between clock signals S_QCLK and S_DCLK. The phase difference φ between two signals corresponds to a time difference between them, as discussed in more detail with FIG. 2.

For example, in FIG. 6, the duration of the HI state of encoded clock signal S_ECLK1 is 3×T_REF, so that the value of time T_Shift is 3×T_REF. In FIG. 7, the duration of the HI state of encoded clock signal S_ECLK2 is 4×T_REF, so that the value of time T_Shift is 4×T_REF. Further, in FIG. 8, the duration of the HI state of encoded clock signal S_ECLK3 is 2×T_REF, so that the value of time T_Shift is 2×T_REF. Hence, the phase difference between clock signals S_QCLK and S_DCLK is adjusted by clock conditioning circuit 100 in response to an adjustment of the duration of the HI state of encoded clock signal S_ECLK. In this way, encoded clock signal S_ECLK is encoded with information regarding the phase difference between clock signals S_QCLK and S_DCLK. It should be noted that, for asymmetric clock signals, the phase difference between clock signals S_QCLK and S_DCLK is related to the duration of the HI state of encoded clock signal S_ECLK during period T_ECLKA. Although, in some situations, the phase difference between clock signals S_QCLK and S_DCLK can be related to the duration of the LO state of encoded clock signal S_ECLK during period T_ECLKA.

As mentioned above, the duty cycle of clock signals S_QCLK and S_DCLK are related to the local period of encoded clock signal S_ECLK. The duty cycle of clock signals S_QCLK and S_DCLK are related to the period of reference clock signal S_REF by encoded clock signal S_ECLK because clock conditioning circuit 100 adjusts the duty cycles of clock signals S_QCLK and S_DCLK in response to an adjustment of the local period of encoded clock signal S_ECLK. For example, the duty cycle of clock signal S_QCLK is increased by clock conditioning circuit 100 in response to an increase of the ratio of local period T_ECLKA to T_ECLKB (i.e. T_ECLKA/T_ECLKB increases), as will be discussed with FIG. 9. Further, the duty cycle of clock signal S_QCLK is decreased by clock conditioning circuit 100 in response to a decrease of the ratio of local period T_ECLKA to T_ECLKB (i.e. T_ECLKA/T_ECLKB decreases), as will be discussed with FIG. 10.

FIG. 9 shows a timing diagram 116 having graphs 110a, 116b, 116c and 116d, which illustrate that the duty cycles of clock signals S_QCLK and S_DCLK are increased by clock conditioning circuit 100 in response to an increase of the ratio of local period T_ECLKA to T_ECLKB and local period T_ECLKC to T_ECLKD, respectively. Graph 116b shows an encoded clock signal S_ECLK4, wherein encoded clock signal S_ECLK4 is periodic with a local period T_ECLK4 that varies between local periods T_ECLKA and T_ECLKB, and between local periods T_ECLKC and T_ECLKD. Hence, encoded clock signal S_ECLK4 has a time varying local period, wherein local period T_ECLK4 varies as a function of time. It should be noted that the global period of encoded clock signal S_ECLK4 is equal to the sum of local periods T_ECLKA and T_ECLKB. Further, the global period of encoded clock signal S_ECLK4 is equal to the sum of local periods T_ECLKC and T_ECLKD.

The HI state of encoded clock signal S_ECLK4 corresponds to three periods of reference clock signal S_REF in period T_ECLKA because the HI state of encoded clock signal S_ECLK4 in period T_ECLKA has a duration of 3×T_REF. Further, the LO state of encoded clock signal S_ECLK4 corresponds to four periods of reference clock signal S_REF in period T_ECLKA because the LO state of encoded clock signal S_ECLK4 in period T_ECLKA has a duration of 4×T_REF. It should be noted that local period T_ECLKA of encoded clock signal S_ECLK4 has a duration of 7×T_REF.

In graph 116b, the HI state of encoded clock signal S_ECLK4 corresponds to three periods of reference clock signal S_REF in period T_ECLKB because the HI state of encoded clock signal S_ECLK4 in period T_ECLKB has a duration of 3×T_REF. Further, the LO state of encoded clock signal S_ECLK4 corresponds to three periods of reference clock signal S_REF in period T_ECLKB because the LO state of encoded clock signal S_ECLK4 in period T_ECLKB has a duration of 3×T_REF. It should be noted that local period T_ECLKB of encoded clock signal S_ECLK4 has a duration of 6×T_REF.

In graph 116b, encoded clock signal S_ECLK4 is asymmetric in local period T_ECLKA because its HI and LO states have different numbers of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK4 correspond to a different number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state of local period T_ECLKA is 3×T_REF and the duration of the LO state of local period T_ECLKA is 4×T_REF-Further, in graph 116b, encoded clock signal S_ECLK4 is symmetric in local period T_ECLKB because its HI and LO states have the same number of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK4 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state of local period T_ECLKB is 3×T_REF and the duration of the LO state of local period T_ECLKB is 3×T_REF. Hence, encoded clock signal S_ECLK4 alternates between being asymmetric during local period T_ECLKA and symmetric during local period T_ECLKB. In this way, encoded clock signal S_ECLK4 has time varying local periods T_ECLKA and T_ECLKB, wherein the duration of the HI and LO states vary from one period to another. The duration of the HI and LO states change from one local period to an adjacent local period so that the symmetry of encoded clock signal S_ECLK4 changes from the one local period to the adjacent local period.

In graph 116b, encoded clock signal S_ECLK4 has local period T_ECLKC, which includes the LO state of local period T_ECLKA and the HI state of local period T_ECLKB. In this example, local period T_ECLKC is equal to T_ECLKA, so that local period T_ECLK4 does not vary between local periods T_ECLKA and T_ECLKC. Further, local period T_ECLKC is not equal to T_ECLKB, so that local period T_ECLK4 varies between local periods T_ECLKB and T_ECLKC. As discussed in more detail below, local period T_ECLKC corresponds with a HI state of clock signal S_DCLK.

In graph 116b, encoded clock signal S_ECLK4 has local period T_ECLKD, which includes the LO state of local period T_ECLKB and the HI state of the adjacent local period. In this example, local period T_ECLKD is equal to T_ECLKB, so that local period T_ECLK4 does not vary between local periods T_ECLKB and T_ECLKD. Further, local period T_ECLKD is not equal to T_ECLKA, so that local period T_ECLK4 varies between local periods T_ECLKA and T_ECLKD. As discussed in more detail below, local period T_ECLKD corresponds with a LO state of clock signal S_DCLK.

Graphs 116c and 116d show clock signals S_QCLK4 and S_DCLK4, respectively, which are provided by clock conditioning system 100 (FIG. 1) in response to receiving encoded clock signal S_ECLK4. The HI and LO states of clock signals S_QCLK4 and S_DCLK4 correspond to the HI and LO states of encoded clock signal S_ECLK4. For example, the HI state of clock signal S_QCLK4 corresponds with local period T_ECLKA of encoded clock signal S_ECLK4. As mentioned above, local period T_ECLKA of encoded clock signal S_ECLK4 is 7×T_REF. Hence, the HI state of clock signal S_QCLK4 has a duration of 7×T_REF.

Further, the LO state of clock signal S_QCLK4 corresponds with local period T_ECLKB of encoded clock signal S_ECLK4. As mentioned above, local period T_ECLKB of encoded clock signal S_ECLK4 is 6×T_REF. Hence, the LO state of clock signal S_QCLK4 has a duration of 6×T_REF, and local period T_QCLK4 of clock signal S_QCLK4 is 13×T_REF. In this way, the HI and LO states of clock signals S_QCLK4 corresponds to the HI and LO states of encoded clock signal S_ECLK4, and clock signal S_QCLK4 is related to reference clock signal S_REF by encoded clock signal S_ECLK4.

It should be noted that, in graph 116c, clock signal S_QCLK4 is asymmetric because its HI and LO states correspond to a different number of periods of reference clock signal S_REF. Further, clock signal S_QCLK4 has a duty cycle that is greater than 50% because its HI state corresponds to a larger number of reference clock periods T_REF than its LO state. The HI state of clock signal S_QCLK4 corresponds to a larger number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 7×T_REF and the duration of the LO state is 6×T_REF. In this particular example, the duty cycle of clock signal S_QCLK4 is 7/13, which corresponds to a duty cycle of about 53.8%.

In graph 116d, the HI state of clock signal S_DCLK4 corresponds with local period T_ECLKC of encoded clock signal S_ECLK4. As mentioned above, local period T_ECLKC of encoded clock signal S_ECLK4 is equal to local period T_ECLKA, and local period T_ECLKA is 7×T_REF. Hence, the HI state of clock signal S_DCLK4 has a duration of 7×T_REF.

Further, the LO state of clock signal S_DCLK4 corresponds with local period T_ECLKD of encoded clock signal S_ECLK4. As mentioned above, local period T_ECLKD of encoded clock signal S_ECLK4 is 6×T_REF. Hence, the LO state of clock signal S_DCLK4 has a duration of 6×T_REF, and the period of clock signal S_DCLK4 is 13×T_REF. In this way, the HI and LO states of clock signal S_DCLK4 corresponds to the HI and LO states of encoded clock signal S_ECLK4, and clock signal S_DCLK4 is related to reference clock signal S_REF by encoded clock signal S_ECLK4.

It should be noted that, in graph 116d, clock signal S_DCLK4 is asymmetric because its HI and LO states correspond to a different number of periods of reference clock signal S_REF. Further, clock signal S_DCLK4 has a duty cycle that is greater than 50% because its HI state corresponds to a larger number of reference clock periods T_REF than its LO state. The HI state of clock signal S_DCLK4 corresponds to a larger number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 7×T_REF and the duration of the LO state is 6×T_REF. In this particular example, the duty cycle of clock signal S_DCLK4 is 7/13, which corresponds to a duty cycle of about 53.8%.

FIG. 10 shows a timing diagram 118 having graphs 110a, 118b, 118c and 118d, which illustrate that the duty cycles of clock signals S_QCLK and S_DCLK are decreased by clock conditioning circuit 100 in response to a decrease of the ratio of local period T_ECLKA to T_ECLKB and local period T_ECLKC to T_ECLKD, respectively. Graph 118b shows an encoded clock signal S_ECLK5, wherein encoded clock signal S_ECLK5 is periodic with a local period T_ECLK5 that varies between periods T_ECLKA to T_ECLKB, and between periods T_ECLKC to T_ECLKD. Hence, encoded clock signal S_ECLK5 has a time varying local period, wherein local period T_ECLK5 varies as a function of time. It should be noted that the global period of encoded clock signal S_ECLK5 is equal to the sum of local periods T_ECLKA and T_ECLKB. Further, the global period of encoded clock signal S_ECLK5 is equal to the sum of local periods T_ECLKC and T_ECLKD.

The HI state of encoded clock signal S_ECLK5 corresponds to three periods of reference clock signal S_REF in period T_ECLKA because the HI state of encoded clock signal S_ECLK5 in period T_ECLKA has a duration of 3×T_REF. Further, the LO state of encoded clock signal S_ECLK5 corresponds to three periods of reference clock signal S_REF in period T_ECLKB because the LO state of encoded clock signal S_ECLK5 in period T_ECLKA has a duration of 3×T_REF. It should be noted that local period T_ECLKA of encoded clock signal S_ECLK5 is 6×T_REF.

In graph 118b, the HI state of encoded clock signal S_ECLK5 corresponds to three periods of reference clock signal S_REF in period T_ECLKB because the HI state of encoded clock signal S_ECLK5 in period T_ECLKB has a duration of 3×T_REF. Further, the LO state of encoded clock signal S_ECLK5 corresponds to four periods of reference clock signal S_REF in period T_ECLKB because the LO state of encoded clock signal S_ECLK5 in period T_ECLKB has a duration of 4×T_REF. It should be noted that local period T_ECLKB encoded clock signal S_ECLK5 has a duration of 7×T_REF.

In graph 118b, encoded clock signal S_ECLK5 is symmetric in local period T_ECLKA because its HI and LO states have the same number of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK5 correspond to the same number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state of local period T_ECLKA is 3×T_REF and the duration of the LO state of local period T_ECLKA is 3×T_REF.

Further, in graph 118b, encoded clock signal S_ECLK5 is asymmetric in local period T_ECLKB because its HI and LO states have a different number of periods of reference clock signal S_REF. The HI and LO states of encoded clock signal S_ECLK5 have a different number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state of local period T_ECLKB is 3×T_REF and the duration of the LO state of local period T_ECLKB is 4×T_REF. Hence, encoded clock signal S_ECLK5 alternates between being symmetric during local period T_ECLKA and asymmetric during local period T_ECLKB. In this way, encoded clock signal S_ECLK5 has time varying local periods T_ECLKA and T_ECLKB, wherein the duration of the HI and LO states vary from one period to another. The duration of the HI and LO states change from one local period to an adjacent local period so that the symmetry of encoded clock signal S_ECLK5 changes from the one local period to the adjacent local period.

In graph 118b, encoded clock signal S_ECLK5 has local period T_ECLKC, which includes the LO state of local period T_ECLKA and the HI state of local period T_ECLKB. In this example, local period T_ECLKC is equal to local period T_ECLKA, so local that period T_ECLK5 does not vary between local periods T_ECLKA and T_ECLKC. Further, local period T_ECLKC is not equal to T_ECLKB, so that local period T_ECLK5 varies between local periods T_ECLKB and T_ECLKC. As discussed in more detail below, local period T_ECLKC corresponds with a HI state of clock signal S_DCLK.

In graph 118b, encoded clock signal S_ECLK5 has local period T_ECLKD, which includes the LO state of local period T_ECLKB and the HI state of the adjacent local period. In this example, local period T_ECLKD is equal to local period T_ECLKB, so that local period T_ECLK5 does not vary between local periods T_ECLKB and T_ECLKD. Further, local period T_ECLKD is not equal to local period T_ECLKA, so that local period T_ECLK5 varies between local periods T_ECLKA and T_ECLKD. As discussed in more detail below, local period T_ECLKD corresponds with a LO state of clock signal S_DCLK.

Graphs 118c and 118d show clock signals S_QCLK5 and S_DCLK5, respectively, which are provided by clock conditioning system 100 (FIG. 1) in response to receiving encoded clock signal S_ECLK5. The HI and LO states of clock signals S_QCLK5 and S_DCLK5 correspond to the HI and LO states of encoded clock signal S_ECLK5. For example, the HI state of clock signal S_QCLK5 corresponds with local period T_ECLKA of encoded clock signal S_ECLK5. As mentioned above, local period T_ECLKA of encoded clock signal S_ECLK5 is 6×T_REF. Hence, the HI state of clock signal S_QCLK5 has a duration of 6×T_REF.

Further, the LO state of clock signal S_QCLK5 corresponds with period T_ECLKB of encoded clock signal S_ECLK5. As mentioned above, local period T_ECLKB of encoded clock signal S_ECLK5 is 7×T_REF. Hence, the LO state of clock signal S_QCLK5 has a duration of 7×T_REF, and local period T_QCLK5 of clock signal S_QCLK5 is 13×T_REF. In this way, the HI and LO states of clock signal S_QCLK5 corresponds to the HI and LO states of encoded clock signal S_ECLK5, and clock signal S_QCLK5 is related to reference clock signal S_REF by encoded clock signal S_ECLK5.

It should be noted that, in graph 118c, clock signal S_QCLK5 is asymmetric because its HI and LO states correspond to a different number of periods of reference clock signal S_REF. Further, clock signal S_QCLK5 has a duty cycle that is less than 50% because its HI state corresponds to a smaller number of reference clock periods T_REF than its LO state. The HI state of clock signal S_QCLK5 corresponds to a smaller number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 6×T_REF and the duration of the LO state is 7×T_REF. In this particular example, the duty cycle of clock signal S_QCLK5 is 6/13, which corresponds to a duty cycle of about 46.2%.

In graph 118d, the HI state of clock signal S_DCLK5 corresponds with local period T_ECLKC of encoded clock signal S_ECLK5. As mentioned above, local period T_ECLKC of encoded clock signal S_ECLK5 is equal to local period T_ECLKA, and local period T_ECLKA is 6×T_REF. Hence, the HI state of clock signal S_DCLK5 has a duration of 6×T_REF.

Further, the LO state of clock signal S_DCLK5 corresponds with local period T_ECLKD of encoded clock signal S_ECLK5. As mentioned above, local period T_ECLKD of encoded clock signal S_ECLK5 is 7×T_REF. Hence, the LO state of clock signal S_DCLK5 has a duration of 7×T_REF, and the period of clock signal S_DCLK5 is 13×T_REF. In this way, the HI and LO states of clock signal S_DCLK5 corresponds to the HI and LO states of encoded clock signal S_ECLK5, and clock signal S_DCLK5 is related to reference clock signal S_REF by encoded clock signal S_ECLK5

It should be noted that, in graph 118d, clock signal S_DCLK5 is asymmetric because its HI and LO states correspond to a different number of periods of reference clock signal S_REF. Further, clock signal S_DCLK5 has a duty cycle that is less than 50% because its HI state corresponds to a smaller number of reference clock periods T_REF than its LO state. The HI state of clock signal S_DCLK5 corresponds to a smaller number of periods of reference clock signal S_REF because, as mentioned above, the duration of the HI state is 6×T_REF and the duration of the LO state is 7×T_REF. In this particular example, the duty cycle of clock signal S_DCLK5 is 6/13, which corresponds to a duty cycle of about 46.2%.

Thus, clock conditioning circuit 100 adjusts the duty cycle of clock signals S_QCLK and S_DCLK in response to a change in a local period of encoded clock signal S_ECLK. The change in the period of encoded clock signal S_ECLK is a time-varying change, wherein the duration of each adjacent local period T_ECLKA and T_ECLKB of encoded clock signal S_ECLK changes so that the ratio of local periods T_ECLKA to T_ECLKB changes (i.e. T_ECLKA/T_ECLKB changes).

Clock conditioning circuit 100 increases the duty cycle of clock signal S_QCLK in response to an increase in the ratio of local period T_ECLKA to T_ECLKB (i.e. T_ECLKA/T_ECLKB increases). Clock conditioning circuit 100 increases the duty cycle of clock signal S_DCLK in response to an increase in the ratio of local period T_ECLKC to T_ECLKD (i.e. T_ECLKC/T_ECLKD increases). For example, local periods T_ECLKA, T_ECLKB, T_ECLKC and T_ECLKD have durations of 6×T_REF for encoded clock signal S_ECLK1 of FIG. 6, so that clock signals S_QCLK1 and S_DCLK1 have a duty cycle of 50%. However, local periods T_ECLKA and T_ECLKB have durations of 7×T_REF and 6×T_REF, respectively, for encoded clock signal S_ECLK4 of FIG. 9, so that clock signal S_QCLK4 has a duty cycle of 53.8%. Similarly, local periods T_ECLKC and T_ECLKD have durations of 7×T_REF and 6×T_REF, respectively, for encoded clock signal S_ECLK4 of FIG. 9, so that clock signal S_DCLK4 has a duty cycle of 53.8%. Thus, FIGS. 6 and 9 illustrate that the duty cycles of clock signals S_QCLK and S_DCLK are increased by clock conditioning circuit 100 in response to an increase of the ratio of local period T_ECLKA to T_ECLKB and local period T_ECLKC to T_ECLKD of encoded clock signal S_ECLK.

Further, clock conditioning circuit 100 decreases the duty cycle of clock signals S_QCLK and S_DCLK in response to a decrease in the ratio of local period T_ECLKA to T_ECLKB (i.e. T_ECLKA/T_ECLKB decreases) and local period T_ECLKC to T_ECLKD (i.e. T_ECLKC/T_ECLKD decreases), as discussed in more detail with FIG. 10. For example, local periods T_ECLKA, T_ECLKB T_ECLKC and T_ECLKD have durations of 6×T_REF for encoded clock signal S_ECLK1 of FIG. 6, so that clock signals S_QCLK1 and S_DCLK1 have a duty cycle of 50%. However, local periods T_ECLKA and T_ECLKB have durations of 6×T_REF and 7×T_REF, respectively, for encoded clock signal S_ECLK5 of FIG. 10, so that clock signal S_QCLK5 has a duty cycle of 46.2%. Similarly, local periods T_ECLKC and T_ECLKD have durations of 6×T_REF and 7×T_REF, respectively, for encoded clock signal S_ECLK5 of FIG. 10, so that clock signal S_DCLK5 has a duty cycle of 46.2%. Thus, FIGS. 6 and 10 illustrate that the duty cycles of clock signals S_QCLK and S_DCLK are decreased by clock conditioning circuit 100 in response to a decrease of the ratio of local period T_ECLKA to T_ECLKB and local period T_ECLKC to T_ECLKD of encoded clock signal S_ECLK. In this way, encoded clock signal S_ECLK is encoded with information regarding the duty cycles of clock signals S_QCLK and S_DCLK.

As mentioned above, for asymmetric clock signals, the phase difference between clock signals S_QCLK and S_DCLK is related to the duration of the HI state of encoded clock signal S_ECLK during local period T_ECLKA. The phase difference between clock signals S_QCLK and S_DCLK is adjusted by clock conditioning circuit 100 in response to an adjustment of the duration of the HI state of encoded clock signal S_ECLK during local period T_ECLKA. The adjustment of the duration of the HI state of encoded clock signal S_ECLK during local period T_ECLKA corresponds with an adjustment of a time T_Shift between clock signals S_QCLK and S_DCLK.

For example, in FIG. 9, the duration of the HI state of encoded clock signal S_ECLK4 is 3×T_REF. Hence, the value of time T_Shift is 3×T_REF. If the duration of the HI state of encoded clock signal S_ECLK4 is 4×T_REF, the value of time T_Shift is 4×T_REF. If the duration of the HI state of encoded clock signal S_ECLK4 is 2×T_REF, the value of time T_Shift is 2×T_REF. In FIG. 10, the duration of the HI state of encoded clock signal S_ECLK5 is 3×T_REF. Hence, the value of time T_Shift is 3×T_REF. If the duration of the HI state of encoded clock signal S_ECLK5 is 4×T_REF, the value of time T_Shift is 4×T_REF. If the duration of the HI state of encoded clock signal S_ECLK5 is 2×T_REF, the value of time T_Shift is 2×T_REF.

Hence, the phase difference between clock signals S_QCLK and S_DCLK is adjusted by clock conditioning circuit 100 in response to an adjustment of the duration of the HI state of encoded clock signal S_ECLK during local period T_ECLKA. In this way, encoded clock signal S_ECLK is encoded with information regarding the phase difference between clock signals S_QCLK and S_DCLK.

FIG. 11 is a circuit diagram 120a of one embodiment of clock conditioning circuit 100. In this embodiment, clock conditioning circuit 100 includes an encoding circuit 130a which includes D flip-flops 131 and 132. It should be noted that D flip-flops 131 and 132 are edge triggered D flip-flops. Further, D flip-flops 131 and 132 are triggered by the rising edge of a digital signal because, as mentioned above, clock conditioning circuit 100 is responsive to the rising edges of the digital signal. D flip-flops 131 and 132 are triggered by the falling edge of the digital signal in embodiments in which clock conditioning circuit 100 is responsive to the falling edges of the digital signal.

The clock input terminal of D flip-flop 131 receives encoded clock signal S_ECLK, and the clock input terminal of D flip-flop 132, receives encoded clock signal S_ECLK through an output terminal of an inverter 133. In this way, D flip-flop 131 is clocked by encoded clock signal S_ECLK and D flip-flop 132 is clocked by the complement of encoded clock signal S_ECLK, which is denoted as S_ECLK. More information regarding clock signals S_ECLK and S_ECLK is provided above with the discussion of FIG. 5. It should be noted that the clock inputs of D flip-flops 131 and 132 are denoted as C in circuit diagram 120a.

Data input terminal of D flip-flop 131 is connected to its Q output terminal, and its Q output terminal is connected to the data input terminal of D flip-flop 132. Data input terminals of D flip-flops 131 and 132 are denoted as D in circuit diagram 120a. The Q output terminal of D flip-flop 131 is connected to the data input terminal of D flip-flop 132 so that D flip-flop 131 drives the operation of D flip-flop 132. The Q output terminals of D flip-flops 131 and 132 provide clock signals S_QCLK and S_DCLK, respectively. Some examples of encoded clock signal S_ECLK and clock signals S_QCLK and S_DCLK are discussed in more detail above with FIGS. 6, 7, 8, 9 and 10.

In operation, D flip-flops 131 and 132 are connected together so that the periods of clock signals S_QCLK and S_DCLK are adjusted in response to receiving encoded clock signal S_ECLK and complementary encoded clock signal S_ECLK. Further, D flip-flops 131 and 132 are connected together so that the duty cycles of clock signals S_QCLK and S_DCLK are adjusted in response to receiving encoded clock signal S_ECLK and complementary encoded clock signal S_ECLK. D flip-flops 131 and 132 are connected together so that the phase difference between clock signals S_QCLK and S_DCLK is adjusted in response to receiving encoded clock signal S_ECLK and complementary encoded clock signal S_ECLK. In this way, encoded clock signal S_ECLK is encoded with information regarding the period, duty cycle and phases of clock signals S_QCLK and S_DCLK. More information regarding the adjustment of the period, duty cycle and phases of clock signals S_QCLK and S_DCLK is provided above with the discussion of FIGS. 6, 7, 8, 9 and 10.

In this embodiment, circuit 120a includes a synchronization circuit 140, which is connected to the reset terminals of D flip-flops 131 and 132. The reset terminals of D flip-flops 131 and 132 are denoted as R in circuit diagram 120a. As will be discussed in more detail with FIG. 13, synchronization circuit 140 provides a reset signal S_Reset to the reset terminals of D flip-flops 131 and 132. Reset signal S_Reset is a digital signal which resets D flip-flops 131 and 132 in response to reset signal S_Reset transitioning from a LO state to a HI state. The Q outputs of D flip-flops 131 and 132 are driven to a predetermined value in response to reset signal S_Reset transitioning between the LO and HI states. In some embodiments, the Q outputs of D flip-flops 131 and 132 are driven to the same value. In this embodiment, the Q outputs of D flip-flops 131 and 132 are driven to LO states. In other embodiments, the Q outputs of D flip-flops 131 and 132 are driven to HI states. In some embodiments, reset signal S_Reset is a digital signal which resets D flip-flops 131 and 132 in response to reset signal S_Reset transitioning from a HI state to a LO state.

In this embodiment, synchronization circuit 140 includes an AND gate 141 with an output terminal connected to an input terminal of an OR gate 142. One input terminal of AND gate 141 receives synchronization signal S_SYNC, and another input terminal of AND gate 141 receives signal S_ECLK. It should be noted that, in some embodiments, signal S_ECLK is provided to the corresponding input terminal of AND gate 141 by the output terminal of inverter 133. The output terminal of OR gate 142 is connected to the reset terminals of D flip-flops 131 and 132.

Another input terminal of OR gate 142 operates as a battery save (BS) terminal, which powers down encoding circuit 130a in response to an indication from a battery save signal S_BS. It is desirable to power down encoding circuit 130a in many different situations, such as in a mobile application when clock conditioning circuit 100 is not being used. In mobile applications, it is desirable to conserve battery power.

D flip-flops 131 and 132 are not responsive to encoded clock signal S_ECLK when the reset terminals receive a HI state of a signal. Further, D flip-flops 131 and 132 are responsive to encoded clock signal S_ECLK when the reset terminals receive a LO state of a signal. The reset terminals of D flip-flops 131 and 132 receive a HI state of a signal in response to receiving a HI state of battery save signal S_BS. The reset terminals of D flip-flops 131 and 132 receive a LO state of a signal in response to receiving a LO state of battery save signal S_BS and a LO state of AND gate 141. In this way, synchronization circuit 140 operates as a battery save circuit.

Synchronization circuit 140 adjusts the phase difference between clock signals S_QCLK and S_DCLK. In the graphs of FIGS. 6, 7, 8, 9 and 10, the phase difference between clock signals S_QCLK and S_DCLK is such that clock signal S_QCLK leads clock signal S_DCLK. It is desirable for clock signal S_QCLK to lead clock signal S_DCLK in situations in which clock signal S_QCLK is used to drive a quantizer of a sigma-delta modulator and clock signal S_DCLK is used to drive a DAC.

However, it should be appreciated that the phase difference between clock signals S_QCLK and S_DCLK is generally unknown at start-up when clock conditioning circuit 100 is turned on. For example, in some situations, clock signal S_QCLK desirably leads clock signal S_DCLK in response to turning on clock conditioning circuit 100 and, in other situations, clock signal S_QCLK undesirably lags clock signal S_DCLK in response to turning on clock conditioning circuit 100.

In situations in which clock signal S_QCLK undesirably lags clock signal S_DCLK, synchronization circuit 140 ensures that clock signal S_QCLK moves from a lagging state to a leading state after clock conditioning circuit 100 has been turned on. In this way, synchronization circuit 140 ensures that clock signal S_QCLK desirably leads clock signal S_DCLK.

The phase difference between clock signals S_QCLK and S_DCLK can be undesirably changed in response to a change in the reference clock signal provided to the signal conditioning system. As mentioned above, in some signal processing systems, the available reference clock signals are at different frequencies, such as 1248 MHz and 1456 MHz. Hence, in some situations, the reference clock signal provided to the signal conditioning system is changed between reference clock signals having frequencies f_REF of 1248 MHz and 1456 MHz. In some of these situations, clock signal S_QCLK desirably leads clock signal S_DCLK in response to changing between reference clock signals having frequencies f_REF of 1248 MHz and 1456 MHz.

In other situations, clock signal S_QCLK undesirably lags clock signal S_DCLK in response to changing between reference clock signals having frequencies f_REF of 1248 MHz and 1456 MHz. In situations in which clock signal S_QCLK undesirably lags clock signal S_DCLK, synchronization circuit 140 ensures that clock signal S_QCLK moves from a lagging state to a leading state after the change in the reference clock signal provided to the signal conditioning system. In this way, synchronization circuit 140 ensures that clock signal S_QCLK desirably leads clock signal S_DCLK. The operation of synchronization circuit 140 will be discussed in more detail with FIG. 13.

FIG. 12 is a circuit diagram 120b of another embodiment of clock conditioning circuit 100. In this embodiment, clock conditioning circuit 100 includes an encoding circuit 130b which includes D flip-flops 131 and 132. The clock input terminal of D flip-flop 131 receives encoded clock signal S_ECLK, and the clock input terminal of D flip-flop 132, receives encoded clock signal S_ECLK through inverter 133. In this way, D flip-flop 131 is clocked by encoded clock signal S_ECLK and D flip-flop 132 is clocked by the complement of encoded clock signal S_ECLK, which is denoted as S_ECLK.

The data input terminal of D flip-flop 131 is connected to its Q output terminal, and the data input terminal of D flip-flop 132 is connected to its Q output terminal. The Q output terminal of D flip-flop 131 is not connected to the data input terminal of D flip-flop 132 so that D flip-flop 131 does not drive the operation of D flip-flop 132. The Q output terminals of D flip-flops 131 and 132 provide clock signals S_QCLK and S_DCLK, respectively.

In this embodiment, circuit 120b includes synchronization circuit 140, which is connected to the reset input terminals of D flip-flops 131 and 132. The operation of synchronization circuit 140 will be discussed in more detail presently.

Clock conditioning circuit 100 embodied in circuit diagrams 120a and 120b of FIGS. 11 and 12, respectively, provides clock signals S_QCLK and S_DCLK, which are down converted from reference signal S_REF, and phase-shifted relative to each other. Clock conditioning circuit 100 of circuit diagrams 120a and 120b include less complicated and less expensive circuitry, and better controls the frequency of clock signals S_QCLK and S_DCLK, as well as the phase difference between them. Clock conditioning circuit 100 of circuit diagrams 120a and 120b is capable of providing clock signals S_QCLK and S_DCLK with a reduced amount of jitter. Further, clock conditioning circuit 100 of circuit diagrams 120a and 120b is capable of providing clock signals S_QCLK and S_DCLK without requiring an increase in frequency f_REF to reduce the amount of jitter. In this way, clock conditioning circuit 100 of circuit diagrams 120a and 120b provides clock signals S_QCLK and S_DCLK without increasing the amount of power consumed.

FIG. 13 is a timing diagram 119 having graphs 114b, 114c and 114d of FIG. 8, as well as a graph 117a showing a synchronization signal S_SYNC1 verses time. Synchronization circuit 140 and synchronization signal S_SYNC1 are used to reset clock conditioned signals S_QCLK and S_DCLK once per local period to ensure that the phase difference between clock signals S_QCLK and S_DCLK is driven to be the desired phase difference within one local period of clock conditioned signals S_QCLK and S_DCLK.

In timing diagram 119, it is assumed that, at start-up, clock signal S_QCLK undesirably lags clock signal S_DCLK by a phase difference of φ_Undesired, as indicated in graph 114c of timing diagram 119. Synchronization signal S_SYNC1 is a periodic digital signal having a HI state at the transition between the HI and LO states of encoded clock signal S_ECLK3 during local period T_ECLKB. Hence, in this example, synchronization signal S_SYNC has a HI state at the falling edge of the HI state of encoded clock signal S_ECLK3 of local period T_ECLKB. Hence, the HI state of synchronization signal S_SYNC1 has a duration during the HI and LO states of encoded clock signal S_ECLK3. It should be noted that the duration of the HI state of synchronization signal S_SYNC1 is less than local period T_ECLKB so that synchronization signal S_SYNC1 has a LO state during local period T_ECLKA.

The corresponding input terminal of AND gate 141 (FIGS. 11 and 12) provides a HI indication in response to the HI state of synchronization signal S_SYNC1. The other input terminal of AND gate 141 receives complementary encoded clock signal S_ECLK, as shown in FIGS. 11 and 12. Hence, the other input terminal of AND gate 141 receives a signal which transitions from LO to HI in response to encoded clock signal S_ECLK3 transitioning from HI to LO during local period T_ECLKB.

A signal provided by the output terminal of AND gate 141 transitions from LO to HI states in response to encoded clock signal S_ECLK3 transitioning from HI to LO states during local period T_ECLKB. As mentioned above with FIGS. 11 and 12, the output terminal of AND gate 141 is connected to a corresponding input terminal of OR gate 142. Hence, the signal provided by the output terminal of OR gate 142 transitions from LO to HI state in response to the signal provided by the output terminal of AND gate 141 transitioning from LO to HI state.

Reset signal S_Reset is provided by the output terminal of OR gate 142, which is connected to the reset terminals of flip-flops 131 and 132. Hence, reset signal S_Reset transitions from LO to HI states in response to the signal provided by the output terminal of AND gate 141 transitioning from LO to HI states. Reset signal S_Reset resets D flip-flops 131 and 132 in response to reset signal S_Reset transitioning from LO to HI states. Clock signals S_QCLK and S_DCLK provided by the Q output terminals of D flip-flops 131 and 132, respectively, are driven to LO states in response to D flip-flops 131 and 132 being reset.

As mentioned above, the duration of the HI state of synchronization signal S_SYNC1 is less than local period T_ECLKB. The duration of the HI state of synchronization signal S_SYNC1 is less than local period T_ECLKB so that reset signal S_Reset transitions from a HI state to a LO state before the adjacent local period T_ECLKA of encoded clock signal S_ECLK3 begins. It is desirable for reset signal S_Reset to transition from a HI state to a LO state before the adjacent local period T_ECLKA of encoded clock signal S_ECLK3 begins so that D flip-flops 131 and 132 will be responsive to the transitions of encoded clock signal S_ECLK of the adjacent local period T_ECLKA.

Clock signal S_QCLK3 has a rising edge at the first rising edge of encoded clock signal S_ECLK3 after the HI state of synchronization signal S_SYNC1, as shown in graph 114c of timing diagram 119. The rising edge of clock signal S_QCLK3 at the first rising edge of encoded clock signal S_ECLK3 after the HI state of synchronization signal S_SYNC1 corresponds with the rising edge of the HI state of clock signal S_QCLK3 during local period T_ECLKA.

After synchronization signal S_SYNC1 transitions from the HI to the LO state of local period T_ECLKB, and before the next local period T_ECLKA, clock conditioning circuit 100 provides clock signals S_QCLK3 and S_DCLK3, as discussed in more detail above with FIG. 8. Hence, clock signal S_DCLK3 has a rising edge at the first falling edge of encoded clock signal S_ECLK3 after the HI state of synchronization signal S_SYNC1, as shown in graph 114d of timing diagram 119. Further, the rising edge of clock signal S_DCLK3 at the first falling edge of encoded clock signal S_ECLK3 after the HI state of synchronization signal S_SYNC1 corresponds with the rising edge of the HI state of clock signal S_DCLK3 during period T_ECLKB. Clock conditioning circuit 100 provides clock signal S_QCLK3 with HI and LO states of durations of local periods T_ECLKA and T_ECLKB, respectively. Further, clock conditioning circuit 100 provides clock signal S_DCLK3 with HI and LO states of durations of local periods T_ECLKA and T_ECLKB, respectively.

It should be noted that the rising edge of clock signal S_DCLK3 at the first failing edge of encoded clock signal S_ECLK3 occurs after a duration of 2×T_REF so that the phase between clock signals S_QCLK3 and S_DCLK3 is 2×T_REF, which is phase φ_Desired. Hence, synchronization circuit 140 drives the phase difference between clock signals S_QCLK3 and S_DCLK3 from phase φ_Undesired to phase φ_Desired. Further, synchronization circuit 140 ensures that clock signal S_QCLK moves from a lagging state to a leading state in response to turning on clock conditioning circuit 100. In this way, synchronization circuit 140 ensures that clock signal S_QCLK desirably leads clock signal S_DCLK.

Synchronization signal S_SYNC1 is provided once per period of S_QCLK and S_DCLK. S_SYNC1 occurs during the HI to LO transition of S_ECLK during T_ECLKB. Thus within one period of startup or other event which causes S_QCLK and S_DCLK to become out of phase with one another, they will be reset to possess the correct relative phase with respect to one another. This feature is useful because at power-up either one or both of conditioned clock signals S_QCLK or S_DCLK could possess a relative polarity and phase which is undesirable.

It should be noted that synchronization circuit 140 is capable of adjusting the phase difference between other clock signals S_QCLK and S_DCLK in response to synchronization signal S_SYNC. For example, synchronization circuit 140 is capable of adjusting the phase difference between the clock signals discussed with FIGS. 6, 7, 8, 9 and 10.

FIGS. 14, 15 and 16 are block diagrams of one embodiment of a signal conditioning system 170 which includes a modulator 141 driven by clock conditioning circuit 100, wherein clock conditioning circuit 100 is driven by an encoded clock generator 149. In this embodiment, encoded clock generator 149 receives reference signal S_REF from clock generator 171 and provides encoded clock signal S_ECLK to clock conditioning circuit 100 in response. It should be noted that clock generator 171 can be included with signal conditioning system 170, or it can be separate from signal conditioning system 170. Encoded clock generator 149 can include many different types of circuitry, such as a pulse generator, frequency synthesizer and phase-locked loop. In some embodiments, encoded clock generator 149 includes a pulse counter circuit which determines a predetermined number of periods of reference clock signal S_REF and provides the rising and falling edges of encoded clock signal E_CLK in response. The predetermined number of periods of reference clock signal S_REF can change from one local period of encoded clock signal E_CLK to an adjacent local period, and from one HI and LO state of encoded clock signal E_CLK to adjacent next HI and LO state of encoded clock signal E_CLK. Encoded clock generator 149 provides encoded clock signal S_ECLK with HI and LO states which correspond to a predetermined number of periods of reference clock signal S_REF. Encoded clock generator 149 adjusts the duration of the HI and LO states of encoded clock signal S_ECLK in response to a change in the reference clock signal provided to encoded clock generator 149. As mentioned above, the available reference clock signals are at different frequencies, such as 1248 MHz and 1456 MHz. Hence, during some time intervals, reference clock signal S_REF of FIGS. 14 and 15 has a frequency of 1248 MHz and during other time intervals, reference clock signal S_REF of FIGS. 14 and 15 has a frequency of 1456 MHz. It should be noted that, in some situations, a single reference clock signal is provided to encoded clock generator, wherein the frequency of the single reference clock signal changes between 1248 MHz and 1456 MHz. However, in other situations, two separate reference clock signals are provided to encoded clock generator, wherein the frequency of one of the reference clock signals is 1248 MHz and the frequency of the other reference clock signal is 1456 MHz.

In this embodiment, clock conditioning circuit 100 includes encoding circuit 130a (FIG. 15) and synchronization circuit 140 (FIG. 11). Clock conditioning circuit 100 receives encoded clock signal S_ECLK from encoded clock generator 149, and provides clock signals S_QCLK and S_DCLK in response, as described in more detail above with FIGS. 6, 7, 8, 910 and 13. In particular, encoding circuit 130a receives encoded clock signal S_ECLK from encoded clock generator 149, and provides clock signals S_QCLK and S_DCLK in response. It should be noted that, in this embodiment, encoded clock generator 149 provides complementary encoded clock signal S_ECLK to clock conditioning circuit 100. However, as mentioned above with FIGS. 11 and 12, complementary encoded clock signal S_ECLK can be provided by an inverter included with encoding circuit 130a.

Clock conditioning circuit 100 receives synchronization signal S_SYNC from encoded clock generator 149, and ensures that clock signal S_QCLK desirably leads clock signal S_DCLK, as described in more detail above with FIG. 13. In particular, synchronization circuit 140 receives synchronization signal S_SYNC from encoded clock generator 149, as shown in FIG. 15, and provides reset signal S_Reset to encoding circuit 130a. It should be noted that clock conditioning circuit 100 can receive synchronization signal S_SYNC from another component, which is not shown here.

Battery save signal S_BS is provided to clock conditioning circuit. In particular, battery save signal S_BS is provided to synchronization circuit 140, as discussed in more detail with FIGS. 11 and 12.

FIG. 16 is a block diagram of one embodiment of modulator 141. In this embodiment, modulator 141 includes a quantizer 144 which receives clock signal S_QCLK from clock conditioning system 100 (FIGS. 14 and 15), and provides digital output signal S_Output in response. Quantizer 144 samples an inputted analog signal at sampling rate f_Sample of clock signal S_QCLK, and provides digital output signal S_Output in response.

Modulator 141 includes a digital-to-analog converter (DAC) 145, which receives digital output signal S_Output from quantizer 144 and clock signal S_DCLK from clock conditioning system 100, and provides a converted analog signal S_Converted in response. Converted analog signal S_Converted is the analog signal representation of digital output signal S_Output.

Modulator 141 includes a summer 146 which receives converted analog signal S_Converted and analog input signal S_Input, and combines them together to provide an analog summed signal S_Summed. Modulator 141 includes an analog filter 147 which receives analog summed signal S_Summed and provides an analog filtered signal S_Filtered to quantizer 144 as the inputted analog signal mentioned above. Quantizer 144 quantizes analog filtered signal S_Filtered at a sampling rate corresponding to the frequency of clock signal S_QCLK. In this way, clock conditioning circuit 100 drives modulator 141.

Sampling rate f_Sample and the phase difference between clock signal S_QCLK and S_DCLK determine the accuracy with which analog input signal S_Input is resolved and represented by digital output signal S_Output. As mentioned above, digital output signal S_Output is a more accurate representation of analog input signal S_Input as the difference between signals S_Input and S_Converter decreases. Further, digital output signal S_Output is a less accurate representation of analog input signal S_Input as the difference between signals S_Input and S_Converter increases.

Clock conditioning circuit 100 provides clock signals S_QCLK and S_DCLK to modulator 141 with a reduced amount of jitter. Further, clock conditioning circuit 100 provides clock signals S_QCLK and S_DCLK to modulator 141 without requiring an increase in frequency f_REF to reduce the amount of jitter. In this way, clock conditioning circuit 100 provides the desired clock signals without increasing the amount of power consumed by signal conditioning system 170.

It should be noted that clock conditioning circuit 100 allows the distance that clock signals S_QCLK and S_DCLK travel to decrease. As mentioned above, the phase difference between clock signals can randomly change in response to the clock signals traveling a distance. In general, the longer the distance the phase shifted clock signals travel, the more skew and attenuation they experience. Further, the shorter the distance the phase shifted clock signals travel, the less skew and attenuation they experience. It should be noted that the phase shifted clock signals typically travel along corresponding conductive lines which provide communication between clock conditioning circuit 100 and modulator 141. The phase difference between clock signals can randomly change because the clock signals are randomly and independently skewed in response to traveling the distance. The random change in the phase difference between the clock signals in response to skew is often uncontrollable and can cause jitter, which reduces the accuracy of the digital signal provided by modulator 141.

FIG. 14 shows distances L₁ and L₂, wherein distance L₁ corresponds with the distance clock signals S_ECLK and S_SYNC travel between encoded clock generator 149 and clock conditioning circuit 100, and distance L₂ corresponds with the distance clock signals S_QCLK and S_DCLK travel between clock conditioning circuit 100 and modulator 141. As distance L₂ increases, clock signals S_QCLK and S_DCLK experience more skew and attenuation, and the accuracy in which modulator 141 provides output signal S_Output decreases. As distance L₂ decreases, clock signals S_QCLK and S_DCLK experience less skew and attenuation, and the accuracy in which modulator 141 provides output signal S_Output increases. Hence, the skew and attenuation experienced by clock signals S_QCLK and S_DCLK is reduced, and the accuracy of the output signal S_Output is increased, in response to positioning clock conditioning circuit 100 closer to modulator 141. Further, the skew and attenuation experienced by clock signals S_QCLK and S_DCLK is increased, and the accuracy of the output signal S_Output is decreased, in response to positioning clock conditioning circuit 100 further away from modulator 141.

Encoded clock generator 149 can be positioned a wider range of distances away from clock conditioning circuit 100 and modulator 141 because any skew experienced by encoded clock signal S_ECLK will not substantially affect the accuracy with which modulator 141 provides output signal S_Output. As distance L₁ increases, the skew experienced by encoded clock signal S_ECLK will not substantially affect the accuracy in which modulator 141 provides output signal S_Output. As distance L₁ decreases, the skew experienced by encoded clock signal S_ECLK will not substantially affect the accuracy in which modulator 141 provides output signal S_Output. In this way, clock conditioning circuit 100 increases the accuracy in which modulator 141 provides output signal S_Output.

However, the ability of clock conditioning circuit 100 to determine the HI and LO states of encoded clock signal S_ECLK does depend on distance L₁. As distance L₁ increases, the HI and LO states of encoded clock signal S_ECLK are attenuated and skewed more, and clock conditioning circuit 100 is less likely to be able to determine them. As distance L₁ decreases, the HI and LO states of encoded clock signal S_ECLK are attenuated less, and clock conditioning circuit 100 is more likely to be able to determine them. In this way, the ability of clock conditioning circuit 100 to determine the HI and LO states of encoded clock signal S_ECLK does depend on distance L₁. The amount of attenuation and skew experienced by encoded clock signal S_ECLK can be decreased in response to increasing the amount of power of encoded clock signal S_ECLK. The amount of power of encoded clock signal S_ECLK is determined by encoded clock generator 149. The ability of clock conditioning circuit 100 to determine the phase difference between signals does not depend on the distance that encoded clock generator 149 is positioned away from modulator 141. Hence, clock conditioning circuit 100 allows encoded clock generator 149 to be positioned a larger distance L₁ away from clock conditioning circuit 100 and modulator 141 without decreasing the accuracy of the digital signal provided by modulator 141.

Embodiments which include clock conditioning circuit 100 and encoded clock generator 149 are different from embodiments in which a clock generator provides phase shifted clock signals to modulator 141 because in this situation the accuracy of the digital signal does depend on the distance between the clock generator and modulator 141.

FIG. 17 is a block diagram of a circuit 150 which includes a clock generator 151 that provides phase shifted clock signals S_QCLK and S_DCLK signals to modulator 141. In this example, clock generator 151 is positioned a distance L₃ from modulator 141, so that phase shifted clock signals S_QCLK and S_DCLK signals travel distance L₃. As the clock signals S_QCLK and S_DCLK travel distance L₃, their phases can undesirably change relative to one another in an uncontrollable manner, as discussed in more detail above. This uncontrollable change in phase of clock signals S_QCLK and S_DCLK reduces the accuracy with which modulator 141 provides output signal S_Output. As distance L₃ increases, clock signals S_QCLK and S_DCLK experience more skew and attenuation, and the accuracy in which modulator 141 provides output signal S_Output decreases. As distance L₃ decreases, clock signals S_QCLK and S_DCLK experience less skew and attenuation, and the accuracy in which modulator 141 provides output signal S_Output increases. Hence, in circuit 150, the amount of skew and attenuation experienced by clock signals S_QCLK and S_DCLK, and the accuracy of output signal S_Output, undesirably depends on distance L₃.

FIG. 18 is a flow diagram of a method 200 of providing a conditioned clock signal. In this embodiment, method 200 includes a step 201 of receiving, with a clock conditioning circuit, an encoded clock signal. The clock conditioning circuit provides first and second conditioned clock signals in response to receiving the encoded clock signal. Method 200 includes a step 202 of adjusting, with the clock conditioning circuit, a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal.

It should be noted that method 200 can include many other steps. For example, in some embodiments, method 200 includes providing the first and second conditioned clock signals to a modulator. The clock conditioning circuit can adjust the duty cycle of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The clock conditioning circuit can adjust the symmetry of the first and second conditioned clock signals in response to an adjustment of the symmetry of the encoded clock signal. The clock conditioning circuit can adjust the phase difference between the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The clock conditioning circuit can adjust the phase of the second conditioned clock signal in response to an adjustment of the phase of the first conditioned clock signal relative to a reference clock signal.

In method 200, the clock conditioning circuit can drive the first and second conditioned clock signals to a predetermined value in response to an indication from a synchronization signal. In some embodiments, the first and second conditioned clock signals are driven to the same value. Further, the clock conditioning circuit can drive the period of the first conditioned clock signal to be a desired fraction of the period of a reference clock signal.

FIG. 19 is a flow diagram of a method 210 of providing a conditioned clock signal. In this embodiment, method 210 includes a step 211 of receiving an encoded clock signal with a clock conditioning circuit. The clock conditioning circuit provides first and second conditioned clock signals in response to receiving the encoded clock signal. Method 210 includes a step 212 of driving, with the clock conditioning circuit, a phase difference between the first and second conditioned clock signals to a phase difference determined by a period of the encoded clock signal.

Method 210 can include many other steps. For example, method 210 can include receiving the first and second conditioned clock signals with a modulator. Method 210 can include adjusting, with the clock conditioning circuit, HI and LO states of the first conditioned clock signal in response to an adjustment of the duration of HI and LO states of the encoded clock signal. The duration of the HI and LO states of encoded clock signal S_ECLK1 correspond to a predetermined number of periods of reference clock signal S_REF. Method 210 can include adjusting, with the clock conditioning circuit, the phase of the second conditioned clock signal in response to an adjustment of the duration of the HI state of the encoded clock signal. Method 210 can include adjusting, with the clock conditioning circuit, a duty cycle of the first conditioned clock signal in response to an adjustment of the duration of the HI and LO states of the encoded clock signal. Method 210 can include adjusting, with the clock conditioning circuit, a phase difference in response to a change in the duration of the HI and LO states of the encoded clock signal.

Method 210 can include changing, with the clock conditioning circuit, the state of the second conditioned clock signal in response to an indication from a synchronization signal.

FIG. 20 is a flow diagram of a method 220 of providing a conditioned clock signal. In this embodiment, method 220 includes a step 221 of receiving, with a clock conditioning circuit, an encoded clock signal. The clock conditioning circuit provides first and second conditioned clock signals in response to receiving the encoded clock signal. Method 220 includes a step 222 of adjusting, with the clock conditioning circuit, a duty cycle of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal.

It should be noted that method 220 can include many other steps. For example, in some embodiments, method 220 includes providing the first and second conditioned clock signals to a modulator. The clock conditioning circuit can adjust a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The clock conditioning circuit can adjust the symmetry of the first and second conditioned clock signals in response to an adjustment of the symmetry of the encoded clock signal. The clock conditioning circuit can adjust a phase difference between the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The clock conditioning circuit can adjust the phase of the second conditioned clock signal in response to an adjustment of the phase of the first conditioned clock signal.

In method 220, the clock conditioning circuit can drive the first and second conditioned clock signals to a predetermined value in response to an indication from a synchronization signal. In some embodiments, the first and second conditioned clock signals are driven to the same value. Further, the clock conditioning circuit can drive a period of the first conditioned clock signal to be a desired fraction of the period of a reference clock signal.

FIG. 21 is a flow diagram of a method 230 of providing a conditioned clock signal. In this embodiment, method 230 includes a step 231 of providing, with an encoded clock generator, an encoded clock signal in response to receiving, with the encoded clock generator, a first reference clock signal, wherein the encoded clock signal has first and second adjacent local periods with durations that correspond to a predetermined number of periods of the first reference clock signal, the first and second local periods having durations which are adjustable relative to each other. Method 230 includes step 232 of providing first and second conditioned clock signals with a clock conditioning circuit in response to receiving the encoded clock signal.

It should be noted that method 230 can include many other steps. For example, in some embodiments, method 230 includes flowing the first and second conditioned clock signals to a modulator. The first and second local periods of the encoded clock signal can have durations which are not equal to each other. Method 230 can include adjusting, with the clock conditioning circuit, a duty cycle of the first and second conditioned clock signals in response to an adjustment of the first and second adjacent local periods of the encoded clock signal. The clock conditioning circuit can adjust a local period of the first conditioned clock signal in response to an adjustment of the first and second local periods of the encoded clock signal. The clock conditioning circuit can adjust a phase difference between the first and second conditioned clock signals in response to an adjustment of a duty cycle of the encoded clock signal. Method 230 can include adjusting, with the encoded clock generator, the durations of the first and second adjacent local periods in response to the encoded clock generator receiving a second reference clock signal, wherein the durations of the first and second adjacent local periods are adjusted to correspond to a predetermined number of periods of the second reference clock signal. The clock conditioning circuit can drive the first and second conditioned clock signals to a predetermined value in response to an indication from a synchronization signal.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the conditioned clock signals can be used to support circuits other than sigma-delta modulators. The frequencies can vary, and the number of conditioned clock signals can be more than two. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A circuit, comprising: an encoded clock generator which provides an encoded clock signal in response to receiving a reference clock signal, wherein the encoded clock signal has first and second adjacent local periods with durations that correspond to a predetermined number of periods of the reference clock signal, the first and second adjacent local periods having HI and LO states with adjustable durations;a clock conditioning circuit which receives the encoded clock signal, and provides first and second conditioned clock signals in response, wherein the clock conditioning circuit drives a phase difference between the first and second conditioned clock signals to a phase difference that corresponds to the duration of one of the HI and LO states of the encoded clock signal; anda modulator which receives the first and second conditioned clock signals.

2. The circuit of claim 1, wherein the clock conditioning circuit provides the first conditioned clock signal with a HI state having a duration that corresponds to a duration of the first local period of the encoded clock signal.

3. The circuit of claim 2, wherein the clock conditioning circuit provides the first conditioned clock signal with a LO state having a duration that corresponds to a duration of the second local period of the encoded clock signal.

4. The circuit of claim 1, wherein the clock conditioning circuit adjusts the phase difference between the first and second conditioned clock signals in response to an adjustment of the duration of a HI state of the encoded clock signal.

5. The circuit of claim 1, wherein the clock conditioning circuit adjusts a duty cycle of the first conditioned clock signal in response to an adjustment of the duration of HI and LO states of the encoded clock signal.

6. The circuit of claim 1, wherein the clock conditioning circuit drives the first and second conditioned clock signals to a predetermined value in response to an indication from a synchronization signal.

7. A circuit, comprising: an encoded clock generator which provides an encoded clock signal in response to receiving a reference clock signal, wherein the encoded clock signal includes first and second adjacent local periods with durations that correspond to a predetermined number of periods of the reference clock signal, the first and second adjacent local periods having durations adjustable relative to each other;a clock conditioning circuit which receives the encoded clock signal, and provides first and second conditioned clock signals in response, wherein the first conditioned clock signal has a local period equal to the sum of the first and second adjacent local periods of the encoded clock signal; anda modulator which receives the first and second conditioned clock signals.

8. The circuit of claim 7, wherein the clock conditioning circuit adjusts a duty cycle of the first conditioned clock signal in response to an adjustment of the duration of the first and second adjacent local periods of the encoded clock signal.

9. The circuit of claim 7, wherein the clock conditioning circuit adjusts the local period of the first conditioned clock signal in response to an adjustment of the first and second adjacent local periods of the encoded clock signal.

10. The circuit of claim 7, wherein the encoded clock signal has third and fourth local periods which are adjacent to each other and have adjustable durations that correspond to a predetermined number of periods of the reference clock signal, the third local period lags the first local period by a predetermined amount of time.

11. The circuit of claim 10, wherein the second conditioned clock signal has a local period equal to the sum of the third and fourth adjacent local periods of the encoded clock signal.

12. The circuit of claim 7, wherein the clock conditioning circuit provides the first conditioned clock signal with a HI state having a duration that corresponds to the duration of the first local period of the encoded clock signal and a LO state having a duration that corresponds to the duration of the second local period of the encoded clock signal.

13. The circuit of claim 7, wherein the clock conditioning circuit drives the first and second conditioned clock signals to a predetermined value in response to an indication from a synchronization signal.

14. A method of driving a modulator, comprising: providing an encoded clock signal, with an encoded clock generator, in response to receiving a first reference clock signal, wherein the encoded clock signal has first and second adjacent local periods with durations that correspond to a predetermined number of periods of the first reference clock signal, the first and second local periods having durations which are adjustable relative to each other;providing first and second conditioned clock signals with a clock conditioning circuit in response to receiving the encoded clock signal; andflowing the first and second conditioned clock signals to a modulator.

15. The method of claim 14, wherein the first and second local periods have durations which are not equal to each other.

16. The method of claim 14, further including adjusting, with the clock conditioning circuit, a duty cycle of the first and second conditioned clock signals in response to an adjustment of the first and second adjacent local periods of the encoded clock signal.

17. The method of claim 14, further including adjusting, with the clock conditioning circuit, a local period of the first conditioned clock signal in response to an adjustment of the first and second local periods of the encoded clock signal.

18. The method of claim 14, further including adjusting, with the clock conditioning circuit, a phase difference between the first and second conditioned clock signals in response to an adjustment of a duty cycle of the encoded clock signal.

19. The method of claim 14, further including adjusting, with the encoded clock generator, the durations of the first and second adjacent local periods in response to the encoded clock generator receiving a second reference clock signal, wherein the durations of the first and second adjacent local periods are adjusted to correspond to a predetermined number of periods of the second reference clock signal.

20. The method of claim 14, further including driving, with the clock conditioning circuit, the first and second conditioned clock signals to a predetermined value in response to an indication from a synchronization signal.