This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-290358, filed on Dec. 22, 2009, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a clock data recovery circuit, a data transfer apparatus for display device, and a data transfer method for display device.
2. Description of Related Art
An increase in the size of the display device poses a problem for a data transfer method to a display driver circuit. Further, the improvement in the resolution and higher speed of drive timings contribute to accelerate data transfer. Yamaguchi et al. (“A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10b 120 Hz LCD Drivers with 1/5-Rate Noise-Tolerant Phase and Frequency Recovery”, Solid-State Circuits Conference—Digest of Technical Papers, 2009.ISSCC 2009.IEEE International, pp. 192-193, February, 2009.) disclose a high-speed data transfer system for display devices by Point-to-Point embedded clock.
A clock data recovery (CDR) circuit disclosed by Yamaguchi et al. is described with reference to
First, a display device of
The transmission circuit TX converts display data, which is a parallel signal, and a command into a serial signal, and transfers the serial signal to the CDR circuit 1. As described later in detail, the display data and the command are alternately transferred. The command includes various control signals such as a data start signal that indicates the start of the display data.
The CDR circuit 1 converts the serial input data transferred from the timing controller into parallel data, and recovers the clock and the data. The recovered clock is referred to as a recovery clock. The data is output to the display element driver circuit 2 via a bus.
Next, the CDR circuit of
The sampling circuit SC samples serial input data transferred from the timing controller based on the recovery clock. The sampled data is output to the frequency detection circuit FD, the phase detection circuit PD, and the display element driver circuit 2.
The frequency detection circuit FD detects a frequency difference between the input data sampled by the sampling circuit SC and the recovery clock. If the frequency of the recovery clock is lower than the frequency of the input data, the frequency detection circuit FD outputs an UP signal for increasing the frequency of the recovery clock to the charge pump CP1 for FD. If the frequency of the recovery clock is higher than the frequency of the input data, the frequency detection circuit FD outputs a DOWN signal for reducing the frequency of the recovery clock to the charge pump CP1 for FD.
The phase detection circuit PD detects a phase difference between the input data sampled by the sampling circuit SC and the recovery clock. If the phase of the recovery clock is behind the phase of the input data, the phase detection circuit PD outputs the UP signal for advancing the phase of the recovery clock to the charge pump CP1 for PD. If the phase of the recovery clock is ahead of the phase of the input data, the phase detection circuit PD outputs the DOWN signal for delaying the phase of the recovery clock to the charge pump CP1 for PD.
The charge pump CP1 for FD and the charge pump CP2 for PD output an analog current signal corresponding to the input UP or DOWN signal.
The loop filter LF generates a control voltage signal according to the analog current signal input from the charge pump CP1 for FD and the charge pump CP2 for PD.
Then, the voltage control oscillator circuit VCO generates a clock CLK according to the control voltage signal which is input from the loop filter LF. In a similar way as the data, the clock CLK is output to the display element driver circuit 2, and fed back to the sampling circuit SC as the recovery clock.
On the other hand, the waveform of the input data of the bottom row indicates the case that the oscillation frequency of the voltage control oscillator circuit VCO is high as compared to the input data frequency. In this case, as indicated by the shaded area, transition of the signal level in the clock phases 0-2 and 6-7 and no transition of the signal level in the clock phase 2-6 are detected. As a result, the frequency detection circuit FD detects that the oscillation frequency is high.
The waveform of the input data of the middle row indicates the case that the input data frequency matches the oscillation frequency of the voltage control oscillator circuit VCO. In this case, the frequency detection circuit FD does not evaluate the oscillation frequency to be neither high nor low.
Note that
However, the present inventors have found a problem that in the clock data recovery circuit disclosed by Yamaguchi et al., the circuit size and power consumption are large, and EMI characteristics are low, as the 4× over sampling is adopted.
An exemplary embodiment of the present invention is a clock data recovery circuit that includes a sampling circuit that samples input data by 2× over sampling, a frequency detection circuit that detects a frequency difference between the input data sampled by the sampling circuit and a recovery clock, a phase detection circuit that detects a phase difference between the input data sampled by the sampling circuit and the recovery clock, a voltage control oscillator circuit that outputs the recovery clock to the sampling circuit at least according to the phase difference detected by the phase detection circuit, and a frequency detection control circuit that stops an operation of the frequency detection circuit while receiving display data as the input data.
Another exemplary embodiment of the present invention is a data transfer apparatus for a display device that includes a timing controller that transmits transfer data and a display element driver circuit that receives the transfer data transmitted from the timing controller. Further, the display element driver circuit includes a sampling circuit that samples input data by 2× over sampling, a frequency detection circuit that detects a frequency difference between the input data sampled by the sampling circuit and a recovery clock, a phase detection circuit that detects a phase difference between the input data sampled by the sampling circuit and the recovery clock, a voltage control oscillator circuit that outputs the recovery clock to the sampling circuit at least according to the phase difference detected by the phase detection circuit, and a frequency detection control circuit that stops an operation of the frequency detection circuit while receiving display data as the input data.
Another exemplary embodiment of the present invention is a data transfer method for a display device that transfers data from a timing controller to a display element driver circuit. The data transfer method includes sampling transfer data by 2× over sampling, detecting a phase difference between the sampled transfer data and a recovery clock instead of a frequency difference while the transfer data is display data so as to generate the recovery clock, detecting the frequency difference and the phase difference of the sampled transfer data while the transfer data is not the display data so as to generate the recovery clock.
In the present invention, the frequency detection control circuit is included that stops the operation of the frequency detection circuit while receiving the display data as the input data, and adopts the 2× over sampling. Therefore, the present invention can provide a clock data recovery circuit with small circuit size, low power consumption and excellent EMI characteristics.
The present invention can provide a clock data recovery circuit with small circuit size, low power consumption, and excellent EMI characteristics.
The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:
Hereinafter, specific exemplary embodiments incorporating the present invention are described with reference to the drawings. However, the present invention is not necessarily limited to following exemplary embodiments. For the clarity of the explanation, the following explanation and drawings are simplified as appropriate.
A clock data recovery (CDR) circuit according to a first exemplary embodiment of the present invention is described with reference to
First, the display device shown in
The transmission circuit TX converts display data, which is a parallel signal, and a command into a serial signal and transfers the serial data to the CDR circuit 100. As described later in detail, the display data and the command are alternately transferred. The command includes various control signals such as a data start signal SOD that indicates a start of the display data.
The CDR circuit 100 recovers a clock CLK while converting the input serial signal into a parallel signal. Then, the data and the clock CLK are output to the display element driver circuit 200. In response to the clock CLK, the display element driver circuit 200 outputs the display data to the display element.
Next, the CDR circuit of
The sampling circuit SC samples the serial input data transferred from the timing controller according to the recovery clock. The sampled data signal is output to the frequency detection circuit FD, the phase detection circuit PD, and the display element driver circuit 200. As the sampling circuit SC according to the present invention adopts the 2× over sampling instead of the 4× over sampling, the circuit size can be smaller than the sampling circuit SC in the CDR circuit of
The frequency detection circuit FD detects a frequency difference between the input data, which is sampled by the sampling circuit SC, and the recovery clock. If the frequency of the recovery clock is lower than the frequency of the input data, the frequency detection circuit FD outputs an UP signal for increasing the frequency of the recovery clock to the charge pump CP1 for FD. If the frequency of the recovery clock is higher than the frequency of the input data, the frequency detection circuit FD outputs a DOWN signal for reducing the frequency of the recovery clock to the charge pump CP1 for FD.
More specifically, the frequency detection circuit FD combines an integration function and a comparator function. Accordingly, if the number that the oscillation frequency is detected as “low” exceeds a predetermined number, the frequency detection circuit FD outputs the UP signal. On the other hand, if the number that the oscillation frequency is detected as “low” does not exceed the predetermined number, the frequency detection circuit FD will not output the UP signal.
Similarly, if the number that the oscillation frequency is detected as “high” exceeds a predetermined number, the frequency detection circuit FD outputs the DOWN signal. On the other hand, if the number that the oscillation frequency is detected as “high” does not exceed the predetermined number, the frequency detection circuit FD will not output the DOWN signal.
The oscillation frequency may be detected as “low” or “high” due to the jitter in the input signal even after the PLL lock. However, as the number of such detection is not many, the UP or DOWN signal is not output by the above function of the frequency detection circuit FD, thereby maintaining the PLL lock state.
More particularly, the UP or DOWN signal is output when the number that the oscillation frequency is detected as “low” or “high” exceeds the predetermined number (threshold) within a predetermined period.
On the other hand, the waveform of the input data of the bottom row indicates the case that the oscillation frequency of the voltage control oscillator circuit VCO is high as compared to the input data frequency. In this case, as indicated by the shaded area, transition of the signal level in the clock phases 0-1 and 3-4 and no transition of the signal level in the clock phase 1-3 are detected. As a result, the frequency detection circuit FD detects that the oscillation frequency is high.
The waveform of the input data of the middle row indicates the case that the input data frequency matches the oscillation frequency of the voltage control oscillator circuit VCO. In this case, the frequency detection circuit FD does not evaluate the oscillation frequency to be neither high nor low.
The phase detection circuit PD detects a phase difference between the input data sampled by the sampling circuit SC and the recovery clock. If the phase of the recovery clock is behind the phase of the input data, the phase detection circuit PD outputs the UP signal for advancing the phase of the recovery clock to the charge pump CP2 for PD. If the phase of the recovery clock is ahead of the phase of the input data, the phase detection circuit PD outputs the DOWN signal for delaying the phase of the recovery clock to the charge pump CP2 for PD.
The charge pump CP1 for FD and the charge pump CP2 for PD output an analog current signal corresponding to the input UP or DOWN signal.
The loop filter LF generates a control voltage signal according to the analog current signal input from the charge pump CP1 for FD and the charge pump CP2 for PD.
Then, the voltage control oscillator circuit VCO generates a clock CLK according to the control voltage signal which is input from the loop filter LF. In a similar way as the data, the clock CLK is output to the display element driver circuit 200 of
The data signal output from the sampling circuit SC is input to the frequency detection control circuit FDC. The frequency detection circuit FD is stopped in response to an FD stop signal included in the data signal. The frequency detection control circuit FDC is not included in the CDR circuit 1 of
Hereinafter, an operation of the frequency detection circuit FD is described with reference to the drawings.
As shown in
On the other hand, as shown in
In the period to transfer the command, noise is tend to be generated and the PLL lock is prone to be unlocked. Therefore, PLL lock state is maintained by both the frequency detection circuit FD and the phase detection circuit PD so as to return the operation. On the other hand, in the period to transfer the display data, the PLL lock will not be unlocked by noise. Therefore, the frequency detection circuit FD can be stopped and the PLL lock state can be maintained only by the phase detection circuit PD.
On the other hand, in the case of the 2× over sampling, the frequency detection circuit FD must be stopped during the display data transfer period from the following reasons. Specifically, if a pattern in which the same level signals continue for only two bits after the PLL lock, such as “1, 0, 0, 1”, or “0, 1, 1, 0” is input, there is a possibility that the frequency detection circuit FD may malfunction in the 2× over sampling. The reason is explained hereinafter.
As shown in
On the other hand, as shown in
As explained above, the inventors have found that it is no problem to stop the frequency detection circuit FD in the display data transfer period, and eliminated the risk of erroneous evaluation in the 2× over sampling. Then, by applying the 2× over sampling, the inventors have succeeded to provide the clock data recovery circuit that has small circuit size, low power consumption, and excellent EMI characteristics. Note that the frequency detection circuit FD is operating while the command is transferred. Therefore, it is necessary to specify command codes so that the frequency detection circuit FD may not malfunction, in a way that the pattern in which the same level signals continue for only two bits is less than or equal to the predetermined number (needless to say that such pattern may not be included at all). However, since the types of the command for display devices are limited, it is possible to allocate the command codes in the abovementioned way.
Although the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to the above exemplary embodiments. Various modifications that can be understood by a person in the art within the scope of the present invention can be made to the configuration and details of the present invention.
While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.
Further, the scope of the claims is not limited by the exemplary embodiments described above.
Furthermore, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.
Number | Date | Country | Kind |
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2009-290358 | Dec 2009 | JP | national |