Typical integrated circuits (ICs) have large numbers of elements that are synchronized to a system clock. Different clock distribution methods can be used to distribute the system clock across the chip to these elements. However, as the clock signal propagates through the clock distribution structure, issues such as process, voltage and temperature variations can affect the delay of the clock signal. In order to ensure proper synchronous behavior, the clock signals arriving at these elements may need to be aligned to the system clock. Delay locked loops (DLLs) are typically used to align the distributed clock signals to a reference clock prior to their use by the synchronous elements.
Embodiments of the present invention provide for a delay locked loop (DLL) comprising a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. The delay line includes a plurality of delay elements. Each delay element receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value. Additionally, each delay element may be a two input multiplexer where the second input is connected to ground. Configured in this manner, the delay element select signal can allow the input signal to propagate through the multiplexer. In this case, the input signal is delayed by a fixed unit of delay. The delay element select signal can also block the input signal to propagate through the multiplexer.
The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.
A description of example embodiments of the invention follows.
A typical delay locked loop (DLL) circuit uses the output of a phase detector to add delay to a given clock to align it with the rising/falling edge of an incoming reference clock. Embodiments of the present invention provide a DLL that requires significantly less power than a typical DLL.
When a high activity signal such as a clock signal is used as an input into the delay line, it results in a significant amount of power consumption as the signal propagates through the entire delay line regardless of the required delay. In wide range DLL architectures, the same delay line is used to lock for clock frequencies ranging, for example, from 400 MHz to 2 GHz. At higher clock frequencies, a significant amount of dynamic power is wasted even though only a small portion of the delay is used for generating delay for clock alignment.
Using the delay element select signals (dly_sel) 204, the clock signal is propagated only through the required delay elements. A multiplexer tree 214 is used to select the delayed output clock signal (CLOCK_OUT) 216. For wide range clock architectures, embodiments of the present invention result in significantly less power consumption by preventing unnecessary circuit switching activity.
In
As an example of operation of the delay line circuit of
Other embodiments of the invention may use a different method for generating the delay element select values. While the example embodiment of
While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.
Number | Name | Date | Kind |
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6756832 | Reuveni et al. | Jun 2004 | B2 |
7525356 | Hui et al. | Apr 2009 | B2 |
8692602 | Chou | Apr 2014 | B2 |