This invention pertains generally to the field of charge pumps and more particularly to clock generation circuit for use with a charge pump.
Charge pumps use a switching process to provide a DC output voltage larger than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock half cycle, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second clock half cycle, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in
Charge pumps are used in many contexts. For example, they are used as peripheral circuits on flash and other non-volatile memories to generate many of the needed operating voltages, such as programming or erase voltages, from a lower power supply voltage. A number of charge pump designs, such as conventional Dickson-type pumps, are know in the art. But given the common reliance upon charge pumps, there is an on going need for improvements in pump design, particularly with respect to trying to reduce the amount of layout area and the current consumption requirements of pumps.
In a typical charge pump arrangement, a Dickson type pump for example, the pump 201 will have a capacitor (such as 5 of
In a first aspect, a charge pump system is formed on an integrated circuit that can be connected to an external power supply. The system includes a charge pump and a clock generator circuit. The clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates an output voltage from an input voltage. The clock frequency is a decreasing function of the voltage level of the external power supply.
In another aspect, a method is described for reducing power consumption in a charge pump system formed on a circuit connectable to an external power supply. This includes receiving a voltage level from the external power supply at a clock circuit and generating in the clock circuit a clock signal having a frequency that is a decreasing function of the voltage level of the external power supply. The clock signal is provided to a charge pump, which operates at the frequency of this clock signal to generate an output voltage from an input voltage.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
The various aspects and features of the present invention may be better understood by examining the following figures, in which:
a is a simplified circuit diagram of the charging half cycle in a generic charge pump.
b is a simplified circuit diagram of the transfer half cycle in a generic charge pump.
The typical pump design uses a constant clock frequency across supply voltage levels. As noted in the Background, as the supply voltage increases, because of clock driver parasitics, the pump consumes more power. To ameliorate this, the following presents a clock generator design that tracks the clock driver period with the external pump supply voltage. More specifically, the clock generator will have a frequency that is a decreasing function of the supply voltage, so that as the supply voltage increases, the frequency will decrease and vice versa. Consequently, the design will save on pump power consumption while maintaining the pump's I-V curve.
More information on charge pumps, such Dickson type pumps and charge pumps generally, can be found, for example, in “Charge Pump Circuit Design” by Pan and Samaddar, McGraw-Hill, 2006, or “Charge Pumps: An Overview”, Pylarinos and Rogers, Department of Electrical and Computer Engineering University of Toronto, available on the webpage “www.eecg.toronto.edu/˜kphang/ece1371/chargepumps.pdf”. Further information on various other charge pump aspeqcts and designs can be found in U.S. Pat. Nos. 5,436,587; 6,370,075; 6,556,465; 6,760,262; 6,922,096; and 7,135,910; and applications Ser. No. 10/842,910 filed on May 10, 2004; Ser. No. 11/295,906 filed on Dec. 6, 2005; Ser. No. 11/303,387 filed on Dec. 16, 2005; Ser. No. 11/497,465 filed on Jul. 31, 2006; Ser. No. 11/523,875 filed on Sep. 19, 2006; Ser. Nos. 11/845,903 and 11/845,939, both filed Aug. 28, 2007; Ser. Nos . 11/955,221 and 11/995,237, both filed on Dec. 12, 2007; and Ser. No. 12/135,945 filed on Jun. 9, 2008.
Initially, with switch SW1411 closed and SW2413 open, Vcom will precharge up to V1. At t0=0, SW1411 is opened and SW2413 is closed, so that Vcom is discharged by Iref through the current source 405. The time, ΔtdelayO, it takes to switch OUT from High to Low is then:
Since each of the quantities does not have any real dependence on the value of the external power supply voltage Vext, the delay—and consequently the clock period—will not depend on the value of the external power supply either. (Again, V1 would here be the on chip Vcc value, not the external supply level.)
In
A capacitor C1507 is connected between the line at Vcom and V1. A second capacitor C2509 is also connected on the one side to the line at Vcom and at the other side through a switch SW3515 to, when position A, V1 or, when in position B to V2, where V2 is here the external supply voltage, V2=Vext. The switches SW1511, SW2513, and SW3515 are controlled but the input from either 317 (CLK) or 313 as shown on
Starting initially with SW1511 closed, SW2513 open, and SW3515 at position A, the top plates of the both C1507 and C2509 are at V1 and Vcom is precharged to V1. Then, at t0=0, SW1511 is opened, SW2513 is closed, and SW3 is at position B and connected to V2, so that Vcom is discharged by Iref through the current source 505. The time, ΔtdelayNew, it takes to switch OUT from High to Low is then:
Right after fed back input changes the switches at t0=0, Vcom is given by:
Consequently, this gives
As before in
This behavior is illustrated in
As discussed in the Background, power consumption of the charge pump system has a contribution of the product of the external voltage and the clock frequency. By having the frequency as a decreasing function of Vext, the dependency of their product on the external supply level can be reduced, with the parameters (Vref, C1, . . . ) chosen accordingly. For example, if C2 is taken so that:
then, putting this into the relation for ΔtdelayNew gives fclock˜1/Vext. Consequently, the dependence on Vext in the current consumption due to the parasitic capacitance will cancel out.
Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as encompassed by the following claims.
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