Patent Application
20110298955
1. Field of the Invention
The present invention relates to a circuit that multiplies a clock signal by two, a solid-stage imaging device including the circuit, and a phase-shift circuit for the clock signal.
2. Description of the Related Art
In the past, in various electronic apparatuses, clock signals have been used to control the operations of the electronic apparatuses. Examples of the control include operation control for a 2:1 parallel-to-serial conversion circuit or the like (see, for example, JP-A-2002-9629 (Patent Document 1)).
A schematic configuration of the 2:1 parallel-to-serial conversion circuit described in Patent Document 1 is shown in
A 2:1 parallel-to-serial conversion circuit 100 includes two flip-flop circuits for retiming 101 and 102 that convert input parallel data (PDIN1 and PDIN2) into a ½ frequency clock signal PCK. The 2:1 parallel-to-serial conversion circuit 100 includes a toggle flip-flop circuit 103 that generates a ½ frequency clock signal PCK from a reference clock signal CK. Further, the 2:1 parallel-to-serial conversion circuit 100 includes a selector 104 and a flip-flop circuit for serial conversion 105.
An output P1 of the flip-flop circuit for retiming 101, an output P2 of the flip-flop circuit for retiming 102, and the ½ frequency clock signal PCK are input to the selector 104. An output P3 of the selector 104 is output (SOUT in
The operation of the 2:1 parallel-to-serial conversion circuit 100 is explained below with reference to
First, as shown in
As shown in
In the 2:1 parallel-to-serial conversion circuit 100 explained above, in order to maximize a setup/hold margin of timing for latching the output P3 of the selector 104 and a data changing point, it is desirable that a duty ratio of a clock signal is 50%. However, when fluctuation in a duty ratio of the reference clock signal CK is large, the setup/hold margin decreases. As a result, it is likely that an error occurs in output data.
As measures against such a problem, it is conceivable to adopt, for example, a method of once dividing the reference clock signal CK having fluctuation in the duty ratio by two and multiplying divided signals by two in a multiplying circuit to thereby align duty ratios of clock signals. As the multiplying circuit used in this case, various circuits have been proposed in the past (see, for example, JP-A-61-226669 (Patent Document 2)).
The configuration of a multiplying circuit proposed in Patent Document 2 is shown in
The operation of the multiplying circuit 200 is explained with reference to
First, when a signal is input to an input end (the “a” point) of the input signal inverter 201, the input signal inverter 201 inverts and outputs the input signal (see
This signal of the triangular wave shape (hereinafter referred to as triangular wave signal) is input to a plus terminal (a positive-phase terminal) of the detector 208. The triangular wave signal passes through an integrating circuit including a resistor R2 and a capacitor C2 having a time constant sufficiently larger than the period T. As shown in
When the level of the triangular wave signal is equal to or higher than the level of the threshold signal, the detector 208 outputs a high-level signal. When the level of the triangular wave signal is lower than the level of the threshold signal, the detector 208 outputs a low-level signal. As a result, as shown in
As shown in
In the multiplying circuit 200 described in Patent Document 2, the detector 207 outputs a pulse-like signal with reference to rising edges of the pulse-like signals output from the three edge detectors 204 to 206. As a result, as shown in
As explained above, as the multiplying circuit used in aligning duty ratios of clock signals, for example, the multiplying circuit employing the integrating circuits (the delay circuits) including the resistors and the capacitors proposed in Patent Document 2 or the like can be applied. However, when the multiplying circuit having the configuration proposed in Patent Document 2 or the like is used, there are problems explained below.
In the multiplying circuit 200 (
In this case, since the amplitude of the triangular wave signal is small, the triangular wave signal tends to be affected by input fluctuation of the reference clock signal CK. Further, the level of the threshold signal compared with the triangular wave signal is also affected by the input fluctuation of the reference clock signal CK. The gradient (the amplitude) of the triangular wave signal and the level of the threshold signal also fluctuate according to fluctuation in performance of the resistor and the capacitor included in the integrated circuit.
In short, in the multiplying circuit 200 employing the integrated circuits (the delay circuits) proposed in Patent Document 2, because of the various causes explained above, it is difficult to stably generate a double clock signal with a predetermined duty ratio (e.g., 50%) when a frequency changes. As a result, in the multiplying circuit 200 proposed in Patent Document 2 or the like, it is difficult to sufficiently deal with a frequency change of an input clock signal.
Therefore, it is desirable to provide a clock multiplying circuit, a solid-state imaging device including the clock multiplying circuit, and a phase-shift circuit that can accurately obtain a clock signal with a desired duty ratio even if an operating frequency substantially fluctuates.
According to an embodiment of the present invention, there is provided a clock multiplying circuit including a first inverter, a second inverter, a capacitive element, a current supplying unit, a differential detecting unit, and a multiplied-signal generating unit. The configurations and the functions of the units are as explained below. The first inverter is ON/OFF-controlled by a positive-phase signal of a first clock signal and includes a current source terminal and a current sync terminal for a control current flowing on the inside when the first inverter is on. The second inverter is ON/OFF-controlled by a negative-phase signal of the first clock signal and includes a current source terminal and a current sync terminal for a control current flowing on the inside when the second inverter is on. The current source terminal and the current sync terminal of the second inverter are respectively connected to the current source terminal and the current sync terminal of the first inverter. The capacitive element is provided between an output end of the first inverter and an output end of the second inverter. The current supplying unit increases, if the frequency of the first clock signal increases, the control current and supplies the control current to the current source terminals of the first inverter and the second inverter. The current supplying unit outputs, from the current sync terminals of the first inverter and the second inverter, a control current having a current amount same as a current amount of the control current supplied to the current source terminal. The differential detecting unit receives input of a potential difference signal between both electrodes of the capacitive element and generates, on the basis of a comparison result in a median value of a fluctuation range of the potential difference signal, a second clock signal having a phase difference of 90 degrees with respect to the positive-phase signal of the first clock signal. The multiplied-signal generating unit generates a double signal of the first clock signal on the basis of the first clock signal and the second clock signal.
According to another embodiment of the present invention, there is provided a solid-state imaging device including plural pixels arranged in a matrix shape in a row direction and a column direction, the clock multiplying circuit according to the embodiment explained above, a digital-to-analog conversion circuit, and an analog-to-digital conversion circuit. In the solid-state imaging device, the digital-to-analog conversion circuit is driven by a double signal generated by the clock multiplying circuit and generates a reference voltage signal for analog-to-digital conversion. The analog-to-digital conversion circuit includes a counter unit driven by the double signal generated by the clock multiplying signal and converts a pixel value of the pixels into a digital value.
According to still another embodiment of the present invention, there is provided a phase-shift circuit including the first inverter, the second inverter, the capacitive element, the current supplying unit, and the differential detecting unit in the clock multiplying circuit according to the embodiment explained above.
In the embodiments, the first and second inverters are ON/OFF-controlled by the first clock signal, whereby the direction of the control current (a bias current) supplied from the current supplying unit to the capacitive element via the first and second inverters is repeatedly changed. When the direction of the control current is repeatedly changed, a potential difference signal between both the electrodes of the capacitive element is input to the differential detecting unit. Subsequently, the differential detecting unit generates, on the basis of a comparison result in a median value of a fluctuation range of the input potential difference signal, the second clock signal having a phase difference of 90 degrees with respect to the positive-phase signal of the first clock signal. In the embodiments, the multiplied-signal generating unit generates a double signal of the first clock signal on the basis of the first clock signal and the second clock signal.
In the embodiments, when the double signal is generated in the operation, if the frequency of the first clock signal increases, the control current supplied to the first and second inverters is increased. Consequently, even if the frequency of the first clock signal increases, the amplitude of the potential difference signal between both the electrodes of the capacitive element can be set sufficiently large. Output accuracy of a comparison result in a median value of a fluctuation range of a potential difference signal in the differential detecting unit can be improved. Further, the differential detecting unit generates the second clock signal on the basis of a comparison result in a median value of a fluctuation range of the input potential signal. Therefore, irrespective of a change in the frequency of the first clock signal, the second clock signal can be stably and highly accurately generated.
As explained above, in the multiplying circuit according to the embodiment, even if the frequency of an input clock signal changes, a potential difference signal between both the electrodes of the capacitive element detected by the differential detecting unit can be set sufficiently large. In the embodiments, irrespective of a change in the frequency of the input clock signal, the clock signal having a phase difference of 90 degrees with respect to the positive-phase signal of the first clock signal can be stably and highly accurately generated. Therefore, in the embodiments, even if the frequency of the input clock signal changes, a double clock signal with a duty ratio of 50% can be accurately generated.
Further, as explained later, in the embodiments, a duty ratio of the second clock signal having a phase difference of 90 degrees with respect to the positive-phase signal of the first clock signal can also be accurately adjusted to 50%. Therefore, in the phase-shift circuit according to the embodiment, the second clock signal with the accurately-adjusted duty ratio can be supplied to an external circuit.
In short, with the clock multiplying circuit, the solid-state imaging device including the clock multiplying circuit, and the phase-shift circuit, even if an operating frequency substantially fluctuates, a clock signal highly-accurately adjusted to a desired duty ratio can be supplied to the external circuit.
Examples of a multiplying circuit, a phase-shift circuit, and a solid-state imaging device including the multiplying circuit according to an embodiment of the present invention are explained in the following order with reference to the accompanying drawings. The present invention is not limited to the example explained below.
1. Configuration example of the multiplying circuit
2. Operation example of the multiplying circuit
3. Configuration example of the solid-state imaging device
A schematic configuration of the multiplying circuit according to the embodiment of the present invention is shown in
The current supplying unit 1 includes a first current mirror circuit 11, a second current mirror circuit 12, a third current mirror circuit 13, and a variable bias current source (a variable current source).
The first current mirror circuit 11 includes a first PMOS (Positive channel Metal Oxide Semiconductor) transistor 41 and a second PMOS transistor 42. A source terminal of the first PMOS transistor 41 is connected to a source terminal of the second PMOS transistor 42. A gate terminal of the first PMOS transistor 41 is connected to a gate terminal of the second PMOS transistor 42 and a drain terminal of the first PMOS transistor 41. The drain terminal of the first PMOS transistor 41 is connected to a terminal on a current source side of the variable bias current source 14. A drain terminal of the second PMOS transistor 42 is connected to a drain terminal of a first NMOS (Negative channel Metal Oxide Semiconductor) transistor 51 explained later in the third current mirror circuit 13.
The second current mirror circuit 12 includes a third PMOS transistor 43 and a fourth PMOS transistor 44. A source terminal of the third PMOS transistor 43 is connected to a source terminal of the fourth PMOS transistor 44 and a source terminal of the first PMOS transistor 41 (the second PMOS transistor 42) in the first current mirror circuit 11. A gate terminal of the third PMOS transistor 43 is connected to a gate terminal of the fourth PMOS transistor 44 and a drain terminal of the third PMOS transistor 43. The drain terminal of the third PMOS transistor 43 is connected to a drain terminal of a second NMOS transistor 52 explained later in the third current mirror circuit 13. A drain terminal of the fourth PMOS transistor 44 is connected to a current source terminal 2a of the first inverter 2 and the second inverter 3.
The third current mirror circuit 13 includes the NMOS transistor 51, the second NMOS transistor 52, and a third NMOS transistor 53. The drain terminal of the first NMOS transistor 51 is connected to the drain terminal of the second PMOS transistor 42 in the first current mirror circuit 11. A gate terminal of the first NMOS transistor 51 is connected to a gate terminal of the second NMOS transistor 52, a gate terminal of the third NMOS transistor 53, and the drain terminal of the first NMOS transistor 51. A source terminal of the first NMOS transistor 51 is connected to a source terminal of the second NMOS transistor 52, a source terminal of the third NMOS transistor 53, and a terminal on a current sync side of the variable bias current source 14. The drain terminal of the second NMOS transistor 52 is connected to the drain terminal of the third PMOS transistor 43 in the second current mirror circuit 12. A drain terminal of the third NMOS transistor 53 is connected to a current sync terminal 2b of the first inverter 2 and the second inverter 3.
The variable bias current source 14 supplies predetermined bias current (a control current) to the first inverter 2 and the second inverter 3 via the first to third current mirror circuits 11 to 13. In this embodiment, as the variable bias current source 14, a variable current source that can adjust a bias current according to an operating frequency of the multiplying circuit 10 (the frequency of a clock signal CK input from the outside) is used. Specifically, the variable bias current source 14 operates to increase and supply the bias current when the frequency of the input clock signal CK increases and reduce and supply the bias current when the frequency of the clock signal CK decreases. As the variable bias current source 14, any variable bias current source can be used as long as the variable bias current source has a bias current adjusting function explained above.
In the current mirror circuits, amounts of electric currents flowing on an input side thereof are the same as those of electric currents flowing on an output side. Therefore, by configuring the current supplying unit 1 as explained above, a current amount flowing into the current source terminal 2a of the first inverter 2 and the second inverter 3 and a current amount flowing out from the current sync terminal 2b can be set the same. As a result, as explained later, a clock signal with a duty ratio of 50% (a clock signal phase-shifted 90 degrees with respect to a double clock signal and the input clock signal CK) can be more surely and highly accurately generated even if an operating frequency substantially fluctuates.
The first inverter 2 includes a PMOS transistor 21 and an NMOS transistor 22. A source terminal of the PMOS transistor 21 is connected to the current source terminal 2a. A drain terminal of the PMOS transistor 21 is connected to a drain terminal of the NMOS transistor 22. A connection point between both the transistors is an output terminal D0b (an output end) of the first inverter 2. A source terminal of the NMOS transistor 22 is connected to the current sync terminal 2b. A gate terminal of the PMOS transistor 21 is connected to a gate terminal of the NMOS transistor 22. A positive-phase clock signal CK (a first clock signal) is input to both the gate terminals from the outside. In other words, ON/OFF operations of the PMOS transistor 21 and the NMOS transistor 22 included in the first inverter 2 are controlled by the positive-phase clock signal CK.
The second inverter 3 includes a PMOS transistor 31 and an NMOS transistor 32. A source terminal of the PMOS transistor 31 is connected to the current source terminal 2a. A drain terminal of the PMOS transistor 31 is connected to a drain terminal of the NMOS transistor 32. A connection point between both the transistors is an output terminal D0 (an output end) of the second inverter 3. A source terminal of the NMOS transistor 32 is connected to the current sync terminal 2b. A gate terminal of the PMOS transistor 31 is connected to a gate terminal of the NMOS transistor 32. A negative-phase clock signal CKb is input to both the gate terminals from the outside. In other words, ON/OFF operations of the PMOS transistor 31 and the NMOS transistor 32 included in the second inverter 3 are controlled by the negative-phase clock signal CKb.
The capacitive element 4 is provided between the output terminal D0b of the first inverter 2 and the output terminal D0 of the second inverter 3. When the capacitive element 4 is connected in this way, the MOS transistors in the first inverter 2 and the second inverter 3 are ON/OFF-controlled by a clock signal, whereby the direction of a bias current supplied from the current supplying unit 1 to the capacitive element 4 is repeatedly inverted. A voltage signal of the output terminal D0b of the first inverter 2, which changes when the direction of the bias current is inverted, is output to a minus side terminal of a differential comparator 7 explained later. A voltage signal of the output terminal D0 of the second inverter 3, which changes when the direction of the bias current is inverted, is output to a plus side terminal of the differential comparator 7 explained later.
The initializing switch 5 is provided between both electrodes of the capacitive element 4. When the multiplying circuit 10 performs multiplication processing for a clock signal, first, the initializing switch 5 is turned on and a potential difference between both the electrodes of the capacitive element 4, i.e., a potential difference between the output terminal D0b of the first inverter 2 and the output terminal D0 of the second inverter 3 is set to zero.
The differential detector 6 includes the differential comparator 7 and a third inverter 8 provided at an output end of the differential comparator 7.
The differential comparator 7 calculates a difference signal (a phase difference signal) between an output signal (a voltage signal) of the second inverter 3 input to a plus side terminal of the differential comparator 7 and an output signal (a voltage signal) of the first inverter 2 input to a minus side terminal of the differential comparator 7. The differential comparator 7 outputs, from the calculated difference signal, a comparison result in a median value of a fluctuation range of the difference signal.
Specifically, the differential comparator 7 outputs a low-level signal when the level of the difference signal is equal to or higher than the median value and outputs a high-level signal when the level of the difference signal is lower than the median value. As a result, as explained later, the differential comparator 7 generates a clock signal (a third clock signal) phase-shifted 90 degrees with respect to the negative-phase clock signal CKb input to the second inverter 3. The differential comparator 7 outputs the generated clock signal to the third inverter 8.
The median value of the difference signal can be set on the basis of the potential at the output terminal D0 or D0b in an initial state.
The third inverter 8 inverts the clock signal input from the differential comparator 7. Consequently, a clock signal X (a second clock signal) phase-shifted 90 degrees with respect to the positive-phase clock signal CK input to the first inverter 2 is generated. The third inverter 8 outputs the generated clock signal X to one input terminal of the EXOR element 9.
The EXOR element 9 calculates exclusive OR of the clock signal X input to one input terminal from the third inverter 8 and the positive-phase clock signal CK input to the other input terminal and outputs a calculated signal of the exclusive OR. As a result, a double clock signal (a double signal) of the positive-phase clock signal is output from the EXOR element 9.
A specific operation of the multiplying circuit 10 according to this embodiment is explained below with reference to
First, at multiplication processing start time T0, the initializing switch 5 is turned on and thereafter maintains the ON state until time T1 (see a signal waveform 61 of
In the operation example explained here, as shown in
Subsequently, from time T1 to time T2 when the level of the positive-phase clock signal CK changes to the high level, the PMOS transistor 31 of the second inverter 3 is in an OFF state and the NMOS transistor 32 is in the ON state. Therefore, a bias current flows out from the output terminal D0. As a result, as shown in
Subsequently, at time T2, when the positive-phase clock signal CK changes to the high level (the negative-phase clock signal CKb changes to the low level), the PMOS transistor 31 of the second inverter 3 changes to the ON state and the NMOS transistor 32 changes to the OFF state. Consequently, a bias current flows into the output terminal D0 of the second inverter 3. Therefore, as shown in
At time T3, when the positive-phase clock signal CK changes to the low level (the negative-phase clock signal CKb changes to the high level), the PMOS transistor 31 of the second inverter 3 changes to the OFF state and the NMOS transistor 32 changes to the ON state. Consequently, a bias current flows out from the output terminal D0 of the second inverter 3. Therefore, as shown in
After time T3, the potentials at the output terminals of the inverters repeat rise and drop at a half period interval of a clock signal. As a result, as shown in
When the output signals of the second inverter 3 and the first inverter 2 explained above are input to the differential comparator 7, the differential comparator 7 generates a difference signal of the output signal of the second inverter 3 and the output signal of the first inverter 2. When the difference signal is generated, the output signal of the second inverter 3 and the output signal of the first inverter 2 are, output signals of a triangular wave shape that symmetrically change each other with respect to the time axis. Therefore, as shown in
The differential comparator 7 outputs a comparison result in a median value of a fluctuation range of the generated difference signal 66. Specifically, the differential comparator 7 outputs a low-level signal when the level of the difference signal 66 is equal to or higher than the median value and outputs a high-level signal when the level of the difference signal 66 is lower than the median value. As a result, as shown in
Subsequently, the third inverter 8 inverts the clock signal 67 input from the differential comparator 7 and outputs an inverted signal of the clock signal 67 to the EXOR element 9. Since the third inverter 8 inverts an output signal of the differential comparator 7, as shown in
The EXOR element 9 calculates exclusive OR of the positive-phase clock signal CK (the signal 62 in
As explained above, the multiplying circuit 10 according to this embodiment generates the double clock signal 69 with a duty ratio of 50%.
In the multiplying circuit 10 according to this embodiment, when a bias current supplied to the first inverter 2 and the second inverter 3 is fixed, the gradient of a triangular wave signal (the difference signal 66 of
However, in this embodiment, when the operating frequency rises, the bias current supplied from the current supplying unit 1 to the first inverter 2 and the second inverter 3 is increased. In this case, the gradient of the triangular wave signal calculated by the differential comparator 7 increases and the amplitude of the triangular wave signal also increases. As a result, the detection accuracy of the comparison result in the median value of the fluctuation range of the difference signal 66 in the differential comparator 7 is improved. A clock signal with a duty ratio of 50% having a phase difference of 90 degrees with respect to the input clock signal CK can be stably and accurately generated. Therefore, in this embodiment, a double clock signal with a duty ratio of 50%, which is finally generated, can be stably and highly accurately generated.
On the other hand, when the operating frequency is low, in this embodiment, the bias current supplied to the first inverter 2 and the second inverter 3 is reduced. In this case, the gradient of the triangular wave signal calculated by the differential comparator 7 decreases. However, since a low-level period or a high-level period of a clock signal increases, the amplitude of the triangular wave signal is sufficiently large. Therefore, in this embodiment, even if the bias current is reduced when the operating frequency is low, the detection accuracy of the comparison result in the median value in the fluctuation range of the triangular wave signal (the difference signal) in the differential comparator 7 does not fall. Further, power consumption in the multiplying circuit 10 can be reduced by reducing the bias current when the operating frequency is low.
In this embodiment, as explained above, the bias current supplied to the circuit including the first inverter 2 and the second inverter 3 by the current supplying unit 1 and a bias current drawn out from the circuit are controlled to be the same. Therefore, in this embodiment, irrespective of the frequency of the input clock signal CK, as shown in
Consequently, the multiplying circuit 10 according to this embodiment can accurately and stably obtain a clock signal with a duty ratio of 50% irrespective of fluctuation in an operating frequency of the multiplying circuit 10.
In the multiplying circuit 10 according to this embodiment, a clock signal with a duty ratio of 50% having a phase difference of 90 degrees with respect to the input clock signal CK can be stably and accurately output from the third inverter 8. Therefore, the multiplying circuit 10 according to this embodiment can supply a clock signal, a duty ratio of which is highly accurately adjusted to 50%, to an external circuit that needs a clock signal phase-shifted 90 degrees with respect to the input clock signal CK.
In the example explained in this embodiment, the differential detector 6 includes the differential comparator 7 and the third inverter 8, whereby a clock signal phase-shifted 90 degrees with respect to the positive-phase clock signal CK is generated from the differential detector 6. However, the present invention is not limited to this.
For example, when the output terminal D0b of the first inverter 2 and the output terminal D0 of the second inverter 3 are respectively connected to a plus terminal and a minus terminal of the differential comparator 7, a positive-phase clock signal phase-shifted 90 degrees can be directly output from the differential comparator 7. In this case, the differential detector 6 can include only the differential comparator 7.
For example, when the negative-phase clock signal CKb is input to the first inverter 2 and the positive-phase clock signal CK is input to the second inverter 3, as in the case explained above, a positive-phase clock signal phase-shifted 90 degrees can be directly output from the differential comparator 7. The differential detector 6 can include only the differential comparator 7.
When the differential detector 6 includes only the differential comparator 7 as explained above, the circuit configuration of the multiplying circuit 10 can be further simplified. However, when a waveform of an output signal of the differential comparator 7 dulls, as in the multiplying circuit 10 according to this embodiment, in order to sharpen the waveform of the output signal of the differential comparator 7, it is desirable to provide the third inverter 8 on the output side of the differential comparator 7.
An example in which the multiplying circuit 10 according to the embodiment of the present invention shown in
When the counter and the DAC are driven in the DDR system, since input data is latched during a rising edge and a falling edge of a clock signal, it is desirable that a duty ratio of the clock signal is 50% taking into account an operation margin of the clock signal. Therefore, in such an application, the multiplying circuit 10 according to the embodiment of the present invention shown in
A circuit configuration near the multiplying circuit 10 in a CMOS solid-state imaging device is shown in
A solid-state imaging device 70 includes a pixel array unit 71 in which plural pixels 72 are arranged in a matrix shape in a row direction and a column direction, a row scanning circuit 73, a column scanning circuit 74, two multiplying circuits 10 and 75, and a timing control circuit 76. The solid-state imaging device 70 further includes a DAC 77 (a digital-to-analog conversion circuit) and an ADC (Analog to Digital Converter) block 78. The configurations and the functions of the units are as explained below.
The pixels 72 in the pixel array unit 71 are connected to row selection lines Hi and column signal lines Vj (i, j=0, 1, 2, . . . ) corresponding thereto. The row scanning circuit 73 selects a predetermined row selection line Hi for reading a pixel value out of the plural row selection lines Hi (i=0, 1, 2, . . . ). The column scanning circuit 74 selects a predetermined column signal line Vj (j=0, 1, 2, . . . ) for reading out a pixel value in the row selection line Hi selected by the row scanning circuit 73.
The multiplying circuit 75 multiplies a clock signal input from the outside and generates a reference clock signal. The multiplying circuit 75 outputs the generated reference clock signal to the timing control circuit 76.
The timing control circuit 76 generates an internal clock signal using the reference clock signal input from the multiplying circuit 75. The timing control circuit 76 outputs the generated internal clock signal to the row scanning circuit 73, the column scanning circuit 74, the DAC 77, the ADC block 78, and the multiplying circuit 10.
The multiplying circuit 10 includes the multiplying circuit according to the embodiment of the present invention explained with reference to
The DAC 77 generates a reference voltage RAMP for analog to digital conversion and supplies the reference voltage RAMP to the ADC block 78. In this example, the DAC 77 is DDR-driven by the double clock signal with a duty ratio of 50% input from the multiplying circuit 10.
The ADC block 78 includes plural column ADC units 80 (analog-to-digital conversion circuits). The column ADC units 80 are provided in columns of the pixel array unit 71 corresponding thereto. Each of the column ADC units 80 includes a comparator 81, a counter unit 82, and a latch circuit 83.
The comparator 81 compares the reference voltage RAMP input from the DAC 77 and an output value from the pixels 72 transmitted via the column signal line Vj connected to the comparator 81.
The counter unit 82 is DDR-driven on the basis of the double clock signal with a duty ratio of 50% input from the multiplying circuit 10 and counts time until comparison processing in the comparator 81 is completed. In the example shown in
The latch circuit 83 is driven by the internal clock signal (a signal LAT in
As explained above, in the solid-state imaging device 70 according to this embodiment, the DAC 77 and the counter unit 82 are driven in the DDR system using the double clock signal with a duty ratio of 50% generated by the multiplying circuit 10 explained with reference to
In the example explained in the embodiment, the multiplying circuit 10 explained with reference to
The present application contains subject matter related to those disclosed in Japanese Priority Patent Applications JP 2010-128621 and JP 2010-196145 filed in the Japan Patent Office on Jun. 4, 2010 and Sep. 1, 2010, respectively, the entire contents of which is hereby incorporated by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-128621 | Jun 2010 | JP | national |
| 2010196145 | Sep 2010 | JP | national |
