Claims
- 1. A clock recovery circuit for a demodulator, comprising:
- non-linear processing means for carrying out a non-linear processing of an analog-digital-converted quasi-coherent detection received signal;
- first inversion/non-inversion means for executing inversion/non-inversion of the non-linearly processed signal by a frequency of 2 times a symbol rate of the received signal;
- means for averaging an output signal of the first inversion/non-inversion means; and
- second inversion/non-inversion means for executing inversion/non-inversion of an output signal of the averaging means by the frequency of 2 times the symbol rate of the received signal.
- 2. The clock recovery circuit of claim 1, further comprising interpolating means for a recovered clock signal oversampled with a frequency of 4 times the symbol rate of the received signal.
- 3. The clock recovery circuit of claim 1, further comprising:
- level detecting means for detecting a level of the averaging means; and
- output level set means for controlling a level of an output signal of the averaging means by using an output signal of the level detecting means.
- 4. The clock recovery circuit of claim 1, further comprising:
- level detecting means for detecting a level of the averaging means; and
- holding means for holding an output signal of the averaging means by using an output signal of the level detecting means.
- 5. The clock recovery circuit of claim 2, further comprising:
- level detecting means for detecting a level of the averaging means; and
- output level set means for controlling a level of an output signal of the averaging means by using an output signal of the level detecting means.
- 6. The clock recovery circuit of claim 2, further comprising:
- level detecting means for detecting a level of the averaging means; and
- holding means for holding an output signal of the averaging means by using an output signal of the level detecting means.
Priority Claims (2)
Number |
Date |
Country |
Kind |
4-331682 |
Dec 1992 |
JPX |
|
5-168832 |
Jul 1993 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/487,333, filed Jun. 7, 1995, entitled CLOCK RECOVERY CIRCUIT OF DEMODULATOR and now PENDING, which is a division of application Ser. No. 08/163,312, filed Dec. 8, 1993, entitled CLOCK RECOVERY CIRCUIT OF DEMODULATOR and now issued as U.S. Pat. No. 5,541,958.
US Referenced Citations (8)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0092400 |
Apr 1982 |
EPX |
0222593 |
May 1987 |
EPX |
0412234 |
Feb 1991 |
EPX |
Non-Patent Literature Citations (2)
Entry |
L.P. Sabel and W.G. Cowley, "A Recursive Algorithm for the Estimation of Symbol Timing in PSK Burst Modema", IEEE Global Telecommunications Conference , vol. 1, 9 Dec. 1992, Orlando, Florida, pp. 360-364. |
Shousei Yoshida, Hideho Tomita "A New Coherent Demodulation Technique for Land-Mobile Satellite Communications" International Mobile Satellite Conference, Ottawa, 1990. |
Divisions (2)
|
Number |
Date |
Country |
Parent |
487333 |
Jun 1995 |
|
Parent |
163312 |
Dec 1993 |
|