Claims
- 1. A clock recovery circuit for a demodulator, comprising:
- non-linear processing means for carrying out a non-linear processing of analog-digital-converted quasi-coherent detection received signals;
- first selecting means for alternately separating the non-linearly processed signals into first and second groups by a frequency of 4 times a symbol rate of the received signals;
- first sign inversion means for selectively inverting the first group of received signals separated by the first selecting means by a frequency of 2 times the symbol rate of the received signals;
- first averaging means for averaging the received signals after processing by the first sign inversion means;
- second sign inversion means for inverting the received signals obtained after processing by the first averaging means;
- third sign inversion means for selectively inverting the second group of received signals separated by the first selecting means by a frequency of 2 times the symbol rate of the received signals;
- second averaging means for averaging the received signals after processing by the third sign inversion means; fourth sign inversion means for inverting the received signals obtained after processing by the second averaging means; and
- second selecting means for alternately selecting output signals of the second and fourth sign inversion means by the frequency of 4 times the symbol rate of the received signals.
- 2. The clock recovery circuit of claim 1, further comprising:
- level detecting means for detecting a level output by each of the first and second averaging means; and
- output level set means for controlling a level of an output signal of each of the first and second averaging means by using an output signal of the level detecting means.
- 3. The clock recovery circuit of claim 1, further comprising:
- level detecting means for detecting a level output by each of the first and second averaging means; and
- holding means for holding an output signal of each of the first and second averaging means by using an output signal of the level detecting means.
- 4. The clock recovery circuit of claim 1, further comprising interpolating means for a recovered clock signal oversampled with a frequency of 4 times the symbol rate of the received signal output by the second selecting means.
- 5. The clock recovery circuit of claim 4, further comprising:
- level detecting means for detecting a level output by each of the first and second averaging means; and
- output level set means for controlling a level of an output signal of each of the first and second averaging means by using an output signal of the level detecting means.
- 6. The clock recovery circuit of claim 4, further comprising:
- level detecting means for detecting a level output by each of the first and second averaging means; and
- holding means for holding an output signal of each of the first and second averaging means by using an output signal of the level detecting means.
Priority Claims (2)
Number |
Date |
Country |
Kind |
4-331682 |
Dec 1992 |
JPX |
|
5-168832 |
Jul 1993 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/163,312, filed Dec. 8, 1993, entitled CLOCK RECOVERY CIRCUIT OF DEMODULATOR and now U.S. Pat. No. 5,541,958.
US Referenced Citations (4)
Non-Patent Literature Citations (1)
Entry |
L.P. Sabel and W.G. Cowley, "A Recursive Algorithm for the Estimation of Symbol Timing in PSK Burst Modems", IEEE Global Telecommunications Conference, vol. 1,9 Dec. 1992, Orlando Florida, pp. 360-364. |
Divisions (1)
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Number |
Date |
Country |
Parent |
163312 |
Dec 1993 |
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