Claims
- 1. A clock recovery circuit for a demodulator, comprising:
- non-linear processing means for carrying out a non-linear processing of an analog-digital-converted quasi-coherent detection received signal;
- a first pair of multiplying means for multiplying each of COS/-SIN values (.+-.1, 0) oversampled with a frequency of 4 times by the non-linearly processed signal, to form first and second results;
- a pair of means for separately averaging over time, each of the first and second results obtained in the first pair of multiplying means;
- a second pair of multiplying means for multiplying each of COS/-SIN values (.+-.1, 0) oversampled with a frequency of 4 times by each of the separately averaged results obtained in the averaging means to form third and fourth results;
- addition means for summing the third and fourth results obtained in the second pair of multiplying means:
- level detecting means for detecting a level of the averaging means; and
- output level set means for controlling a level of an output signal of the averaging means by using an output signal of the level detecting means.
- 2. The clock recovery circuit of claim 1, the clock recovery circuit receiving a signal transmitted thereto at a symbol rate, the clock recovery circuit further comprising interpolating means for interpolating a recovered clock signal oversampled with a frequency of 4 times the symbol rate.
- 3. A clock recovery circuit for a demodulator, comprising:
- non-linear processing means for carrying out a non-linear processing of an analog-digital-converted quasi-coherent detection received signal;
- a first pair of multiplying means for multiplying each of COS/-SIN values (.+-.1, 0) oversampled with a frequency of 4 times by the non-linearly processed signal, to form first and second results;
- a pair of means for separately averaging over time, each of the first and second results obtained in the first pair of multiplying means;
- a second pair of multiplying means for multiplying each of COS/-SIN values (.+-.1, 0) oversampled with a frequency of 4 times by each of the separately averaged results obtained in the averaging means to form third and fourth results;
- addition means for summing the third and fourth results obtained in the second pair of multiplying means;
- level detecting means for detecting a level of the averaging means; and
- holding means for holding an output signal of the averaging means by using an output signal of the level detecting means.
- 4. The clock recovery circuit of claim 3, the clock recovery circuit receiving a signal transmitted thereto at a symbol rate, the clock recovery circuit further comprising interpolating means for interpolating a recovered clock signal oversampled with a frequency of 4 times the symbol rate.
Priority Claims (2)
Number |
Date |
Country |
Kind |
4-331682 |
Dec 1992 |
JPX |
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5-168832 |
Jul 1993 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 08/163,312, filed Dec. 8, 1993, entiled CLOCK RECOVERY CIRCUIT OF DEMODULATOR and now U.S. Pat. No. 5,541,958.
US Referenced Citations (10)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0092400 |
Apr 1982 |
EPX |
0222593 |
May 1987 |
EPX |
0412234 |
Feb 1991 |
EPX |
Non-Patent Literature Citations (2)
Entry |
Shousei Yoshida, Hideho Tomita "A New Coherent Demodulation Technique for Land-Mobile Satellite Communications; International Mobile Satellite Conference", Ottawa, 1990. |
L.P. Sabel and W.G. Cowley, "A Recursive Algorithm for the Estimation of Symbol Timing in PSK Burst Modems:, IEEE Global Telecommunications Conf.", vol. 1, 9 Dec. 1992, Orlando, FL, pp. 360-364. |
Divisions (1)
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Number |
Date |
Country |
Parent |
163312 |
Dec 1993 |
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