NN8206138 (“Logical, Device Level Simulation of MOS Networks”, IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, pp. 138-145 (pp. 1-7).* |
Visweswariah (“Optimization techniques for high-performance digital circuits”, 1997 IEEE/ACM International Conference on Computer-Aided Design, Nov. 9, 1997, pp. 198-207).* |
Casas et al. (“Logic verification of very large circuits using Shark”, Proceedings of the Twelfth International Conference on VLSI Design, Jan. 7, 1999, pp. 310-317).* |
Razdan et al. (“Clock suppression techniques for synchronous circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 10, Oct. 1993, pp. 1547-1556).* |
Sayah, J.Y., inter alia: “Design Planning for High-Performance ASIC's”, IBM J. Res. Develop. vol. 40, No. 4, Jul. 1996, pp. 431-452. |
Dartu, F., Pileggi, L.T.: TETRA: “Transistor-Level Engine for Timing Analysis”, DCA 98, pp. 595-598, Jan. 1998. |