A clock signal generating circuit is provided. The clock signal generating circuit includes a clock signal generator for generating a first clock signal having a predetermined frequency; a frequency dividing circuit receiving the first clock signal, for providing a second clock signal with a frequency that is lower than the predetermined frequency of the first clock signal; and a frequency multiplier circuit receiving the second clock signal, for providing a system clock signal resuming the predetermined frequency to a load.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a clock signal generating circuit, in accordance with a preferred embodiment of the present invention; and
FIG. 2 is a circuit diagram of a frequency dividing circuit and a frequency multiplier circuit of FIG. 1.
Claims
1. A clock signal generating circuit comprising:
a clock signal generator for generating a first clock signal having a predetermined frequency;a frequency dividing circuit receiving the first clock signal, for providing a second clock signal with a frequency that is lower than the predetermined frequency of the first clock signal; anda frequency multiplier circuit receiving the second clock signal, for providing a system clock signal resuming the predetermined frequency to a load.
2. The clock signal generating circuit as claimed in claim 1, wherein the frequency dividing circuit comprises a NPN transistor having an emitter connected to ground, a collector connected to a voltage input, and a base connected to the clock signal generator.
3. The clock signal generating circuit as claimed in claim 2, wherein the frequency dividing circuit further comprises a first diode having an anode connected to ground, and a cathode connected to the collector of the NPN transistor via a first variable capacitor, and a second diode having a cathode connected to ground via a second variable capacitor, and an anode connected to the collector of the NPN transistor via the first variable capacitor.
4. The clock signal generating circuit as claimed in claim 3, wherein the frequency dividing circuit further comprises a programmable uni-junction transistor having a gate connected to the cathode of the second diode, an anode connected to the voltage input via a resistor and also connected to ground via another resistor, and a cathode connected to ground and providing the second clock signal.
5. The clock signal generating circuit as claimed in claim 1, wherein the frequency multiplier circuit comprises a frequency selection network for selecting a harmonic component of the second clock signal, a voltage amplifying circuit for amplifying a voltage of the harmonic component, and a filter circuit for filtering a direct-current component of the amplified voltage of the harmonic component and providing the system clock signal.
6. A clock signal generating circuit for providing a system clock signal, the clock signal generating circuit comprising:
a clock signal generator for generating a first clock signal having a predetermined frequency;a frequency dividing circuit receiving the first clock signal, for providing a second clock signal with a frequency that is lower than the predetermined frequency of the first clock signal, the second clock signal being transmitted on a printed circuit board; anda frequency multiplier circuit receiving the second clock signal, for providing the system clock signal resuming the predetermined frequency to a load connected with the printed circuit board.
7. The clock signal generating circuit as claimed in claim 6, wherein the frequency dividing circuit comprises a NPN transistor having an emitter connected to ground, a collector connected to a voltage input, and a base connected to the clock signal generator.
8. The clock signal generating circuit as claimed in claim 7, wherein the frequency dividing circuit further comprises a first diode having an anode connected to ground, and a cathode connected to the collector of the NPN transistor via a first variable capacitor, and a second diode having a cathode connected to ground via a second variable capacitor, and an anode connected to the collector of the NPN transistor via the first variable capacitor.
9. The clock signal generating circuit as claimed in claim 8, wherein the frequency dividing circuit further comprises a programmable uni-junction transistor having a gate connected to the cathode of the second diode, an anode connected to the voltage input via a resistor and also connected to ground via another resistor, and a cathode connected to ground and providing the second clock signal.
10. The clock signal generating circuit as claimed in claim 1, wherein the frequency multiplier circuit comprises a frequency selection network for selecting a harmonic component of the second clock signal, a voltage amplifying circuit for amplifying a voltage of the harmonic component, and a filter circuit for filtering a direct-current component of the amplified voltage of the harmonic component and providing the system clock signal.
Patent Application
20070176692
