Clock supply device

Abstract

Each clock supply unit comprises an inter-unit synchronization portion which operates when the clock supply unit is acting as a standby unit, using a clock signal from a DPLL of a unit which is active as reference, to apply a predetermined phase difference to the output clock signal of the DPLL of the unit to cause synchronization with the output clock signal of the DPLL of the active unit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the description as set below with reference to the accompanying drawings, wherein:

FIG. 1 is a block diagram of an example of a prior-art system clock supply device having a redundant configuration;

FIG. 2 shows phase fluctuations in the supplied clock signal which occur during the switching of the active unit;

FIG. 3 is a block diagram of the basic configuration of a first embodiment of a system clock supply device in accordance with the present invention;

FIG. 4 is a block diagram of the basic configuration of the DPLL of FIG. 3;

FIG. 5 is a timing chart of signals of various positions of a clock supply unit which is operating as the active unit;

FIG. 6 is a timing chart of signals of various positions of a clock supply unit which is operating as the standby unit;

FIG. 7 is a block diagram of the basic configuration of a second embodiment of a system clock supply device in accordance with the present invention; and

FIG. 8 is a block diagram of the basic configuration of the DPLL of FIG. 7.

Claims

1. A clock supply device having a redundant configuration which comprises a plurality of clock supply units each having a DPLL which generates a clock signal based on an external reference signal, such that one of said clock supply units acts as an active unit which supplies a clock signal generated by that clock supply unit to a later stage and another of said clock supply units acts as a standby unit; wherein each of said clock supply units comprises an inter-unit synchronization portion which operates when the unit is said standby unit, to cause synchronization of the output clock signal of the DPLL of the self unit to the output clock signal of the DPLL of said active unit, with a predetermined phase difference therebetween, with reference to a clock signal from the DPLL of said active unit which is input from said active unit.

2. The clock supply device as set forth in claim 1, wherein said DPLL comprises: a phase comparison portion which outputs a difference signal between a specified convergence phase difference and a phase difference, wherein the latter phase difference is a difference between the phase of an input reference clock signal and the phase of the output clock signal of said DPLL;an oscillation portion which generates a clock signal to be output by said DPLL, while varying the frequency of said clock signal such that the value of the difference signal becomes smaller;and wherein said inter-unit synchronization portion comprises:a clock signal switching portion which operates when the unit is said standby unit, to switch the reference clock signal which is input to said DPLL from an external reference clock signal to a clock signal which is input from said active unit; anda convergence phase difference modification portion which modifies a specified value of said convergence phase difference when the reference clock signal which is input to said DPLL is switched.

3. The clock supply device as set forth in claim 2, wherein said convergence phase difference modification portion selects a specified value of said convergence phase difference from a plurality of different fixed values which were determined previously.

4. The clock supply device as set forth in claim 2, wherein said clock supply unit comprises: a supply clock selection portion which selects either the clock signal from the DPLL of the unit or a clock signal which is input from said active unit, as a clock signal to be output to the exterior; anda phase difference detection portion which detects an output phase difference which is the phase difference between the clock signal from the DPLL of the unit and a clock signal which is input from said active unit;and wherein said convergence phase difference modification portion modifies the specified value of said convergence phase difference such that said output phase difference becomes smaller.

5. The clock supply device as set forth in claim 1, wherein said clock supply unit further comprises a cut-off frequency modification portion which increases the cut-off frequency of the DPLL of said unit when said unit is acting as said standby unit to greater than that when said unit is acting as said active unit.