Clock synchronization method, receiver, transmitter, and clock synchronization system

Information

  • Patent Grant
  • 10291446
  • Patent Number
    10,291,446
  • Date Filed
    Friday, April 27, 2018
    6 years ago
  • Date Issued
    Tuesday, May 14, 2019
    5 years ago
Abstract
A clock synchronization method, a receiver, a transmitter, and a clock synchronization system, where the method includes obtaining a common reference clock signal, determining Bt according to the common reference clock signal and Mrd(t−1), where
Description
TECHNICAL FIELD

The present disclosure relates to the field of communications technologies, and in particular, to a clock synchronization method, a receiver, a transmitter, and a clock synchronization system.


BACKGROUND

A circuit emulation service relates to a clock synchronization technology. The International Telecommunication Union Telecommunication Standardization Sector (ITU-T) 1.363.1 standard defines a synchronous residual time stamp (SRTS) method for implementing differential clock synchronization. In the SRTS method, a transmitter sends information about a frequency offset between a service clock and a common reference clock to a receiver using a residual time stamp (RTS) packet. The receiver performs clock recovery according to the frequency offset information in the received RTS packet.


However, when the receiver does not receive the RTS packet sent by the transmitter, an offset may occur on a phase, relative to a phase of a service clock signal of the transmitter, of a service clock signal generated by the receiver.


SUMMARY

Embodiments of the present disclosure provide a clock synchronization method, a receiver, a transmitter, and a clock synchronization system such that when the receiver does not receive an RTS packet sent by the transmitter, an offset of a phase, relative to a phase of a service clock signal of the transmitter, of a service clock signal generated by the receiver decreases.


According to a first aspect, a clock synchronization method is disclosed, where the method is executed by a receiver and includes obtaining a common reference clock signal, where a frequency of the common reference clock signal is fn, determining Bt according to the common reference clock signal and Mrd(t−1), where








B
t

=

mod




[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]


,





t is a positive integer, and Mrd(0) is an initial value, when Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, determining that Mrd(t−1) is a target Mrd, where Ct=Bt−At, At is included in an RTS packet that is sent by a transmitter and that is received by the receiver last time, and








A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]


,





Md(n) is frequency offset information, and Md(n)=Mq(n)−Mnom, Mq(n) is a quantity, determined by the transmitter within an nth RTS period, of rising edges of the common reference clock signal, Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period, P is a bit width of a counter in the transmitter, the counter in the transmitter is configured to record the quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and n is a positive integer, performing frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient to obtain a first clock signal, where a frequency of the first clock signal is fsN, and performing frequency multiplication processing on the first clock signal to obtain a service clock signal, where a frequency of the service clock signal is fs, fs=fsN×N, and N is a multiplication factor.


With reference to the first aspect, in a first possible implementation manner of the first aspect, determining Bt according to the common reference clock signal and Mrd(t−1) includes performing frequency division on the common reference clock signal using Mrd(t−1) as a frequency dividing coefficient to obtain a second clock signal, where a frequency of the second clock signal is fsN(t−1), and a period of the second clock signal is T(t−1), performing summation on Mrd using a formula Bt=Bt−1+Mrd(t−1), and storing Bt obtained after the summation into a counter in the receiver when the period T(t−1) of the second clock signal starts, and obtaining a new Bt by means of calculation using a formula Bt=Bt−2p when Bt>2p.


With reference to the first aspect, or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, when t is greater than 1, Mrd(t−1) is Mrd(t−2).


With reference to the first possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the method further includes generating a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold, recalculating Bt according to the new Mrd and the common reference clock signal, recalculating Ct according to Bt that is obtained after the recalculation, and determining that the new Mrd is the target Mrd when Ct that is obtained after the recalculation is less than or equal to the threshold.


With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the generating a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold includes performing transition detection filtering on Ct to obtain a smooth Ct, performing loop filtering on the smooth Ct to obtain an adjustment factor ΔMrd used for adjusting the value of Mrd(t−1), and adjusting the value of Mrd(t−1) according to the adjustment factor ΔMrd to obtain the new Mrd.


With reference to any one of the first aspect, or the first to the fourth possible implementation manners of the first aspect, in a fifth possible implementation manner of the first aspect, the RTS packet further includes the bit width P of the counter in the transmitter, and/or the reference quantity Mnom, in the transmitter, of the common reference clock signal within the nth RTS period.


According to a second aspect, a clock synchronization method is disclosed, where the method is executed by a transmitter and includes obtaining a service clock signal, where a frequency of the service clock signal is fs, dividing the frequency fs of the service clock signal by a factor N, and determining an RTS period T of sending an RTS packet by the transmitter, where







T
=

N

f
s



,





and N is greater than 1, determining a quantity Mq(n) of clock periods of a common reference clock signal within an nth RTS period T, where a frequency of the common reference clock signal is fn, calculating information Md(n) about a frequency offset between the frequency fs of the service clock signal and the frequency fn of the common reference clock signal using a formula Md(n)=Mq(n)−Mnom and Mq(n), where Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period T, and n is a positive integer, calculating At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to the frequency offset information Md(n), where P is a bit width of a counter in the transmitter, and the counter in the transmitter is configured to record a quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and sending the RTS packet to a receiver, where the RTS packet includes At.


With reference to the second aspect, in a first possible implementation manner of the second aspect, the calculating At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to the frequency offset information Md(t) includes performing summation on the frequency offset information Md(n) using a formula At=At−1+Md(t), and storing At obtained after the summation into the counter in the transmitter, and when At>2p, obtaining a new At by means of calculation using a formula At=At−2p.


According to a third aspect, a receiver is disclosed, including a first obtaining unit configured to obtain a common reference clock signal, where a frequency of the common reference clock signal is fn, a first calculation unit configured to determine Bt according to Mrd(t−1) and the common reference clock signal that is obtained by the first obtaining unit, where








B
t

=

mod




[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]


,





t is a positive integer, and Mrd(0) is an initial value, a first determining unit configured to determine that Mrd(t−1) is a target Mrd when Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, where Ct=Bt−At, At is included in an RTS packet that is sent by a transmitter and that is received by the receiver last time, and








A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]


,





Md(n) is frequency offset information, and Md(n)=Mq(n)−Mnom, Mq(n) is a quantity, determined by the transmitter within an nth RTS period, of rising edges of the common reference clock signal, Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period, P is a bit width of a counter in the transmitter, the counter in the transmitter is configured to record the quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and n is a positive integer, a first frequency-division processing unit configured to perform frequency division on the common reference clock signal using the target Mrd, which is determined by the first determining unit, as a frequency dividing coefficient to obtain a first clock signal, where a frequency of the first clock signal is fsN, and a clock-recovery processing unit configured to perform frequency multiplication processing on the first clock signal obtained by the first frequency-division processing unit to obtain a service clock signal, where a frequency of the service clock signal is fs, fs=fsN×N, and N is a multiplication factor.


With reference to the third aspect, in a first possible implementation manner of the third aspect, the first calculation unit includes a frequency-division processing subunit configured to perform frequency division on the common reference clock signal using Mrd(t−1) as a frequency dividing coefficient to obtain a second clock signal, where a frequency of the second clock signal is fsN(t−1), and a period of the second clock signal is T(t−1), a first integral-calculation subunit configured to perform summation on Mrd using a formula Bt=Bt−1+Mrd(t−1), and store Bt obtained after the summation into a counter in the receiver when the period T(t−1) of the second clock signal obtained by the frequency-division processing subunit starts, and a first numeric-value turnover subunit configured to obtain a new Bt by means of calculation using a formula Bt=Bt−2p when Bt stored by the first integral-calculation subunit is greater than 2p.


With reference to the third aspect, or the first possible implementation manner of the third aspect, in a second possible implementation manner of the third aspect, when t is greater than 1, Mrd(t−1) is Mrd(t−2).


With reference to the first possible implementation manner of the third aspect, in a third possible implementation manner of the third aspect, the receiver further includes an adjustment unit configured to generate a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold, the first calculation unit is further configured to recalculate Bt according to the new Mrd and the common reference clock signal, and recalculate Ct according to Bt that is obtained after the recalculation, until Ct that is obtained after the recalculation is less than or equal to the threshold, and the first determining unit is further configured to determine that the new Mrd is the target Mrd when Ct that is obtained after the recalculation by the first calculation unit is less than or equal to the threshold.


With reference to the third possible implementation manner of the third aspect, in a fourth possible implementation manner of the third aspect, the adjustment includes a transition detection subunit configured to perform transition detection filtering on Ct to obtain a smooth Ct, a loop filtering subunit configured to perform loop filtering on the smooth Ct obtained by the transition detection subunit to obtain an adjustment factor ΔMrd used for adjusting the value of Mrd(t−1), and an adjustment subunit configured to adjust the value of Mrd(t−1) according to the adjustment factor ΔMrd obtained by the loop filtering subunit to obtain the new Mrd.


With reference to any one of the third aspect, or the first to the fourth possible implementation manners of the third aspect, in a fifth possible implementation manner of the third aspect, the RTS packet further includes the bit width P of the counter in the transmitter, and/or the reference quantity Mnom, in the transmitter, of the common reference clock signal within the nth RTS period.


According to a fourth aspect, a transmitter is disclosed, including a second obtaining unit configured to obtain a service clock signal, where a frequency of the service clock signal is fs, a second frequency-division processing unit configured to divide the frequency fs of the service clock signal, obtained by the second obtaining unit, by a factor N, and determine an RTS period T of sending an RTS packet by the transmitter, where







T
=

N

f
s



,





and N is greater than 1, a second determining unit configured to determine a quantity Mq(n) of clock periods of a common reference clock signal within an nth RTS period T determined by the second frequency-division processing unit, where a frequency of the common reference clock signal is fn, a second calculation unit configured to calculate information Md(n) about a frequency offset between the frequency fs of the service clock signal and the frequency fn of the common reference clock signal using a formula Md(n)=Mq(n)−Mnom and Mq(n) that is determined by the second determining unit, where Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period T, and n is a positive integer, a third calculation unit configured to calculate At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to the frequency offset information Md(n) calculated by the second calculation unit, where P is a bit width of a counter in the transmitter, and the counter in the transmitter is configured to record a quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and a sending unit configured to send the RTS packet to a receiver, where the RTS packet includes At calculated by the third calculation unit.


With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect, the third calculation unit includes a second integral-calculation subunit configured to perform summation on the frequency offset information Md(n) using a formula At=At−1+Md(t), and store At obtained after the summation into the counter in the transmitter, and a second numeric-value turnover subunit configured to when At obtained by the second integral-calculation subunit is greater than 2p, obtain a new At by means of calculation using a formula At=At−2p.


According to a fifth aspect, a clock synchronization system is disclosed, including the transmitter according to the fourth aspect or the first possible implementation manner of the fourth aspect, and the receiver according to any one of the third aspect to the fifth possible implementation manner of the third aspect.


It may be learnt from the foregoing technical solutions that, a transmitter calculates At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to information Md(n), obtained by means of calculation, about a frequency offset between a frequency fs of a service clock signal and a frequency fn of a common reference clock signal, and sends an RTS packet that includes At to a receiver. Therefore, the transmitter implements summation processing on multiple pieces of generated frequency offset information Md(n), that is, the transmitter implements integral processing on Md(n). In terms of the receiver, after obtaining the common reference clock signal, the receiver determines Bt according to the common reference clock signal and Mrd(t−1), where







B
t

=


mod




[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]

.






When determining that Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, the receiver determines that Mrd(t−1) is a target Mrd, where Ct=Bt−At. The receiver performs frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient, to obtain a first clock signal. A frequency of the first clock signal is fsN. The receiver performs frequency multiplication processing on the first clock signal, to obtain a service clock signal. The frequency of the service clock signal is fs=fsN×N. N is a multiplication factor. It is assumed that the transmitter sends three RTS packets to the receiver in three consecutive RTS periods. Further, the transmitter sends a packet 1 within an RTS period 1, sends a packet 2 within an RTS period 2, and sends a packet 3 within an RTS period 3. The RTS period 1 is the last RTS period of the RTS period 2, and the RTS period 2 is the last RTS period of the RTS period 3. The receiver receives the packets 1 and 3, but does not receive the packet 2. When the receiver does not receive the RTS packet 2 sent by the transmitter, the receiver calculates the frequency fsN of the clock signal according to Mrd(t−1). Mrd(t−1) is obtained by the transmitter by means of calculation according to At−1 carried in the packet 1. The receiver calculates the frequency fsN of the clock signal according to Mrd(t−1), and determines that, relative to a phase of a service clock signal when the transmitter sends the RTS packet 2, an offset occurs on a phase of the service clock signal generated according to the calculated frequency fsN of the clock signal. When the receiver calculates the frequency fsN of the clock signal according to At+1 carried in the packet 3, the received At+1 is equal to the sum of the multiple pieces of frequency offset information Md(n) generated by the transmitter. Although the receiver does not receive the RTS packet 2, At+1 received by the receiver is equal to the sum of the multiple pieces of frequency offset information Md(n) generated by the transmitter. The multiple pieces of frequency offset information Md(n) include frequency offset information generated when the transmitter sends the RTS packet 2. After obtaining At+1 in the packet 3, the receiver calculates Mrd(t+1) according to At+1. The receiver may alternatively recalculate Mrd(t+1) according to At+1 in order to enable the difference Ct between At and Bt to be less than or equal to the threshold. When the difference Ct between At and Bt is less than or equal to the threshold, the phase of the service clock signal generated according to Mrd(t+1) is consistent with a phase of a service clock signal when the transmitter sends the packet 3, and no phase offset occurs.





BRIEF DESCRIPTION OF DRAWINGS

To describe the technical solutions in the embodiments of the present disclosure more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments. The accompanying drawings in the following description merely show some embodiments of the present disclosure, and a person of ordinary skill in the art can derive other drawings from these accompanying drawings without creative efforts.



FIG. 1 is a schematic flowchart of a clock synchronization method according to an embodiment;



FIG. 2 is a schematic diagram of a phase offset when a packet loss occurs in a clock synchronization method according to an embodiment;



FIG. 3 is a schematic flowchart of a clock synchronization method according to an embodiment;



FIG. 4 is a schematic flowchart of a clock synchronization method according to an embodiment;



FIG. 5 is a schematic structural diagram of an RTS packet according to an embodiment;



FIG. 6 is a schematic diagram of a change status of parameters, that is, Md(n) and At of a transmitter, and Mrd(n) and Bt of a receiver, when no packet loss occurs in a scenario provided in an embodiment;



FIG. 7 is a schematic diagram of a change status of parameters, that is, Md(n) and At of a transmitter, and Mrd(n) and Bt of a receiver, when a packet loss occurs in a scenario provided in an embodiment;



FIG. 8 is a schematic structural diagram of a receiver according to an embodiment of the present disclosure;



FIG. 9 is a schematic structural diagram of a transmitter according to an embodiment of the present disclosure;



FIG. 10 is a schematic structural diagram of a receiver according to an embodiment of the present disclosure; and



FIG. 11 is a schematic structural diagram of a transmitter according to an embodiment of the present disclosure.





DESCRIPTION OF EMBODIMENTS

The following clearly describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. The described embodiments are merely some but not all of the embodiments of the present disclosure.


Before specific descriptions of the embodiments, related parameter information involved in the application file is first described briefly.


A transmitter involved in this application refers to a transmitter defined in ITU-T 1.363.1. A receiver involved in this application refers to a receiver defined in ITU-T 1.363.1.


A phase offset in this application refers to an offset of a phase, relative to a phase of a service clock signal of a transmitter, of a service clock signal generated by a receiver.


Dividing a frequency of a service clock signal by a factor N that is mentioned in this application refers to performing frequency division on the frequency of the service clock signal, where a frequency dividing coefficient is N.


A packet loss mentioned in this application indicates that a receiver does not receive an RTS packet sent by a transmitter.


For an RTS period mentioned in this application, reference may be made to ITU-T 1.363.1.


An nth RTS period mentioned in this application refers to the nth RTS period with specified chronological order, where n is a positive integer. For example, the second RTS period refers to an RTS period that is adjacent to the first RTS period and that is after the first RTS period. The third RTS period refers to an RTS period that is adjacent to the second RTS period and that is after the first RTS period and the second RTS period.


For example, a quantity, determined by a transmitter within the nth RTS period, of rising edges of a common reference clock signal refers to a quantity, within the nth RTS period, of detected rising edges of the common reference clock signal.


fs is a frequency of a service clock signal, fn is a frequency of a common reference clock signal, for example, 155.52 megahertz (MHz), N is a quantity of periods, included in an RTS period T, of the service clock signal, T is an RTS period, or may be referred to as a sending period of an RTS, where







T
=

N

f
s



,





in M (Mmin, Mnom, Mmax), Mmin, Mnom, and Mmax are respectively a minimum quantity, a reference quantity, and a maximum quantity of clock periods of the common reference clock signal within the RTS period T, and meet the following condition







M
=



f
n


(


f
s

N

)


=


f
n


T



,





Mq(n) is a maximum integer less than or equal to M, Md(n) is a difference between Mq(n) and Mnom, that is, Md(n)=Mq(n)−Mnom, At is a result obtained after a transmitter performs, using the RTS period T as a period, summation on Md(n) resulting from each calculation, and a bit width of a counter in the transmitter is a P-bit width, Mrd(n) is frequency offset information of a receiver and meets









f
n



M
rd

+

M
nom



=


f
s

N


,





where Mrd(0) is an initial value, Bt is a result obtained after the receiver performs, using a clock signal period T corresponding to a clock signal frequency fsN obtained by means of calculation as a period, summation on all obtained Mrd(n), and a bit width of a counter in the receiver is a P-bit width, and Ct is a difference between At and Bt, that is, Ct=Bt−At.


An embodiment provides a clock synchronization method. Referring to FIG. 1, the clock synchronization method includes the following steps.


Step 101: A transmitter obtains a service clock signal, where a frequency of the service clock signal is fs, and divides the frequency fs by a factor N to obtain







f
sN

=



f
s

N

.





N is a quantity of clock periods of the service clock signal within an RTS period T (the RTS period T may be alternatively referred to as a sending period T of an RTS), where N is greater than 1, and the RTS period is






T
=


1

f
sN


.





Step 102: The transmitter determines a quantity Mq(n) of clock periods of a common reference clock signal within an RTS period T.


Further, Mq(n) is a quantity, determined by the transmitter within an nth RTS period T, of rising edges of the common reference clock signal.


Step 103: The transmitter obtains information Md(n) about a frequency offset between the frequency fs of the service clock signal and a frequency fn of the common reference clock signal by means of calculation using a formula Md(n)=Mq(n)−Mnom, and sends the frequency offset information Md(n) to a receiver.


Mnom is a reference quantity of clock periods of the common reference clock signal within the RTS period T, and the value has a specified association relationship with N and can be set according to actual needs.


Step 104: The receiver receives Md(n), and obtains Mq(n) by means of calculation using a formula Mq(n)=Md(n)+Mnom.


Step 105: The receiver performs frequency division on the frequency fn of the common reference clock signal using Mq(n) obtained by means of calculation as a frequency dividing coefficient, to obtain a new clock signal frequency fsN.


Further,








f
sN

_

=



f
n



M
q



(
n
)



.






In this case, fsN obtained by the receiver approximates to fsN.


Step 106: The receiver performs processing on the new clock signal frequency fsN using a clock frequency multiplier including a phase-locked loop (PLL) to obtain a new service clock signal, where a frequency of the new service clock signal is fs=N×fsN, and N is a multiplication factor of the clock frequency multiplier.


In the foregoing clock synchronization method, when a packet loss occurs due to network congestion, an RTS packet sent by a transmitter may be lost. A receiver cannot obtain a frequency offset Md(n) in the lost RTS packet to obtain Mq(n) by means of calculation. In this case, the receiver generates a service clock signal this time using a frequency offset Mq(n−1) calculated last time. However, the frequency offset Mq(n−1) calculated last time may be inconsistent with Mq(n) actually required this time. Mq(n) actually required this time refers to Mq(n) obtained by means of calculation according to the frequency offset information Md(n) in the lost RTS packet. When the frequency offset Mq(n−1) calculated last time is inconsistent with Mq(n) actually required this time, if the frequency offset Mq(n−1) calculated last time is used to generate the service clock signal this time, an offset occurs on a phase of the newly generated service clock signal relative to a phase of a service clock signal of the transmitter. As shown in FIG. 2, a dashed line in FIG. 2 represents a phase offset status of a service clock signal of a receiver side, and a solid line represents a change status of a value of Mq(n). It may be learnt that the value of Mq(n) is characterized by periodic jitter, that is, periodic jitter of Mq(n)=Mnom+1 and Mq(n)=Mnom−1. A phase offset of a service clock signal also changes periodically. It is assumed that, when an RTS packet corresponding to Mq(3) is lost, a phase of a service clock signal generated by the receiver using a value of Mq(2) deviates upwards a lot, relative to a phase of a service clock signal generated by the receiver using a value of Mq(3). The phase of the service clock signal generated by the receiver using the value of Mq(3) is equal to the phase of the service clock signal of the transmitter. When multiple RTS packet losses occur, an offset obviously occurs on a phase of a service clock signal generated by the receiver.


Based on the foregoing, an embodiment of the present disclosure provides a clock synchronization method such that when a receiver does not receive an RTS packet sent by a transmitter in the foregoing technology, an offset of a phase, relative to a phase of a service clock signal of a transmitter side, of a service clock signal generated by the receiver decreases. Further, an embodiment of the present disclosure provides a clock synchronization system, including a receiver and a transmitter.


For ease of description, a method executed by the transmitter is described first. As shown in FIG. 3, the method includes the following steps.


Step 301: The transmitter obtains a service clock signal, where a frequency of the service clock signal is fs.


Step 302: The transmitter divides the frequency fs of the service clock signal by a factor N, and determines an RTS period T of sending an RTS packet by the transmitter.


The transmitter divides the frequency fs of the service clock signal by a factor N, to obtain fsN, where







f
sN

=



f
s

N

.






The RTS period is







T
=

1

f
sN



,





and therefore,







T
=

N

f
s



,





where N is greater than 1.


Preferably, a value of N is a corresponding value when a value of fsN is equal to 8×103 hertz (Hz) during calculation of the value







f
sN

=



f
s

N

.





Step 303: The transmitter determines a quantity Mq(n) of clock periods of a common reference clock signal within an nth RTS period T, where a frequency of the common reference clock signal is fn.


Further, within the nth RTS period T, each time the transmitter detects a rising edge of the common reference clock signal, counting is performed such that counting is performed on the frequency fn of the received common reference clock signal. Further, the transmitter stores a result that is obtained by means of counting within the nth RTS period T, and obtains the quantity Mq(n) of clock periods of the common reference clock signal within the nth RTS period T.


When a rising edge of the frequency fn of the common reference clock signal is detected once, counting may be performed on the frequency fn of the common reference clock signal once using a P-bit counter, that is, 1 is added to a numeric value of the P-bit counter.


Step 304: The transmitter calculates information Md(n) about a frequency offset between the frequency fs of the service clock signal and the frequency fn of the common reference clock signal using a formula Md(n)=Mq(n)−Mnom and Mq(n).


Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period T, where n is a positive integer.


Step 305: The transmitter calculates At using a formula







A
t

=

mod


[





n
=
0

t








M
d



(
n
)



,

2
p


]







and according to the frequency offset information Md(n).


P is a bit width of the counter in the transmitter and may be in a binary, decimal, or hexadecimal system, the counter in the transmitter is configured to record a quantity, in the transmitter within the nth RTS period T, of rising edges of the common reference clock signal.


Further, the transmitter performs summation on the frequency offset information Md(n) using a formula At=At−1+Md(t), and stores At obtained after the summation to the P-bit counter. For example, when the transmitter obtains frequency offset information Md1 for the first time, At=Md1. When the transmitter obtains frequency offset information Md2 for the second time, A2=A1+Md2, that is, A2=Md1+Md2. When the transmitter obtains frequency offset information Md3 for the third time, A3=A2+Md3, that is, A3=Md1+Md2+Md3. By analogy, when the transmitter obtains frequency offset information Mdn for the nth time, At=Md1+Md2+ . . . +Mdn.


When At>2p, numeric-value turnover is performed on At using a formula At=At−2p, to obtain a new At by means of calculation.


Step 306: The transmitter sends the RTS packet to a receiver, where the RTS packet includes At.


In the foregoing technical solutions, instead of sending frequency offset information Md(n) that is separately obtained by means of calculation within each RTS period T to a receiver, a transmitter performs summation and turnover processing on multiple pieces of frequency offset information Md(n) that are respectively corresponding to multiple consecutive RTS periods T to obtain At, and then sends At to the receiver. At is related to the sum of the multiple pieces of frequency offset information Md(n) generated by the transmitter.


As described above, an embodiment of the present disclosure provides a clock synchronization system, including a receiver and a transmitter. FIG. 4 is a schematic diagram of a method executed by the receiver. It may be understood that the clock synchronization system is described in FIG. 3 and FIG. 4 from different perspectives. The clock synchronization system is implemented by means of interaction between the transmitter and the receiver. Therefore, for understanding of the method shown in FIG. 3, reference may be made to the method shown in FIG. 4 and a description of an embodiment corresponding to FIG. 4. For understanding of the method shown in FIG. 4, reference may be made to the method shown in FIG. 3 and a description of the embodiment corresponding to FIG. 3. Referring to FIG. 4, the method executed by the receiver includes the following steps.


Step 401: The receiver obtains a common reference clock signal, where a frequency of the common reference clock signal is fn.


Step 402: The receiver determines Bt according to the common reference clock signal and Mrd(t−1).








B
t

=

mod


[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]



,





is a positive integer, and Mrd(0) is an initial value preset by the receiver side.


During specific implementation of the foregoing technical solutions, the receiver presets the initial Mrd(0), the numeric value of Mrd(0) is a numeric value first assigned by a user according to experience. When calculating B1 for the first time, the receiver first uses Mrd(0) to perform calculation. Subsequently, when calculating B2 for the second time, the receiver performs calculation according to Mrd(1) that is determined by means of calculation for the first time. When calculating B3 for the third time, the receiver performs calculation according to Mrd(2) that is determined by means of calculation for the second time. By analogy, when calculating Bt for the tth time, the receiver performs calculation according to Mrd(t−1) that is determined by means of calculation for the (t−1)th time.


The following further details the method, in step 402, of obtaining Bt by means of calculation, where the method includes the following steps.


Step 4021: The receiver performs frequency division on the common reference clock signal using Mrd(t−1) as a frequency dividing coefficient to obtain a second clock signal, where a frequency of the second clock signal is fsN(t−1), and a period of the second clock signal is T(t−1).


In this embodiment, when calculating B1 for the first time, the receiver first uses Mrd(0) as a frequency dividing coefficient to perform frequency division on the frequency fn of the common reference clock signal. In this case, a frequency fsN(0) and a period T(0) of the second clock signal are obtained.


When calculating B2 for the second time, the receiver uses Mrd(1), which is determined after B1 is calculated for the first time, as a frequency dividing coefficient to perform frequency division on the frequency fn of the common reference clock signal. In this case, a frequency fsN(1) and a period T(1) of the second clock signal are obtained.


By analogy, when calculating Bt for the tth time, the receiver uses Mrd(t−1), which is determined after Bt−1 is calculated for the (t−1)th time, as a frequency dividing coefficient to perform frequency division on the frequency fn of the common reference clock signal. In this case, a frequency fsN(t−1) and a period T(t−1) of the second clock signal are obtained.


Step 4022: When the period T(t−1) of the second clock signal starts, the receiver performs summation on Mrd using a formula Bt=Bt−1+Mrd(t−1), and store Bt obtained after the summation into a counter in the receiver.


Further, when the first period T(0) of the second clock signal starts, the receiver calculates B1. In this case, B1=B0+Mrd(0). It should be noted that B0=0.


When the second period T(1) of the second clock signal starts, the receiver calculates B2. In this case, B2=B1+Mrd(1), that is, B2=Mrd(0)+Mrd(1).


When the third period T(2) of the second clock signal starts, the receiver calculates B3. In this case, B3=B2+Mrd(2), that is, B3=Mrd(0)+Mrd(1)+Mrd(2).


By analogy, when the tth period T(t−1) of the second clock signal starts, the receiver calculates Bt. In this case, Bt=Bt+Mrd(t−1), that is, Bt=Mrd(0)+Mrd(1)+Mrd(2)+ . . . +Mrd(t−1).


Step 4023: When Bt>2p, perform numeric-value turnover on Bt using a formula Bt=Bt−2p, to obtain a new Bt by means of calculation.


Therefore, after Bt is obtained by means of calculation, Bt is subsequently used for calculating Ct in step 403.


It should be noted herein that the transmitter and the receiver use a same numeric-value turnover processing manner, and therefore, the transmitter and the receiver need to construct a same turnover counter (a P-bit counter). Therefore, the transmitter and the receiver may preset a same P-bit counter, or the transmitter may send a bit width of a P-bit counter in the transmitter to the receiver. The bit width of the P-bit counter in the transmitter may be carried in an RTS packet. More further, bit width information of the P-bit counter in the transmitter may be stored in a fixed location in an RTS frame header, as shown in FIG. 5.


Step 403: The receiver calculates Ct using a formula Ct=Bt−At.


At is included in an RTS packet that is sent by the transmitter and that is received by the receiver last time, and








A
t

=

mod


[





n
=
0

t








M
d



(
n
)



,

2
p


]



,





Md(n) is frequency offset information, and Md(n)=Mq(n)−Mnom, Mq(n) is a quantity, determined by the transmitter within an nth RTS period, of rising edges of the common reference clock signal, Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period, P is a bit width of a counter in the transmitter, the counter in the transmitter is configured to record the quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and n is a positive integer.


In this embodiment, after obtaining Bt by means of calculation, the receiver obtains At from the RTS packet that is sent by the transmitter and that is receiver by the receiver last time, and then calculates Ct using a formula Ct=Bt−At.


Step 404: When Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, the receiver determines that Mrd(t−1) is a target Mrd.


At is the foregoing At that is generated and sent by the transmitter, and








A
t

=

mod


[





n
=
0

t








M
d



(
n
)



,

2
p


]



,





Md(n) is the frequency offset information, and Md(n)=Mq(n)−Mnom, Mq(n) is the quantity, determined by the transmitter within the nth RTS period, of rising edges of the common reference clock signal, Mnom is the reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period, P is the bit width of the counter in the transmitter, the counter in the transmitter is configured to record the quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and n is a positive integer.


Preferably, the threshold may be 0 or an extremely small numeric value.


Further, when C1 that is obtained for the first time by means of calculation using Mrd(0) as a frequency diving coefficient is less than or equal to the threshold, the receiver determines that Mrd(0) is the target Mrd. In this case, Mrd(1) is marked as the target Mrd, that is, Mrd(1)=Mrd(0).


When C2 that is obtained for the second time by means of calculation using Mrd(1) as a frequency diving coefficient is less than or equal to the threshold, the receiver determines that Mrd(1) is the target Mrd. In this case, Mrd(2) is marked as the target Mrd, that is, Mrd(2)=Mrd(1).


By analogy, when Ct that is obtained for the tth time by means of calculation using Mrd(t−1) as a frequency diving coefficient is less than or equal to the threshold, the receiver determines that Mrd(t−1) is the target Mrd. In this case, Mrd(t) is marked as the target Mrd, that is, Mrd(t)=Mrd(t−1).


In this embodiment, when Ct that is obtained by the receiver by means of calculation according to Mrd(t−1) is less than or equal to the threshold, it indicates that Mrd(t−1) currently obtained is the target Mrd needed by the receiver. In this case, step 405 continues to be performed.


Step 405: The receiver performs frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient, to obtain a first clock signal, where a frequency of the first clock signal is fsN.


In this embodiment, after performing frequency division on the frequency fn of the common reference clock signal using the target Mrd as the frequency dividing coefficient, the receiver obtains the frequency fsN of the first clock signal and a period T of the first clock signal, where









f
sN

_

=


f
n



M
rd

+

M
nom




,


and






T
_


=


1


f
sN

_


.






It should be specially noted that values of Mnom that are set respectively by the transmitter and the receiver need to be consistent. Therefore, values of Mnom may be respectively preset in the transmitter and the receiver. Alternatively, the transmitter may add Mnom to the RTS packet, and then send the RTS packet to the receiver.


Step 406: The receiver performs frequency multiplication processing on the first clock signal to obtain a service clock signal, where a frequency of the service clock signal is fs, fs=fsN×N, and N is a multiplication factor.


Further, the receiver may perform processing on the first clock signal using a clock frequency multiplier, where N is a multiplication factor of the clock frequency multiplier.


In this embodiment of the present disclosure, the receiver performs controlled frequency division on the frequency fn of the common reference clock signal using the target Mrd, to obtain the frequency fsN of the first clock signal, and further performs frequency multiplication processing on the first clock signal using the clock frequency multiplier, to obtain the service clock signal. The fsN that is of the first clock signal and that is obtained by the receiver by performing controlled frequency division on the frequency fn of the common reference clock signal using the target Mrd is a clock signal frequency required by the receiver. The receiver may perform frequency multiplication processing on the frequency fsN of the clock signal using the clock frequency multiplier including a PLL to obtain the service clock signal.


Therefore, in the foregoing embodiment, a transmitter calculates At using a formula







A
t

=

mod


[





n
=
0

t








M
d



(
n
)



,

2
p


]







and according to information Md(n), obtained by means of calculation, about a frequency offset between a frequency fs of a service clock signal and a frequency fn of a common reference clock signal, and sends an RTS packet that includes At to a receiver. Therefore, the transmitter implements summation processing on multiple pieces of generated frequency offset information Md(n), that is, the transmitter implements integral processing on Md(n).


In terms of the receiver, after obtaining the common reference clock signal, the receiver determines Bt according to the common reference clock signal and Mrd(t−1), where







B
t

=


mod


[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]


.






When determining that Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, the receiver determines that Mrd(t−1) is a target Mrd, where Ct=Bt−At. Further, the receiver performs frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient to obtain a first clock signal, where a frequency of the first clock signal is fsN. The receiver performs frequency multiplication processing on the first clock signal to obtain a service clock signal, where a frequency of the service clock signal is fsN=fs×N, and N is a multiplication factor.


Therefore, in the foregoing technical solutions, it is assumed that the transmitter sends three RTS packets to the receiver in three consecutive RTS periods T. Further, the transmitter sends a packet 1 within an RTS period T1, sends a packet 2 within an RTS period T2, and sends a packet 3 within an RTS period T3. The RTS period T1 is the last RTS period of the RTS period T2, and the RTS period T2 is the last RTS period of the RTS period T3. The receiver receives the packets 1 and 3, but does not receive the packet 2. When the receiver does not receive the RTS packet 2 sent by the transmitter, the receiver calculates the frequency fsN of the clock signal according to Mrd(t−1). Mrd(t−1) is obtained by the transmitter by means of calculation according to At−1 carried in the packet 1. The receiver calculates the frequency fsN of the clock signal according to Mrd(t−1), and determines that, relative to a phase of a frequency of a service clock signal when the transmitter sends the RTS packet 2, an offset occurs on a phase of the service clock signal generated according to the calculated frequency fsN of the clock signal. When the receiver calculates the frequency fsN of the clock signal according to At+1 carried in the packet 3, the received At+1 is equal to the sum of the multiple pieces of frequency offset information Md(n) generated by the transmitter. Although the receiver does not receive the RTS packet 2, At+1 received by the receiver is equal to the sum of the multiple pieces of frequency offset information Md(n) generated by the transmitter. The multiple pieces of frequency offset information Md(n) include frequency offset information generated when the transmitter sends the RTS packet 2. After obtaining At+1 in the packet 3, the receiver calculates Mrd(t+1) according to At+1. The receiver may alternatively recalculate Mrd(t+1) according to At+1 in order to enable the difference Ct between At and Bt to be less than or equal to the threshold. When the difference Ct between At and Bt is less than or equal to the threshold, the phase of the service clock signal generated according to Mrd(t+1) is consistent with a phase of a service clock signal when the transmitter sends the packet 3, and no phase offset occurs. For details, reference may be made to FIG. 6 and FIG. 7. FIG. 6 shows a normal change status of parameters, that is, Md(n) and At of a transmitter, and Mrd(n), and Bt of a receiver, when no packet loss occurs, and FIG. 7 shows a change status of parameters, that is, Md(n) and At of a transmitter, and Mrd(n) and Bt of a receiver, when a packet loss occurs. Obviously, according to the clock synchronization method in the foregoing technical solutions, if a packet loss occurs, after a receiver receives a first RTS packet that includes the sum of multiple pieces of frequency offset information and that is sent by a transmitter, a phase of a service clock signal is promptly adjusted to be consistent with a phase of a service clock signal of the transmitter in order to avoid random phase offset.


In addition, based on the foregoing embodiment, preferably, the method may further include the following step (not shown).


Step 407: The receiver generates a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold, recalculates Bt according to the new Mrd and the common reference clock signal, recalculates Ct according to Bt that is obtained after the recalculation, and when Ct that is obtained after the recalculation is less than or equal to the threshold, determines that the new Mrd is the target Mrd.


In this embodiment, when Ct is greater than the threshold, it indicates that an offset exists in Mrd(t−1) selected currently. Adjustment needs to be performed on Mrd(t−1), to obtain the new Mrd. A specific adjustment method includes the following steps.


Step 4071: Perform transition detection filtering on Ct to obtain a smooth Ct.


Step 4072: Perform loop filtering on the smooth Ct to obtain an adjustment factor ΔMrd used for adjusting the value of Mrd(t−1).


Step 4073: Adjust the value of Mrd(t−1) according to the adjustment factor ΔMrd to obtain the new Mrd.


After the new Mrd is obtained, step 4021 is performed. The receiver performs frequency division on the frequency fn of the common reference clock signal using the new Mrd as a frequency dividing coefficient, to obtain a new second clock signal. Further, step 4021 to step 406 continue to be performed using a frequency and a period that are of the new second clock signal, and the new Mrd.


In this embodiment, when a new Bt that is obtained by means of calculation according to the new Mrd meets a condition that Ct is less than or equal to the threshold, it is determined that the new Mrd is the target Mrd.


An embodiment further provides a receiver. The receiver may be configured to execute the method shown in FIG. 4. As shown in FIG. 8, the receiver includes a first obtaining unit 10 configured to obtain a common reference clock signal, where a frequency of the common reference clock signal is fn, a first calculation unit 20 configured to determine Bt according to Mrd(t−1) and the common reference clock signal that is obtained by the first obtaining unit 10, where








B
t

=

mod


[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]



,





t is a positive integer, and Mrd(0) is an initial value, a first determining unit 30 configured to when Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, determine that Mrd(t−1) is a target Mrd, where Ct=Bt−At, At is included in an RTS packet that is sent by a transmitter and that is received by the receiver last time, and








A
t

=

mod


[





n
=
0

t








M
d



(
n
)



,

2
p


]



,





Md(n) is frequency offset information, and Md(n)=Mq(n)−Mnom m, Mq(n) is a quantity, determined by the transmitter within an nth RTS period, of rising edges of the common reference clock signal, Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period, P is a bit width of a counter in the transmitter, the counter in the transmitter is configured to record the quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and n is a positive integer, a first frequency-division processing unit 40 configured to perform frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient, to obtain a first clock signal, where a frequency of the first clock signal is fsN, and a clock-recovery processing unit 50 configured to perform frequency multiplication processing on the first clock signal obtained by the first frequency-division processing unit 40 to obtain a service clock signal, where a frequency of the service clock signal is fs, fs=fsN×N, and N is a multiplication factor. The clock-recovery processing unit 50 may be further a clock frequency multiplier, and N is a multiplication factor of the clock frequency multiplier.


The first calculation unit 20 includes a frequency-division processing subunit (not shown) configured to perform frequency division on the common reference clock signal using Mrd(t−1) as a frequency dividing coefficient, to obtain a second clock signal, where a frequency of the second clock signal is fsN(t−1), and a period of the second clock signal is T(t−1), a first integral-calculation subunit (not shown) configured to, when the period T(t−1) of the second clock signal obtained by the frequency-division processing subunit starts, perform summation on Mrd using a formula Bt=Bt−1+Mrd(t−1), and store Bt obtained after the summation into a counter in the receiver, and a first numeric-value turnover subunit (not shown) configured to, when Bt stored by the first integral-calculation subunit 22 is greater than 2p, obtain a new Bt by means of calculation using a formula Bt=Bt−2p.


When t is greater than 1, Mrd(t−1) is Mrd(t−2).


Preferably, the receiver further includes an adjustment unit (not shown) configured to generate a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold, in this case, the first calculation unit 20 is further configured to recalculate Bt according to the new Mrd and the common reference clock signal, and recalculate Ct according to Bt that is obtained after the recalculation, until Ct that is obtained after the recalculation is less than or equal to the threshold, and the first determining unit 30 is further configured to when Ct that is obtained after the recalculation by the first calculation unit 20 is less than or equal to the threshold, determine that the new Mrd is the target Mrd.


Further, the adjustment unit includes a transition detection subunit (not shown) configured to perform transition detection filtering on Ct, to obtain a smooth Ct, a loop filtering subunit (not shown) configured to perform loop filtering on the smooth Ct obtained by the transition detection subunit to obtain an adjustment factor ΔMrd used for adjusting the value of Mrd(t−1), and an adjustment subunit (not shown) configured to adjust the value of Mrd(t−1) according to the adjustment factor ΔMrd obtained by the loop filtering subunit to obtain the new Mrd.


In the foregoing solutions, optionally, the RTS packet further includes the bit width P of the counter in the transmitter, and/or the reference quantity Mnom, in the transmitter, of the common reference clock signal within the nth RTS period.


A transmitter is further provided, which may be configured to execute the method shown in FIG. 3. As shown in FIG. 9, the transmitter includes a second obtaining unit 100 configured to obtain a service clock signal, where a frequency of the service clock signal is fs, a second frequency-division processing unit 200 configured to divide the frequency fs of the service clock signal, obtained by the second obtaining unit 100, by a factor N, and determine an RTS period T of sending an RTS packet by the transmitter, where







T
=

N

f
s



,





and N is greater than 1, a second determining unit 300 configured to determine a quantity Mq(n) of clock periods of a common reference clock signal within an nth RTS period T determined by the second frequency-division processing unit 200, where a frequency of the common reference clock signal is fn, a second calculation unit 400 configured to calculate information Md(n) about a frequency offset between the frequency fs of the service clock signal and the frequency fn of the common reference clock signal using a formula Md(n)=Mq(n)−Mnom and Mq(n) that is determined by the second determining unit 300, where Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period T, and n is a positive integer, a third calculation unit 500 configured to calculate At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to the frequency offset information Md(n) calculated by the second calculation unit 400, where P is a bit width of a counter in the transmitter, and the counter in the transmitter is configured to record a quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and a sending unit 600 configured to send the RTS packet to a receiver, where the RTS packet includes At calculated by the third calculation unit 500.


The third calculation unit 500 further includes a second integral-calculation subunit (not shown) configured to perform summation on the frequency offset information Md(n) using a formula At=At−1+Md(t), and store At obtained after the summation into the counter in the transmitter, and a second numeric-value turnover subunit (not shown) configured to when At obtained by the second integral-calculation subunit is greater than 2p, obtain a new At by means of calculation using a formula At=At−2p.


In addition, a clock synchronization system is further provided, including the foregoing transmitter and receiver.


Moreover, an embodiment of the present disclosure further provides a receiver. The receiver may be a host server, personal computer PC, portable computer or terminal that has a computing capability, or the like. Specific implementation of the receiver is not limited in a specific embodiment.



FIG. 10 is a schematic structural diagram of a receiver according to an embodiment. The receiver shown in FIG. 10 may be configured to execute the method shown in FIG. 4. In addition, the receiver shown in FIG. 10 may be configured to implement the receiver shown in FIG. 8. Referring to FIG. 10, the receiver includes a processor 1010, a communications interface 1020, a memory 1030, and a bus 1040.


The processor 1010, the communications interface 1020, and the memory 1030 implement communication with each other using the bus 1040.


The processor 1010 is configured to execute a program 1032.


Further, the program 1032 may include program code, where the program code includes a computer operation instruction.


The processor 1010 may be a central processing unit (CPU), may be an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement this embodiment of the present disclosure.


The memory 1030 is configured to store the program 1032. The memory 1030 may include a high-speed random access memory (RAM), and may further include a non-volatile memory, such as at least one disk memory. The program 1032 may further include obtaining a common reference clock signal, where a frequency of the common reference clock signal is fn, determining Bt according to the common reference clock signal and Mrd(t−1), where








B
t

=

mod




[





n
=
0


t
-
1









Mr
d



(
n
)



,

2
p


]


,





t is a positive integer, and Mrd(0) is an initial value, when Ct obtained by means of calculation according to Mrd(t−1) is less than or equal to a threshold, determining that Mrd(t−1) is a target Mrd, where C=Bt−At, At is included in an RTS packet that is sent by a transmitter and that is received by the receiver last time, and








A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]


,





Md(n) is frequency offset information, and Md(n)=Mq(n)−Mnom, Mq(n) is a quantity, determined by the transmitter within an nth RTS period, of rising edges of the common reference clock signal, Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period, P is a bit width of a counter in the transmitter, the counter in the transmitter is configured to record the quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and n is a positive integer, performing frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient, to obtain a first clock signal, where a frequency of the first clock signal is fsN, and performing frequency multiplication processing on the first clock signal, to obtain a service clock signal, where a frequency of the service clock signal is fs, fs=fsN×N, and N is a multiplication factor.


Optionally, the determining Bt according to the common reference clock signal and Mrd(t−1) further includes performing frequency division on the common reference clock signal using Mrd(t−1) as a frequency dividing coefficient, to obtain a second clock signal, where a frequency of the second clock signal is fsN(t−1), and a period of the second clock signal is T(t−1), when the period T(t−1) of the second clock signal starts, performing summation on Mrd using a formula Bt=Bt−1+Mrd(t−1), and storing Bt obtained after the summation into a counter in the receiver, and when Bt>2p, obtaining a new Bt by means of calculation using a formula Bt=Bt−2p.


Optionally, when t is greater than 1, Mrd(t−1) is Mrd(t−2).


Optionally, the program 1032 further includes generating a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold, recalculating Bt according to the new Mrd and the common reference clock signal, recalculating Ct according to Bt that is obtained after the recalculation, and when Ct that is obtained after the recalculation is less than or equal to the threshold, determining that the new Mrd is the target Mrd.


Optionally, the generating a new Mrd according to a value of Mrd(t−1) when Ct obtained by means of calculation according to Mrd(t−1) is greater than the threshold includes performing transition detection filtering on Ct, to obtain a smooth Ct, performing loop filtering on the smooth Ct, to obtain an adjustment factor ΔMrd used for adjusting the value of Mrd(t−1), and adjusting the value of Mrd(t−1) according to the adjustment factor ΔMrd, to obtain the new Mrd.


Optionally, the RTS packet further includes the bit width P of the counter in the transmitter, and/or the reference quantity Mnom, in the transmitter, of the common reference clock signal within the nth RTS period.


Moreover, a transmitter is further provided. The transmitter may be a host server, personal computer PC, or portable computer or terminal that has a computing capability. Specific implementation of the transmitter is not limited in a specific embodiment.



FIG. 11 is a schematic structural diagram of a transmitter according to an embodiment. The transmitter shown in FIG. 11 may be configured to execute the method shown in FIG. 3. In addition, the transmitter shown in FIG. 11 may be configured to implement the transmitter shown in FIG. 9. Referring to FIG. 11, the transmitter includes a processor 1110, a communications interface 1120, a memory 1130, and a bus 1140.


The processor 1110, the communications interface 1120, and the memory 1130 implement communication with each other using the bus 1140.


The processor 1110 is configured to execute a program 1132.


Further, the program 1132 may include program code, where the program code includes a computer operation instruction.


The processor 1110 may be a CPU, may be an ASIC, or one or more integrated circuits configured to implement this embodiment of the present disclosure.


The memory 1130 is configured to store the program 1132. The memory 1130 may include a high-speed RAM, and may further include a non-volatile memory, such as at least one disk memory. The program 1132 may further include obtaining a service clock signal, where a frequency of the service clock signal is fs, dividing the frequency fs of the service clock signal by a factor N, and determining an RTS period T of sending an RTS packet by the transmitter, where







T
=

N

f
s



,





and N is greater than 1, determining a quantity Mq(n) of clock periods of a common reference clock signal within an nth RTS period T, where a frequency of the common reference clock signal is fn, calculating information Md(n) about a frequency offset between the frequency fs of the service clock signal and the frequency fn of the common reference clock signal using a formula Md(n)=Mq(n)−Mnom and Mq(n), where Mnom is a reference quantity, obtained by the transmitter, of clock periods of the common reference clock signal within the nth RTS period T, and n is a positive integer, calculating At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to the frequency offset information Md(n), where P is a bit width of a counter in the transmitter, and the counter in the transmitter is configured to record a quantity, in the transmitter within the nth RTS period, of rising edges of the common reference clock signal, and sending the RTS packet to a receiver, where the RTS packet includes At.


Optionally, calculating At using a formula







A
t

=

mod




[





n
=
0

t








M
d



(
n
)



,

2
p


]






and according to the frequency offset information Md(t) includes performing summation on the frequency offset information Md(n) using a formula At=At−1+Md(t), and storing At obtained after the summation into the counter in the transmitter, and when At>2p, obtaining a new At by means of calculation using a formula At=At−2p.


It should be noted that the embodiments in this application are all described in a progressive manner. Each embodiment focuses on a difference from other embodiments. For same or similar parts in the embodiments, reference may be made to these embodiments. The apparatus disclosed in the embodiments corresponds to the method disclosed in the embodiments, and therefore is described briefly. For related parts, reference may be made to descriptions in the method embodiments.


A person skilled in the art may further be aware that, in combination with the examples described in the embodiments disclosed in this specification, units and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. To clearly describe the interchangeability between the hardware and the software, the foregoing has generally described compositions and steps of each example according to functions. Whether the functions are performed by hardware or a combination of software and hardware depends on particular applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the present disclosure.


Steps of methods or algorithms described in the embodiments disclosed in this specification may be implemented using a processor directly, or a combination of a software module and a processor. The software module may be disposed in a RAM, a ROM, an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc ROM (CD-ROM), or any other form of memory well-known in the art. The processor is coupled with a memory that includes the software module. The processor may execute the method in the embodiments by accessing the software module in the memory.

Claims
  • 1. A clock synchronization method, comprising: obtaining, by a receiver, a common reference clock signal, a frequency of the common reference clock signal being fn;determining, by the receiver, Bt of the receiver based on the common reference clock signal and Mrd(t−1), the
  • 2. The method of claim 1, wherein determining the Bt comprises: performing, by the receiver, the frequency division on the common reference clock signal using the Mrd(t−1) as the frequency dividing coefficient to obtain a second clock signal, a frequency of the second clock signal being fsN(t−1), and a period of the second clock signal being T(t−1);performing, by the receiver, summation on the Mrd(t−1) using Bt=Bt+Mrd(t−1);storing the Bt obtained after the summation into a counter in the receiver when the T(t−1) starts; andobtaining, by the receiver, a new Bt using Bt=Bt−2p when the Bt>2p.
  • 3. The method of claim 1, further comprising replacing the Mrd(t−1) with Mrd(t−2) when the t is greater than one.
  • 4. The method of claim 2, further comprising: generating, by the receiver, a new threshold when the Ct obtained according to the Mrd(t−1) is greater than the threshold;recalculating, by the receiver, the Bt based on the new threshold and the common reference clock signal when the Ct according to the Mrd(t−1) is greater than the threshold;recalculating, by the receiver, the Ct based on the Bt obtained after the recalculation; anddetermining, by the receiver, that the new threshold comprises the Mrd(t−1) when the Ct obtained after the recalculation is less than or equal to the threshold.
  • 5. The method of claim 4, wherein generating the new threshold comprises: performing, by the receiver, transition detection filtering on the Ct to obtain a smooth Ct;performing, by the receiver, loop filtering on the smooth Ct to obtain an adjustment factor ΔMrd for adjusting the value of the Mrd(t−1); andadjusting, by the receiver, the value of the Mrd(t−1) based on the ΔMrd to obtain the new threshold.
  • 6. The method of claim 1, wherein the RTS packet further comprises the P and the Mnom.
  • 7. The method of claim 1, wherein the RTS packet further comprises the P.
  • 8. The method of claim 1, wherein the RTS packet further comprises the Mnom.
  • 9. A clock synchronization method, comprising: obtaining, by a transmitter, a transmitter service clock signal, a frequency of the transmitter service clock signal comprising fs;dividing, by the transmitter, the frequency fs of the transmitter service clock signal by a factor N;determining, by the transmitter, a residual time stamp (RTS) period T for sending an RTS packet, where the period
  • 10. The method of claim 9, wherein calculating the At comprises: performing, by the transmitter, summation on the Md(n) using At=At−1+Md(t);storing, by the transmitter, the At obtained after the summation into the counter in the transmitter; andobtaining, by the transmitter, a new At using At=At−2p when the At>2p.
  • 11. A receiver, comprising: a memory comprising instructions; anda processor coupled to the memory, the instructions, when executed by the processor, cause the processor to: obtain a common reference clock signal, a frequency of the common reference clock signal being fn;determine Bt of the receiver based on Mrd(t−1) and the common reference clock signal, the
  • 12. The receiver of claim 11, wherein the instructions, when executed, further cause the processor to be configured to: perform the frequency division on the common reference clock signal using the Mrd(t−1) as the frequency dividing coefficient to obtain a second clock signal, a frequency of the second clock signal comprising fsN(t−1), and a period of the second clock signal being T(t−1);perform summation on the Mrd(t−1) using Bt=Bt−1+Mrd(t−1);store the Bt obtained after the summation into a counter in the receiver when the T(t−1) starts; andobtain a new Bt using Bt=Bt−2p when the Bt is greater than 2p.
  • 13. The receiver of claim 11, further comprising replacing the Mrd(t−1) with Mrd(t−2) when the t is greater than one.
  • 14. The receiver according to claim 12, wherein the instructions, when executed by the processor, further cause the processor to be configured to: generate a new threshold;recalculate the Bt based on the new threshold and the common reference clock signal;recalculate the Ct based on the Bt obtained after the recalculation, until the Ct obtained after the recalculation is less than or equal to the threshold; anddetermine that the new threshold comprises the Mrd(t−1) when the Ct obtained after the recalculation is less than or equal to the threshold.
  • 15. The receiver of claim 14, wherein the instructions, when executed by the processor, further cause the processor to be configured to: perform transition detection filtering on the Ct to obtain a smooth Ct;perform loop filtering on the smooth Ct to obtain an adjustment factor ΔMrd for adjusting the value of the Mrd(t−1); andadjust the value of the Mrd(t−1) based on the ΔMrd to obtain the new threshold.
  • 16. The receiver of claim 11, wherein the RTS packet further comprises the P and the Mnom.
  • 17. The receiver of claim 11, wherein the RTS packet further comprises the P.
  • 18. The receiver of claim 11, wherein the RTS packet further comprises the Mnom.
  • 19. A transmitter, comprising: a memory comprising instructions; anda processor coupled to the memory, the instructions, when executed, causing the processor to be configured to: obtain a transmitter service clock signal, a frequency of the service clock signal comprising fs;divide the frequency fs of the service clock signal by a factor N;determine a residual time stamp (RTS) period T of sending an RTS packet, where the period
  • 20. The transmitter of claim 19, wherein the instructions, when executed by the processor, further cause the processor to be configured to: perform summation on the Md(n) using At=At−1+Md (t);store the At obtained after the summation into the counter in the transmitter; andobtain a new At using At=At−2p when the At is greater than 2p.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Patent Application No. PCT/CN2015/093354 filed on Oct. 30, 2015, which is hereby incorporated by reference in its entirety.

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Related Publications (1)
Number Date Country
20180248721 A1 Aug 2018 US
Continuations (1)
Number Date Country
Parent PCT/CN2015/093354 Oct 2015 US
Child 15965362 US