Patent Application
20230324522
The present disclosure is directed to Light Detection and Ranging (LIDAR; also referred to as lidar) systems, and more particularly, to time-of-flight lidar systems.
Time of flight (ToF) based imaging is used in a number of applications including range finding, depth profiling, and 3D imaging (e.g., lidar). Direct time of flight (dToF) measurement includes directly measuring the length of time between emitting radiation and sensing the radiation after reflection from an object or other target. From this, the distance to the target can be determined. Indirect time of flight (iToF) measurement includes determining the distance to the target by phase modulating the amplitude of the signals emitted by emitter element(s) of the lidar system and measuring phases (e.g., with respect to delay or shift) of the echo signals received at detector element(s) of the lidar system. These phases may be measured with a series of separate measurements or samples.
In specific applications, the sensing of the reflected radiation in either direct or indirect time of flight systems may be performed using an array of photodetectors, such as an array of single photon detectors, for example, Single Photon Avalanche Diodes (SPADs). One or more photodetectors may define a detector pixel of the array. SPAD arrays may be used as solid-state detectors in imaging applications where high sensitivity and timing resolution may be required.
A SPAD is based on a semiconductor junction (e.g., a p-n junction) that may detect incident photons when biased beyond its breakdown region (also referred to as excess bias or overbias), for example, by or in response to a strobe signal having a desired pulse width. The high reverse bias voltage generates a sufficient magnitude of electric field such that a single charge carrier introduced into the depletion layer of the device can cause a self-sustaining avalanche via impact ionization. The avalanche is quenched by a quench circuit, either actively (e.g., by reducing the bias voltage) or passively (e.g., by using the voltage drop across a serially connected resistor), to allow the photodetector to be recharged (to a bias voltage above breakdown, by charging the SPAD device capacitance) or “reset” to detect further photons. The recharge operation may likewise be performed actively (e.g., using an active circuit element to switch current through a low resistance path) or passively (e.g., by ramping the voltage across the photodetector through a serially connected RC circuit). The initiating charge carrier can be photo-electrically generated by a single incident photon striking the high field region. It is this feature which gives rise to the name ‘Single Photon Avalanche Diode’. This single photon detection mode of operation is often referred to as ‘Geiger Mode’.
When imaging a scene, ToF sensors for LIDAR applications can include circuits that time stamp and/or count incident photons as reflected from a target. Some ToF pixel approaches may use digital and/or analog circuits to count the detection of photons and the arrival times of photons, also referred to as time-stamping, which may be stored in a memory.
Data rates can be compressed by histogramming timestamps; however, this can involve considerable memory resources which may be inefficiently used in typical ToF LIDAR systems. In histogramming memory applications, such inefficiencies can involve (but are not limited to) the number of detector pixels (where more transistors per memory cell or pixel may cause surface area peak power requirements to increase), memory or bit depth (e.g., the number of bits) of each histogram bin (which may correspond to a subrange of photon arrival times), and the number of histogram bins that may be required to cover the typical time range of a LIDAR system (e.g., on the order of microseconds).
Static Random Access Memory (SRAM) may be used for memory storage. SRAM (e.g., where a single bit may be represented by 6 transistors) is many times more compact per bit than some counters that may be conventionally applied to SPAD pixels (where a single bit in a counter may be represented by a D-type (or T-type) flip-flop with around 32 transistors). In addition a readout cell (e.g., a tristate buffer) may be used per bit. SRAM may involve challenges, however, in that the read-increment-write logic conventionally incorporated in some SRAM configurations may be large and difficult to incorporate in smaller pixel due to layout/space limitations, particularly as speed and storage requirements increase.
Some embodiments described herein provide a lidar system including one or more emitter units (including one or more semiconductor lasers, such as surface- or edge-emitting laser diodes; generally referred to herein as emitters, which output emitter signals), one or more light detector pixels (including one or more photodetectors, such as semiconductor photodiodes, including avalanche photodiodes and single-photon avalanche detectors; generally referred to herein as detectors, which output detection signals in response to incident light), and one or more control circuits that are configured to selectively operate subsets of the emitter units and/or detector pixels (including respective emitters and/or detectors thereof, respectively) to provide a 3D time of flight (ToF) flash lidar system.
In some embodiments, the control circuit(s) includes a photodetector control circuit that is configured to receive respective detection signals from one or more photodetector elements, and to perform a quench and reset operation that resets the one or more photodetector elements responsive to a transition of a clock signal after a detection event. The clock signal may be a global clock signal that is configured to control output of pulses of an emitter signal from a lidar emitter or emitter array. That is, the photodetector control circuit may be configured to quench and reset the one or more photodetectors upon a next pulse of the global clock signal after a detection event.
In some embodiments, the control circuit(s) includes a memory control circuit that is configured to execute an increment operation to update data indicative of detection events that is stored in respective memory bins defined by memory cells of a non-transitory memory device, responsive to respective detection signals indicating occurrence of the detection events. The memory control circuit includes a logic-based counter circuit (e.g., a linear feedback shift register) that is configured to perform the increment operation by charge sharing between a storage element of a respective memory cell of the memory device and a bit line of a preceding memory cell (e.g., in the same row of the memory device), where the capacitance of the bit line may be much greater than the capacitance of the storage element.
According to some embodiments of the present disclosure, a Light Detection and Ranging (LIDAR) detector circuit includes one or more photodetector elements configured to output respective detection signals indicating respective detection events responsive to light incident thereon; and at least one control circuit configured to receive the respective detection signals from the one or more photodetector elements, and to reset the one or more photodetector elements responsive to a transition of a clock signal after the respective detection events.
In some embodiments, the clock signal may be a global clock signal that is configured to control output of pulses of an emitter signal from a LIDAR emitter element or emitter array.
In some embodiments, the at least one control circuit may include a sampling circuit that is configured to sample the respective detection signals responsive to the global clock signal to generate a sampled detection signal, and a reset circuit that is configured to reset the one or more of the photodetector elements responsive to the sampled detection signal.
In some embodiments, the sampling circuit may include a logic circuit that is free of delay logic.
In some embodiments, the at least one control circuit may be configured to reset the one or more photodetector elements responsive to the transition of the clock signal and after respective delay times that are associated with the one or more photodetector elements.
In some embodiments, the one or more photodetector elements may be detectors of a same detector pixel of a LIDAR detector array, and the respective delay times of the detectors of the same detector pixel may differ from one another.
In some embodiments, the one or more photodetector elements may be detectors of different detector pixels of a LIDAR detector array, and the respective delay times of the detectors of the different detector pixels may differ from one another.
In some embodiments, the one or more photodetector elements may be detectors of different groups of detector pixels of a LIDAR detector array, and the respective delay times of the detectors of the different groups of the detector pixels may differ from one another.
In some embodiments, the at least one control circuit may include a sampling and delay circuit that is configured to sample the respective detection signals responsive to the clock signal to generate sampled detection signals and to offset the sampled detection signals by the respective delay times, and a reset circuit that is configured to reset the one or more of the photodetector elements responsive to the sampled detection signals that are offset by the delay circuit.
In some embodiments, the sampling and delay circuit may include one or more delay elements having respective timing offsets associated therewith, and the one or more delay elements may be selectable responsive to a delay select signal.
In some embodiments, the one or more photodetector elements may be configured to operate at a different voltage level than the reset circuit. The at least one control circuit may further include a bias circuit that is coupled between an output of the one or more photodetector elements and the reset circuit. The reset circuit and the bias circuit may be free of voltage level shift electronics.
In some embodiments, the reset circuit may include a reset transistor that is coupled to the output of the one or more photodetector elements. The bias circuit may include a bias transistor that is coupled in a cascode arrangement between the output of the one or more photodetector elements and the reset transistor.
In some embodiments, the one or more photodetector elements may be detectors of a same detector pixel of a LIDAR detector array, and the at least one control circuit may be configured to reset the one or more photodetector elements responsive to the transition of the global clock signal after a first one of the respective detection events.
In some embodiments, a memory device may be provided by a non-transitory storage medium including a plurality of memory cells and may be configured to store data in respective memory bins comprising one or more of the memory cells. The at least one control circuit may further include a memory control circuit configured to execute an increment operation to update the data in the respective memory bins responsive to the respective detection events.
In some embodiments, the memory control circuit may be a logic-based counter circuit that is configured to perform the increment operation by connecting a storage element of a respective one of the memory cells to a bit line of a preceding one of the memory cells in a same row or column of the memory device. A capacitance of the bit line may be greater than a capacitance of the storage element.
In some embodiments, the logic-based counter circuit may include a linear feedback shift register that is configured to execute the increment operation by sequentially shifting the data stored in the storage element of the respective one of the memory cells to a bit line of a succeeding one of the memory cells in the row using a linear feedback loop.
According to some embodiments of the present disclosure, a Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a non-transitory storage medium including a plurality of memory cells configured to store data in respective memory bins comprising one or more of the memory cells; and at least one control circuit configured to execute an increment operation to update the data in the respective memory bins by connecting a storage element of a respective memory cell of the memory cells to a bit line of a preceding memory cell of the memory cells in a same row or column of the memory device.
In some embodiments, the respective memory cell may include a transistor that is configured to be switched to connect the storage element thereof with the bit line of the preceding memory cell. A capacitance of the bit line may be greater than a capacitance of the storage element.
In some embodiments, the at least one control circuit may further include a photodetector interface circuit that is configured to receive respective detection signals from one or more photodetector elements. The at least one control circuit may be configured to execute the increment operation to update the data in the respective memory bins responsive to respective detection events indicated by the respective detection signals, and to reset the one or more photodetector elements responsive to transition of a clock signal after the respective detection events. The clock signal may be configured to control output of pulses of an emitter signal from a LIDAR emitter element.
In some embodiments, the at least one control circuit may include a logic-based counter circuit that is configured to execute the increment operation responsive to the respective detection events.
In some embodiments, the logic-based counter circuit may include a linear feedback shift register that is configured to execute the increment operation by sequentially shifting the data stored in the storage element of the respective memory cell to a bit line of a succeeding memory cell in the same row or column of the memory device using a linear feedback loop.
According to some embodiments of the present disclosure, a Light Detection and Ranging (LIDAR) detector circuit includes a detector array comprising a plurality of photodetector elements configured to output respective detection signals indicating respective detection events responsive to light incident thereon; a memory device comprising a non-transitory storage medium including a plurality of memory cells configured to store data in respective memory bins comprising one or more of the memory cells; and at least one control circuit configured to receive the respective detection signals from the photodetector elements, and to execute an increment operation to update the data in the respective memory bins responsive to the respective detection events. The at least one control circuit includes a photodetector control circuit configured to reset the photodetector elements responsive to a transition of a clock signal after the respective detection events; and/or a memory control circuit configured to execute the increment operation by connecting a storage element of a respective memory cell of the memory cells to a bit line of a preceding memory cell of the memory cells in a same row or column of the memory device.
In some embodiments, the clock signal may be a global clock signal that is configured to control output of pulses of an emitter signal from a LIDAR emitter element or emitter array. In some embodiments, the photodetector control circuit may be configured to reset the photodetector elements responsive to the transition of the clock signal and after respective delay times that are associated with the photodetector elements.
In some embodiments, the at least one control circuit may include a sampling circuit that is configured to sample the respective detection signals responsive to the global clock signal to generate sampled detection signals; and a reset circuit that is configured to reset the photodetector elements responsive to the sampled detection signals.
In some embodiments, the sampling circuit may further include a delay circuit that is configured to offset the sampled detection signals by the respective delay times. The reset circuit may be configured to reset the photodetector elements responsive to the sampled detection signals that are offset by the delay circuit.
In some embodiments, the memory device may be a memory array comprising respective rows or columns of dynamic random access memory (DRAM) cells that define the respective memory bins. The at least one control circuit may further be configured to output a readout signal responsive to a read signal that is sequentially applied to the respective rows or columns.
In some embodiments, the readout signal may include a count signal and/or a time integration signal, and the at least one control circuit may be configured to calculate an estimated time of arrival of photons incident on the photodetector elements based on the readout signal.
In some embodiments, the at least one control circuit may be configured to transmit respective strobe signals that activate the photodetector elements for respective detection windows that are differently delayed between pulses of an emitter signal that are generated responsive to the clock signal. The respective detection windows may correspond to respective distance subranges, and the at least one control circuit may be configured to transmit the respective strobe signals to activate the photodetector elements to sequentially cycle through the respective distance subranges.
In some embodiments, the one or more photodetector elements may be one or more single photon avalanche diodes (SPADs).
In some embodiments, the LIDAR system may be configured to be coupled to an autonomous vehicle such that one or more emitter elements and the one or more photodetector elements are oriented relative to an intended direction of travel of the autonomous vehicle.
Other devices, apparatus, and/or methods according to some embodiments will become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the above embodiments, be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
In the following detailed description, numerous specific details are set forth to provide a thorough understanding of embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present disclosure. It is intended that all embodiments disclosed herein can be implemented separately or combined in any way and/or combination. Aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination.
Embodiments of the present disclosure are described herein with reference to lidar applications and systems. A lidar system may include an array of emitters and an array of detectors, or a system having a single emitter and an array of detectors, or a system having an array of emitters and a single detector. As described herein, one or more emitters may define an emitter unit, and one or more detectors may define a detector pixel. A detector pixel may also include or provide outputs to dedicated circuits, such as storage and logic circuits, which are not shared with other pixels, referred to herein as an “in-pixel” configuration. A flash lidar system may acquire images by emitting light from an array of emitters, or a subset of the array, for short durations (pulses) over a field of view (FoV) or scene, and detecting the echo signals reflected from one or more targets in the FoV at one or more detectors. A non-flash or scanning lidar system may generate image frames by raster scanning light emission (continuously) over a field of view or scene, for example, using a point scan or line scan to emit the necessary power per point and sequentially scan to reconstruct the full FoV.
In embodiments described herein, a detection window or strobe window may refer to the respective durations of activation and deactivation of one or more detectors (e.g., responsive to respective detector time gates/control signals from a control circuit) over a temporal period or time between pulses of the optical signal output by the emitter(s) (also referred to as the emitter signal, which may likewise be responsive to respective emitter control signals from a control circuit). The relative timings and durations of the respective detection windows may be controlled by respective strobe signals as described herein, in which case the detection windows may be referred to as strobe windows. A clock signal (Clk) may be used to synchronize the emitter control signals and the strobe signals, to ensure that the detectors are activated to detect photons at the desired times between the pulses of the emitter signal (which may correspond to respective distance subranges of the overall imaging range of the lidar system).
Some detector pixel implementations may include limitations as to surface area-per-bit and power-per-bit. For example, some circuits may include active quench (AQ) and edge sampler circuits, which may have significant area and power consumption. In particular, an active quench circuit may include delay cells (which may delay the resetting or “quenching” of a SPAD responsive to a detection event) and level shifters (which may shift the (typically higher) voltage levels of the SPAD output signals down and the (typically lower) voltage levels used by the logic circuit up, for compatibility with one another) that may be responsible for excess power consumption.
Also, arithmetic logic units (ALU) and differential SRAM read-increment-write logic circuits may consume significant circuit area. For example, the logic required to precharge, read, modify, and write (PRMW) an SRAM-based detector pixel (some of which may include six transistors (NMOS and PMOS) per SRAM cell; also referred to as 6T) may be relatively complex and area-consuming. Address generation and clock generation may also have significant area consumption.
In addition, binary arithmetic carry chain settling may limit binary counting and arithmetic logic unit (ALU) cycle time. For example, some binary counters may use a k-bit carry chain, which may require k gate delays to settle if implemented with chained full-adders (e.g., whereby the carry output (Co) of one full adder is connected to the carry input (Ci) of the next full adder). However, such a configuration may make it difficult to settle within or inside about half of a bin time (i.e., with respect to a bin update clock cycle) in some instances, which can thus impose limitations on the histogram bin widths (e.g., limiting bin times to about 4 ns) and associated depth resolution.
Some embodiments of the present disclosure may arise from realization that, in some lidar applications, memory may be accessed sequentially, e.g., by stepping progressively through and updating time bins in real time with incoming photon counts returning from the laser pulse reflected from a target responsive to continuously or periodically applying a control signal to an emitter unit and applying a strobe signal to a detector pixel to cycle through a series of distance sub-ranges. In contrast, in some conventional uses of SRAM, data states may typically be held for unpredictable time durations set by sporadic access by an external system, and the memory access may be random.
Accordingly, some embodiments of the present disclosure provide detector pixels including memory array implementations and related control schemes that use sequential memory access operations that are coordinated with the cycling through the series of distance sub-ranges performed by lidar detector pixels, as well as with the time between pulses of a lidar emitter signal. Some embodiments of the present disclosure may use Dynamic Random Access Memory (DRAM)-based memory arrays for the detector pixels, with memory refresh operations performed at a sufficient refresh rate (e.g., once per emitter signal cycle, once every two emitter signal cycles, etc.) to prevent leakage of the stored value in each DRAM cell.
Embodiments of the present disclosure are further directed to improvements in circuit area and power consumption requirements in lidar applications, particularly with respect to the size and complexity of the active quench, edge sampler, PRMW, and address generator logic circuits. In particular, embodiments of the present disclosure may combine the functionality of the active quench and edge sampler circuits (and the generation of the precharge signal for the PRMW logic circuits) by synchronizing the active quench operations using a clock signal, rather than by using delay elements. Also, memory modify (i.e., increment or refresh) operations may be effectively performed by charge sharing between adjacent memory cells.
Accordingly, some embodiments of the present disclosure may provide detector pixels including memory array implementations and related control schemes that allow for the use of the clock signal to reset or “quench” each SPAD, with the state of each SPAD being held on its own capacitance. As used herein, a quench circuit may describe one or more circuits that are configured to perform sampling, quenching, and/or recharge operations as described herein. For example (with reference to
Additionally or alternatively, some embodiments of the present disclosure may provide detector pixels including memory array implementations and related control schemes that allow for memory increment or refresh operations to be performed using a logic-based counter circuit, such as linear-feedback shift register (LFSR)-based counting, rather than (or in addition to) ALU-based counting. LFSR based counting may only involve a cyclic shift operation where data is moved from one bit to the succeeding bit. This can eliminate the need for random input and output data transfer of a DRAM (or SRAM), which may require both input and output bit lines. Instead an output bit line may be shared or combined with the output bit line of the next bit in succession, which can eliminate a bit line as well as making it possible to share source/drain diffusions in the DRAM matrix leading to greater compactness.
For example, in some embodiments, a charge sharing memory array may be implemented by connecting (e.g., using a transistor switch) a bit line, which is coupled to the output of one memory cell, to the input (in particular, to the storage element) of an adjacent memory cell (with a feedback loop from the output of the last memory cell to the input of a first memory cell), thereby operating the memory cells as a linear feedback shift register (LFSR). Because the bit line capacitance (Cbl) is much greater than the capacitance (Cg) of the storage element (which may be implemented by the parasitic capacitance of a storage node transistor) of the adjacent memory cell, the charge sharing may overwrite the state held by the storage element. Increment or refresh operations may be triggered by the presence or absence of detected photons (e.g., as indicated by high or low states of signal (Photon) output from the clocked active quench circuit), respectively. As LFSR-based incrementing is a fast parallel operation (e.g., the read and write operations may be performed in parallel), binary carry chains may be eliminated. Also, address generation may be shared across many pixels, for example, using a read/write (Rd/Wr) Non-overlap Generator 450 that is shared between pixels (e.g., as shown in
Accordingly, some embodiments may allow for fully dynamic (i.e., where power may only be consumed by charging memory and SPAD parasitic capacitances) and fully synchronous (i.e., with no asynchronous activity on power supplies other than SPAD itself) SPAD pixels, using simplified per-SPAD memory increment electronics to allow for implementation of sub-10 micrometer (μm) pitch dToF pixels for short range ToF. This may allow for reduced-cost digital process compatibility (e.g., fewer requirements for eSRAM or eDRAM process modules). Fully dynamic operation of SPAD pixels (both detector and increment circuitry) may have the potential to reduce power consumption to physically achievable limits, which may be similar to figures of merit in ADC converters where fully dynamic successive approximation ADCs are close to theoretical energy consumption per operation limits. Such a dynamic pixel can target the theoretically achievable energy consumption limits per photon.
An example of a lidar system or circuit 100 that may utilize embodiments of the present disclosure is shown in
The driver electronics 116 may each correspond to one or more emitter elements, and may each be operated responsive to timing control signals with reference to a master or global clock (Clk) and/or power control signals that control the peak power of the light output by the emitter elements 115e. The driver circuit or circuitry 116 may include one or more driver transistors configured to control the modulation frequency, timing and amplitude of the optical emission signals that are output from the emitters 115e.
The emission of optical signals from multiple emitters 115e provides a single image frame for the flash LIDAR system 100. The maximum optical power output of the emitters 115e may be selected to generate a signal-to-noise ratio of the echo signal from the farthest, least reflective target at the brightest background illumination conditions that can be detected in accordance with embodiments described herein. An optional filter to control the emitted wavelengths of light, and optics 113 and diffuser 114 to increase a field of illumination of the emitter array 115 may be provided in some embodiments and are illustrated by way of example.
The receiver/detector module or circuit 110 includes an array of detector pixels (with each detector pixel including one or more detectors 110d, e.g., single photon detectors, such as SPADs), receiver optics 112 (e.g., one or more lenses to collect light over the FoV 190), and receiver electronics (including timing circuit 106) that are configured to power, enable, and disable all or parts of the detector array 110 and to provide timing signals thereto. The detector pixels can be activated or deactivated with at least nanosecond precision, and may be individually addressable, addressable by group, and/or globally addressable. In some embodiments, a spectral filter 111 may be provided to pass or allow passage of ‘signal’ light (i.e., light of wavelengths corresponding to those of the optical signals output from the emitters) but substantially reject or prevent passage of non-signal light (i.e., light of wavelengths different than the optical signals output from the emitters).
The detectors 110d of the detector array 110 are connected to the timing circuit 106. The timing circuit 106 may be phase-locked to the driver circuitry 116 of the emitter array 115, and may be controlled by the global clock (Clk). The sensitivity of each of the detectors 110d or of groups of detectors may be controlled. For example, when the detector elements include reverse-biased photodiodes, avalanche photodiodes (APD), PIN diodes, and/or Geiger-mode Avalanche Diodes (SPADs), the reverse bias may be adjusted, whereby, the higher the overbias, the higher the sensitivity.
Light emission output from one or more of the emitters 115e impinges on and is reflected by one or more targets 150, and the reflected light is detected as an optical signal (also referred to herein as a return signal, echo signal, or echo) by one or more of the detectors 110d (e.g., via receiver optics 112), converted into an electrical signal representation (referred to herein as a detection signal), and processed (e.g., based on time of flight) to define a 3-D point cloud representation 170 of the field of view 190. Operations of lidar systems in accordance with embodiments of the present disclosure as described herein may be performed by one or more processors or controllers, such as the control circuit 105 of
The control circuit 105 may include a microcontroller or microprocessor that provides different emitter control signals to the driver circuitry 116 of different emitters 115e and/or provides different signals (e.g., strobe signals) to the timing circuitry 106 of different detectors 110d to enable/disable the different detectors 110d so as to detect the echo signal from the target 150. ‘Strobing’ as used herein may refer to the generation of detector control signals (also referred to herein as strobe signals or ‘strobes’) to control the timing and/or duration of activation (also referred to herein as detection windows or strobe windows) of one or more detectors 110d of the lidar system 100. The control circuit 105 may also control memory storage operations for storing data indicated by the detection signals in a non-transitory memory or memory array 205.
The processor circuit 105′ and the timing generator 116′ may implement some of the operations of the control circuit 105 and the driver circuit 116 of
The processor circuit 105′ may provide analog and/or digital implementations of logic circuits that provide the necessary timing signals (such as quenching and gating or strobe signals) to control operation of the single-photon detectors 110d of the array 110 and process the detection signals output therefrom. For example, the single-photon detectors 110d of the array 110 may generate detection signals in response to incident photons only during the short gating intervals or strobe windows that are defined by the strobe signals. Photons that are incident outside the strobe windows have no effect on the outputs of the single photon detectors.
Detection events may be identified by the processor circuit 105′ based on one or more photon counts indicated by the detection signals output from the detector array 110, which may be stored in the memory 205. More generally, the processor circuit 105′ may include one or more circuits that are configured to generate the respective detector control signals that control the timing and/or durations of activation of the detectors 110d, and/or to generate respective emitter control signals that control the output of optical signals from the emitters 115e. In embodiments described herein, a global clock signal (Clk) may be generated and used to control the timing of the output of the optical signals (Laser Pulse) from the emitters and the quench signals (SPADRst) to reset the detectors 110d.
The processor circuit 105′ may be small enough to allow for three-dimensionally stacked implementations, e.g., with the detector array 110 “stacked” on top of the processor circuit 105′ (and/or other related circuits, such as the memory 205) that is/are sized to fit within an area or footprint of the array 110. For example, some embodiments may implement the detector array 110 on a first substrate, and transistor arrays of the circuits 105/105′ on a second substrate, with the first and second substrates/wafers bonded in a stacked arrangement, as described for example in U.S. patent application Ser. No. 16/668,271 entitled “High Quantum Efficiency Geiger-Mode Avalanche Diodes Including High Sensitivity Photon Mixing Structures and Arrays Thereof,” filed Oct. 30, 2019, the disclosure of which is incorporated by reference herein.
The pixel processor implemented by the processor circuit 105′ is configured to calculate an estimate of the average ToF aggregated over thousands of laser pulses 130 and photon returns in reflected light 135. The processor circuit 105′ may be configured to count incident photons in the reflected light 135 to identify detection events (e.g., based on one or more SPADs that have been triggered) over a laser cycle (or portion thereof). The timings and durations of the detection windows may be controlled by a strobe signal, many repetitions of which are aggregated (e.g., in the pixel) to define a sub-frame, with one or multiple sub-frames defining an image frame. Each sub-frame may correspond to a respective distance sub-range of the overall imaging distance range, where the frequency of the laser cycle may be selected based on the desired imaging distance range.
In some embodiments, a detector pixel may include one or more detectors 110d (e.g., SPADs 410d), circuits that implement a memory array (e.g., memory 205), and a memory controller (e.g., control circuit 105/processor 105′) such as a DRAM controller, collectively referred to herein as a memory circuit. In some embodiments, the DRAM controller may be implemented with simplified or minimal circuitry, for example, using a XOR-based LFSR feedback loop, precharge transistors, and two NOR gates per word, as described in further embodiment herein.
The DRAM-based pixel 300 of
The refresh rate of the DRAM cells is also controlled by the memory controller 305c. In some embodiments, the refresh rate is selected such that memory refresh operations for all DRAM cells in the memory array 305a can be completed within the time (or period T) between emitter signal pulses (e.g., laser pulses). The time between laser pulses (which defines a laser cycle, or more generally emitter pulse frequency) may be selected or may otherwise correspond to a desired imaging distance range for the lidar system. In some embodiments, the refresh rate may be some integer multiple R of the laser frequency or rep rate, where for 1 in R laser cycles, the system may read, modify, and write all bins, and in the other R-1 cycles the system would read, modify, and write bins only if there was a photon detected.
In embodiments described herein, a refresh operation may be achieved by using a multiplexer in the clocked active quench circuit 302 (e.g., MODE=0 or Photon=0, pulse on Refresh) to force an increment of the memory cells for each of the n memory bins. This can be a deterministic increment which may require a relatively small value in terms of the dynamic range of the memory bins available for photon counting. However, this value is known and can be subtracted from the memory values. Retention times of a few milliseconds (ms) may be expected, which may allow fewer than 10 refresh cycles in a 10 ms full exposure occupying only 4 bits of the memory bin width k, which can be over 16 bits. This may be a simpler operation than using external circuitry to change the direction of LFSR data shift during a refresh operation.
An example implementation of the clocked active quench circuit 302 of
As shown in the timing diagram of
The clocked active quench circuit 302 of
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As shown in
Each of the increment and refresh operations for the DRAM-based pixels described herein may include a precharge-read-modify-write (PRMW) operation, in which the current contents of a given memory bin 0 to n−1 is read, incremented (responsive to the presence of detection events) or refreshed (responsive to the absence of detection events), and written back to the respective memory bin. The retention time of the voltage on the storage node can determine a maximum refresh period required to maintain a stored logic state for each DRAM cell. In some embodiments, the time to complete a refresh operation may be such that each DRAM cell of the memory array may be refreshed in the time between pulses of the lidar emitter signal; however, the period or frequency of performing the refresh operations may be dependent on the leakage (also referred to herein with reference to retention time) of the DRAM cells, which can vary with temperature. As such, it will be understood that refresh operations may be performed more or less frequently, or otherwise as needed to meet the leakage requirements of the DRAM cells under the operating conditions.
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In the DRAM array of
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More particularly, as shown in
In the examples of
In some embodiments, the memory may be gain cell-based memory (e.g., gain cell-eDRAM). Example gain cell-eDRAM (GC-eDRAM) transistor arrangements that may be used in memory cell arrays in accordance with embodiments of the present disclosure may be as described in Meinerzhagen et al., “Gain-Cell Embedded DRAMs for Low-Power VLSI,” Springer International Publishing AG (2018). These transistor arrangements are provided by way of example only, and embodiments of the present disclosure are not limited thereto. The use of gain cell DRAM may require fewer transistors per pixel (e.g., 1-3 transistors) of a same type (e.g., NMOS-only, or PMOS-only) as compared to SRAM implementations, with memory refresh operations performed that may be at a sufficient refresh rate (e.g., once per emitter signal cycle, once every two emitter signal cycles, etc.) to prevent leakage of the stored value in each DRAM cell, and may be completed within the time between pulses of a lidar emitter signal. In some embodiments, the state of the DRAM cell may be held on its own parasitic capacitance (e.g., the parasitic capacitance of its storage node transistor).
Some embodiments may include two transistor (2T) and/or three transistor (3T) DRAM configurations, where the DRAM cells of each memory bin can be incremented in response to a detection event, or can be refreshed periodically and/or in the absence of detection events, during the time between pulses of the emitter signal. For example, for a 200 meter (m) imaging distance range, an emitter cycle may have a frequency of 750 kHz, with a period of about 1.33 μs between pulses of the emitter signal. The maximum refresh time for a memory bin in this example may correspond to the 1.33 μs emitter cycle, which may be sufficient to overcome bit leakage issues (e.g., at temperatures of about 125° C. or more).
In particular, in the example of
Similarly, in the example of
In the implementations shown in
More generally, in the implementations shown in
Some embodiments may require increased LFSR decoder power in some regions (e.g., edge regions) of the memory array, but may provide reduced LFSR+DRAM power in other regions (e.g., in the central regions) of the memory array, which may allow for easier or more efficient power distribution. Embodiments described herein may be used to achieve pixel parameters (e.g., pixel pitch, on the order of micrometers) that may be used in various applications, for example (but not limited to) high dynamic range (HDR) multi-megapixel resolution direct or indirect time of flight image sensors. Also, even pixels with two to four bins (which may be conventionally used in iToF) can be used in strobed mode with power stepping or variation of emission power for different strobe windows (as described for example in U.S. Patent Application Publication No. 2020/0249318 entitled “Strobe Window Dependent Illumination for Flash LIDAR” to Henderson et al., the disclosure of which is incorporated by reference herein) to achieve dToF. Embodiments described herein may achieve pixel pitches of less than about 10 μm, for example, of between about 3 to 10 μm in some embodiments.
Embodiments using LFSR-based counting as discussed above may allow for relaxed bin timing, simplified operation, and reduced power. As discussed above, a DRAM pixel (e.g., 300, 900) using LFSR-based counting may be used with a single SPAD input per pixel 410p, e.g., where the increment operation is performed in response to the presence of a detection event by sequentially shifting data stored in a storage element (e.g., 625-1, 825-1) to a bit line of a succeeding memory cell 601 in a same row, and a refresh operation is performed in response to the absence of a detection event. However, problems may arise in implementations with multiple SPADs per pixel, as the LFSR 305c2 may not be shifted multiple times within the duration of a single bin in order to account for multiple or all SPAD firings, unless a more complex multiplexing scheme is used.
Further embodiments of the present disclosure may provide DRAM pixels using LFSR-based counting in combination with inputs from multiple SPADs per pixel by using partial ALU-based counting. For example, in some embodiments a partial ALU circuit may be used for counting lower or less significant bits (e.g., for the 3 least significant bits), allowing for faster settling response without significant power draw or area implications.
As shown in the timing diagram of
Further embodiments of the present disclosure are directed to improvements in active quench and recharge schemes in lidar applications. As noted above, a SPAD may be quenched and recharged using passive or active schemes. In a passive recharge scheme, the voltage across a SPAD may be ramped through an RC circuit (e.g., a reset or recharge transistor or resistor (R) in series with the diode's resistance, and the associated capacitances (C)). However, the RC time constant may be large and/or may otherwise cause the dead time of the SPAD to be too long for operation in high-count-rate scenarios. In other situations, the RC time constant may be too short to release deep charge traps between consecutive avalanches, which may result in high afterpulsing rates (i.e., the triggering of a new avalanche due to the release of a trapped charge carrier from a previous avalanche event rather than a new incident photon) may result. Also, because the probability of inducing an avalanche may depend on the overbias of the SPAD and the overbias may gradually change during the charging of the junction capacitance, the photon detection probability may vary with time, and a long time (e.g., many multiples of the RC time constant) may be required for the overbias to reach its optimal value. In addition, because the RC time constant may depend on analog properties of the SPADs, it may vary differently across a the SPADs of a large array and between SPADs, and may also vary with operating temperature, resulting in non-uniform operation of pixels and devices.
In an active recharge scheme, a sensing circuit may be configured to sense the onset of an avalanche and, following a preset delay can actively switch current through a low resistance path to quickly recharge the SPAD. This can result in a more deterministic operation of the pixel because a respective detector may have either a charged or discharged state, and the probability of detection in a charged state may be consistent or fixed. However, because the recharging in an active recharge scheme may be almost instantaneous, large current spikes can result. For example, for a SPAD with a junction capacitance of about 20 femtofarads (fF), a detector array including 1 million SPADs may have a total capacitance (excluding interconnect capacitance) of about 20 nanofarads (nF). A difference in voltage between a discharged state and a charged state of each SPAD may be about 5V, and recharging may be completed within 500 picoseconds (psec) for desired operation. In lidar applications, all SPADs of the detector array may be discharged instantaneously, for example if a retroreflector is imaged by the detector array. Not accounting for the discharge current spike resulting from the detection event (which may be substantial), the resulting active recharge current spike to recharge a SPAD with a capacitance of 20 nF to 5V in 500 psec may be estimated as 20 nF×5V/500 psec=200 A per SPAD. If this is driven by a pulse with a 100 psec rise time, the change in current over time dI/dt=200 A/100 psec=2 kA/nsec, and the self-induced emf (ε) may be approximated by ε=−L (dI/dt). As such, with very high dI/dt, even with small inductances, e.g., resulting from packaging leads, traces, or interconnects, very large emf will be created, which will result in undesirable circuit performance.
Further embodiments of the present disclosure may provide quench and recharge circuits configured to addresses such current spikes and associated emf issues. In particular, embodiments of the present disclosure may provide active quench and recharge operations responsive to a clock signal (such as the global clock signal (Clk), as discussed above with reference to
For example, a clocked active recharge circuit may be implemented by coupling the detection signal (VSPAD) output from a photodetector (e.g., a SPAD) to a logic circuit (e.g., one or more flip-flops arranged as a shift register) sampled by the global clock signal (Clk; which may also control operation of the emitter elements and/or bin widths) to provide the quench or recharge signal (SPADRst) to a reset or recharge circuit (e.g., a reset transistor) that resets the photodetector at a respective delay time relative to one or more other photodetectors. The recharge signal (SPADRst) may thus be generated responsive to (i) an avalanche or detection event (e.g., as indicated by a detection signal (VSPAD) output from a SPAD), and (ii) after or following the respective delay time associated with the SPAD after the next clock signal (Clk).
The logic circuit may be configured to generate a fixed delay value and/or a group-specific delay value. In some embodiments, the group-specific delay may be generated by a variable delay line. The delay value(s) may be generated by one or more delay elements within a respective pixel in some embodiments. In some embodiments, a common delay value may be generated for groups of pixels. In some embodiments, the delay value(s) may be generated globally for the detector array. In some embodiments, the delay value(s) may be generated in an analog fashion, e.g., through RC delays across the chip or IC including the detector array.
An example implementation of the clocked active recharge circuit 302′ is shown in the schematic block diagram of
As shown in
In the timing diagram of
In other embodiments, the timing of recharge signal (SPADRst) for a respective SPAD 410d may be implemented by delay of the clock signal Clk, likewise on a per-pixel or a per-detector basis. In some embodiments, such a delay in the recharge time may be inherent in providing offset detector control signals to implement histogram data that is offset by a fraction of a bin, as described in copending U.S. patent application Ser. No. 17/391,864 entitled “Methods And Systems For Power-Efficient Subsampled 3d Imaging,” the disclosure of which is incorporated by reference herein in its entirety.
Using clocked active recharge and delay schemes as described herein, even when multiple or all SPADs of a detector array fire or discharge simultaneously, the change in recharge current over time (dI/dt) is greatly reduced, thus reducing the self-induced emf as well as other resulting electrical problems (e.g., signal bounce). Since the current decreases, any I-R drops which can result in overbias non-uniformities across the array may also be reduced. According to some embodiments, the distribution (or collective duration) of the respective delays may be greater than the required active recharge time, but significantly shorter than the dead time of the SPAD. As such, the dead times of the respective SPADs may be substantially uniform, resulting in approximately uniform performance of all SPADs, regardless of their assigned delay. In contrast, some conventional active quench and recharge operations may be self-timed or asynchronous, i.e., the recharge or reset signal may be generated based on or relative to a delay from the prior avalanche, rather than based on a clock signal.
Lidar systems and arrays described herein may further be applied to ADAS (Advanced Driver Assistance Systems), autonomous vehicles, UAVs (unmanned aerial vehicles), industrial automation, robotics, biometrics, modeling, augmented and virtual reality, 3D mapping, and security. In some embodiments, the emitter elements of the emitter array may be vertical cavity surface emitting lasers (VCSELs). In some embodiments, the emitter array may include a non-native substrate having thousands of discrete emitter elements electrically connected in series and/or parallel thereon, with the driver circuit implemented by driver transistors integrated on the non-native substrate adjacent respective rows and/or columns of the emitter array, as described for example in U.S. Patent Application Publication No. 2018/0301872 to Burroughs et al., filed Apr. 12, 2018, with the United States Patent and Trademark Office, the disclosure of which is incorporated by reference herein.
Various embodiments have been described herein with reference to the accompanying drawings in which example embodiments are shown. These embodiments may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concept to those skilled in the art. Various modifications to the example embodiments and the generic principles and features described herein will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not shown to scale, and in some instances may be exaggerated for clarity. Like numbers refer to like elements (or examples of like elements) throughout.
The example embodiments are mainly described in terms of particular methods and devices provided in particular implementations. However, the methods and devices may operate effectively in other implementations. Phrases such as “example embodiment”, “one embodiment” and “another embodiment” may refer to the same or different embodiments as well as to multiple embodiments. The embodiments will be described with respect to systems and/or devices having certain components. However, the systems and/or devices may include fewer or additional components than those shown, and variations in the arrangement and type of the components may be made without departing from the scope of the inventive concepts.
The example embodiments may be described in the context of particular methods having certain steps or operations. However, the methods and devices may operate effectively for other methods having different and/or additional steps/operations and steps/operations in different orders that are not inconsistent with the example embodiments. Thus, the present inventive concepts are not intended to be limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features described herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It also will be understood that, as used herein, the term “comprising” or “comprises” is open-ended, and includes one or more stated elements, steps and/or functions without precluding one or more unstated elements, steps and/or functions. The term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present inventive concepts.
It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
In the drawings and specification, there have been disclosed embodiments of the disclosure and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the present invention being set forth in the following claims.
This application claims priority from U.S. Provisional Patent Application Ser. No. 63/077,101, filed Sep. 11, 2020, the disclosure of which is incorporated by reference herein in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2021/049194 | 9/7/2021 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63231009 | Aug 2021 | US | |
| 63077101 | Sep 2020 | US |
