Closed loop feedback control of integrated circuits

Information

  • Patent Grant
  • 9407241
  • Patent Number
    9,407,241
  • Date Filed
    Thursday, August 16, 2012
    12 years ago
  • Date Issued
    Tuesday, August 2, 2016
    8 years ago
Abstract
Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
Description
FIELD OF THE INVENTION

Embodiments in accordance with the present invention relate to systems and methods for closed loop feedback control of integrated circuits.


BACKGROUND

In order to operate an integrated circuit, e.g., a microprocessor, in an efficient manner, for example, to consume a low amount of energy to accomplish a task, it is known to adjust various controlling parameters. These parameters may include an operating voltage that can be adjusted to a value characteristic of an advantageous power condition in accordance with the task to be accomplished. For example, an operating voltage is set to a minimized value consistent with a desired frequency of operation. In the conventional art, such operating points are applied in an open loop manner.


SUMMARY OF THE INVENTION

Therefore, systems and methods for closed loop feedback control of integrated circuits are highly desired.


Accordingly, systems and methods for closed loop feedback control of integrated circuits are disclosed. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.


In accordance with other embodiments of the present invention, a plurality of controllable input values to an integrated circuit is determined that achieves a desirably low power operating condition of the integrated circuit for a given operating frequency.


In accordance with yet other embodiments of the present invention, a dynamic operating condition of an integrated circuit is measured for a specific operating frequency at controllable input values that achieve an advantageous low power operating condition of the integrated circuit.


In one exemplary embodiment of the present invention, the integrated circuit is a microprocessor capable of operating at various frequencies and voltages.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 illustrates a microprocessor comprising dynamic condition reporting registers, in accordance with embodiments of the present invention.



FIG. 2 illustrates a method of operating an integrated circuit, in accordance with embodiments of the present invention.



FIGS. 3A and 3B illustrate an exemplary application of portions of a method of operating an integrated circuit, in accordance with embodiments of the present invention.



FIG. 4 illustrates a microprocessor, in accordance with embodiments of the present invention.





DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the present invention, system and method for closed loop feedback control of integrated circuits, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.


Notation and Nomenclature

Some portions of the detailed descriptions that follow (e.g., process 200) are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that can be performed on computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.


It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “storing” or “dividing” or “computing” or “testing” or “calculating” or “determining” or “storing” or “measuring” or “adjusting” or “generating” or “performing” or “comparing” or “synchronizing” or “accessing” or “retrieving” or “conveying” or “sending” or “resuming” or “installing” or “gathering” or the like, refer to the action and processes of a computer system, processor, or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.


Closed Loop Feedback Control of Integrated Circuits

Embodiments in accordance with the present invention are described in the context of design and operation of integrated semiconductors. More particularly, embodiments of the present invention relate to systems and methods for closed loop feedback control of integrated circuits. It is appreciated, however, that elements of the present invention may be utilized in other areas of semiconductor operation.


Several operational indicators of an integrated circuit, e.g., a microprocessor, can be measured dynamically, e.g., in-situ while the integrated circuit is in operation. For example, the operating temperature of the integrated circuit can be measured. Such measurements can be external, e.g., via an applied thermocouple, or they can be made internally, e.g., via on-chip measurement circuits.


A wide variety of integrated circuit characteristics can be measured or determined, either directly or inferred from other characteristics, while the device is operating. For example, in addition to temperature, other characteristics such as gate delays, metal delays, leakage current, “on” or active current, relative behavior of NMOS and PMOS devices, maximum frequency and the like can be measured or determined for the instant operating conditions of an integrated circuit. Co-pending, commonly owned U.S. patent application Ser. No. 10/124,152, filed Apr. 16, 2002, entitled “System and Method for Measuring Transistor Leakage Current with a Ring Oscillator” and incorporated by reference herein, provides exemplary systems and methods of such dynamic determinations, or dynamic operating indicators, that are well suited to embodiments in accordance with the present invention.


Such measurements or indications are typically made available, e.g., to state machines and/or processor control software, via registers. Such register values frequently comprise a count of a number of events, e.g., oscillations of a ring oscillator in a given time interval. It is appreciated that there are many methods of creating such indications, and all such indications are well suited to embodiments in accordance with the present invention. For the purpose of illustrating embodiments in accordance with the present invention, a model of a register reporting a value that is correlated to an operating characteristic of an integrated circuit is employed. It is to be appreciated, however, that embodiments in accordance with the present invention are well suited to a variety of systems and methods of determining and reporting dynamic operating conditions of an integrated circuit.



FIG. 1 illustrates a microprocessor 100 comprising dynamic condition reporting registers, in accordance with embodiments of the present invention. Dynamic condition reporting registers R1101, R2102 and R3103 each indicate a dynamic condition metric of microprocessor 100. For example, generally each dynamic condition reporting register is associated with a dynamic condition measuring circuit either as a part of the integrated circuit or external to the integrated circuit. Conversion of a measured quantity, e.g., oscillations of a particular ring oscillator, into a usable metric related to the measured quantity, e.g., a frequency measurement, e.g., in hertz, or a count of oscillations per unit time, can be embodied in either software or hardware, and all such embodiments are to be considered within the scope of the present invention. For example, logic circuitry can increment a counting register for each oscillation for a period of time. If the count exceeds a predetermined limit, an interrupt can be created to enable software adjustment of a feedback loop. Alternatively, for example, a software timing loop, with or without hardware timing assistance, can count a number of oscillations per unit time. In accordance with embodiments of the present invention, dynamic condition reporting registers, e.g., dynamic condition reporting registers R1101, R2102 and R3103, can refer to any memory location utilized to store such indications of a dynamic condition.


As operating conditions of microprocessor 100 change, values reported by dynamic condition reporting registers R1101, R2102 and R3103 will generally change. For example, operating voltage and operating temperature are strong influences on a maximum operating frequency achievable by an integrated circuit. As operating voltage and/or operating temperature vary, so too in general will the values reported by dynamic condition reporting registers R1101, R2102 and R3103.


For example, dynamic condition reporting register R1101 can indicate a number of oscillations per time of a ring oscillator comprising complementary metal oxide inverter gates. Such a circuit can be utilized to indicate gate delays for the microprocessor at the instant operating conditions, e.g., operating temperature, operating voltage and the like. Similarly, other dynamic condition reporting registers can indicate other operational characteristics of microprocessor 100. For example, device leakage, gate leakage, temperature, metal delays, “on” current, behavior of n type and p type devices and/or relative behavior of n type and p type devices can be reported by dynamic condition reporting registers.


Most useful dynamic conditions indications will have a correlation with maximum achievable operating frequency of an integrated circuit at those operating conditions. For example, an indication of operating temperature will generally have a negative correlation with maximum achievable operating frequency (for operating voltages above about 0.6 volts). For example, as operating temperature increases, maximum achievable operating frequency generally decreases. Other dynamic condition indications may have a positive correlation with maximum achievable operating frequency. For example, the number of oscillations of a NAND-gate ring oscillator per unit time will generally increase as maximum achievable operating frequency of an integrated circuit increases.


Such correlations among dynamic conditions and maximum achievable operating frequency can be utilized in a system of closed loop feedback involving the condition registers, to optimize power consumption for operating an integrated circuit at a particular frequency.



FIG. 2 illustrates a process 200 of operating an integrated circuit, in accordance with embodiments of the present invention. In optional block 210, a plurality of controllable input values to an integrated circuit is determined that achieves a desired power operating condition of the integrated circuit for a given operating frequency. In accordance with one embodiment of the present invention, the condition is a desired low power operating condition. Exemplary controllable inputs to an integrated circuit can include, for example, operating voltage(s), body biasing voltage(s) applied to NMOS devices and/or body biasing voltage(s) applied to PMOS devices.


For example, an integrated circuit tester can run test vectors against an integrated circuit at a particular operating frequency for a fixed operating temperature. Controllable inputs to the integrated circuit, e.g., operating voltage(s) and/or body biasing voltage(s), can be adjusted to decrease power consumption of the integrated circuit consistent with proper operation at the particular operating frequency. Power consumption of the integrated circuit should be minimized consistent with proper operation at the particular operating frequency. Block 200 can be repeated for a plurality of different operating frequencies and/or temperatures.


In optional block 220, a dynamic operating indicator of the integrated circuit is observed for the specific operating frequency at the controllable input values determined in block 210. For example, a dynamic condition reporting register value corresponding to a ring oscillator can be read, either by an integrated circuit tester or under software control. It is to be appreciated that such dynamic operating conditions are generally determined in digital form, e.g., as a count of events. However, embodiments in accordance with the present invention are well suited to the use of analog condition reporting, e.g., a condition expressed as a voltage or charge stored on a floating gate.


In optional block 230, the dynamic operating indicator value is stored to a first computer usable media. Such a dynamic operating condition value is well suited to a wide variety of storing methods and media. For example, such a value can be stored in non-volatile memory of the integrated circuit, in non-volatile memory of an integrated circuit package, or on media separate from the integrated circuit, e.g., on a separate non-volatile memory integrated circuit or in a computer system database. In accordance with an embodiment of the present invention, the indicator may be stored in a register of a microprocessor.


In optional block 240, the predetermined dynamic operating indicator value is accessed from a second computer usable media. It is to be appreciated that the first and second computer usable media can be the same media. Alternatively, the first and second computer usable media can be separate media. Embodiments in accordance with the present invention are well suited to utilizing a wide variety of media and techniques known to the data processing arts to transfer information of the dynamic operating condition between the first and second computer usable media.


It is to be appreciated that the predetermined dynamic operating indicator value is generally frequency specific. Consequently, if it is desirable to operate the integrated circuit at a different operating frequency, block 240 may be repeated to obtain a predetermined dynamic operating indicator value corresponding to the different operating frequency.


In block 250, a plurality of controllable inputs to an integrated circuit is adjusted to achieve the predetermined value of a dynamic operating indicator of the integrated circuit. It is to be appreciated that, in general, each controllable input can be adjusted independently of other such controllable inputs. In some cases, a range of controllable input values, e.g., a body bias voltage, can be influenced by another controllable input value, e.g., operating voltage. In optional block 260, block 250 is periodically repeated.


In accordance with embodiments of the present invention, the predetermined dynamic operating condition can be determined for a specific integrated circuit or for a group of integrated circuits, e.g., those from a common wafer, a production run or by part number.


In accordance with other embodiments of the present invention, the predetermined dynamic operating condition may comprise evaluation of a function and/or lists of values. Such a function may present a condition that the system attempts to have dynamic operating indicators meet. For example, it may be desirable to control a combination of dynamic operating condition values. Referring once again to FIG. 1, the predetermined dynamic operating condition could be determined as three times the value of register R1101 squared plus 17 times the value of register R2102 plus the value of register R3103. Other functions and/or operations, e.g., boundary operations such as MIN and MAX, can further be applied to dynamic operating condition values. All such manipulations of dynamic operating condition values to form a predetermined dynamic operating condition are well suited to embodiments in accordance with the present invention.


In this novel manner, an operating condition of an integrated circuit, e.g., power consumption of a microprocessor, can be advantageously controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior. Under the conventional art, controllable inputs to an integrated circuit, e.g., operating voltage, were based on open loop methods that provided, for example, a recommended operating voltage for a given operating frequency and/or temperature.



FIGS. 3A and 3B illustrate an exemplary application of portions of process 200, in accordance with embodiments of the present invention. Computer system 300 comprises microprocessor 100. Microprocessor 100 comprises dynamic condition reporting register R1101. Dynamic condition reporting register R1101 indicates a dynamic condition metric of microprocessor 100, e.g., a number of oscillations of a ring oscillator for a given time period. The time period may be externally measured, for example via a stable oscillator, e.g., a quartz oscillator. As operating conditions of microprocessor 100 change, values reported by dynamic condition reporting register R1101 will generally change. For the purposes of the present example, assume that the value reported by dynamic condition reporting register R1101 is positively correlated with maximum achievable operating frequency of microprocessor 100. For example, the greater the value in dynamic condition reporting register R1101, the faster that microprocessor 100 can run. It is appreciated that embodiments in accordance with the present invention are well suited to negative correlations between dynamic condition reporting register values and maximum achievable operating frequency of a microprocessor.


Computer system 300 further comprises a first variable voltage supply 310 to provide an operating voltage to microprocessor 100. Optionally, computer system 300 can comprise a second variable voltage supply 320 to provide a body biasing voltage to n type devices, e.g., NMOS devices, of microprocessor 100. Similarly, computer system 300 can optionally comprise a third variable voltage supply 330 to provide a body biasing voltage to p type devices, e.g., PMOS devices, of microprocessor 100.


Computer system 300 also comprises a memory 340 coupled to microprocessor 100 that can be used to store data and programs for execution on microprocessor 100. Further, computer system 300 comprises a memory 350 for storing a predetermined value for a dynamic condition indicator. Memory 350 is well suited to being a part of memory 340, e.g., a location within memory 350.


The predetermined value for a dynamic condition indicator stored in memory 350, “27000000,” represents a value of dynamic condition reporting register R1101 that was previously determined. For example, this value can represent the value of dynamic condition reporting register R1101 that corresponds to the lowest power operation of microprocessor 100 at a particular operating frequency, e.g., 500 MHz.


Referring now to FIG. 3A, at a point in time when microprocessor 100 is operating at 500 MHz, dynamic condition reporting register R1101 reports a value of “45838210.” Controllable inputs to microprocessor 100, e.g., operating voltage provided by first variable voltage supply 310 and body biasing voltages provided by second and third variable voltage supplies 320 and 330, are adjusted to achieve the predetermined value for dynamic condition reporting register R1101, e.g., “27000000.” For example, first variable voltage supply 310 can be commanded to reduce the operating voltage provided to microprocessor 100. It is to be appreciated that any or all controllable inputs can be adjusted in any combination and/or sequence in order to achieve the predetermined value for dynamic condition reporting register R1101, in accordance with embodiments of the present invention.


Referring now to FIG. 3B, after such adjustments of controllable inputs to microprocessor 100, dynamic condition reporting register R1101 reports a value of “27241467” that is very close to the predetermined value for dynamic condition reporting register R1101, “27000000.” It is to be appreciated that the actual predetermined value for dynamic condition reporting register R1101 may not be achievable for a variety of reasons, including, for example, an operating temperature difference for microprocessor 100 between the point when the predetermined value for dynamic condition reporting register R1101 was determined and the point in time represented by FIG. 3B.



FIG. 4 illustrates a microprocessor 400, in accordance with embodiments of the present invention. Microprocessor 400 is configured to operate from a plurality of variable voltage supplies or controllable inputs, e.g., variable voltage supplies 410, 420 and 430. Variable voltage supply 410 provides a variable operating voltage to microprocessor 400. Variable voltage supply 420 provides a variable body biasing voltage to n type devices, e.g., NMOS devices, of microprocessor 400. Variable voltage supply 430 provides a variable body biasing voltage to p type devices, e.g., PMOS devices, of microprocessor 400.


Microprocessor 400 further comprises a plurality of dynamic operating indicators for indicating operating conditions of microprocessor 400, e.g., dynamic operating indicator circuits 440, 450, 460, 470, and 480. One or more of dynamic operating indicator circuits 440, 450, 460, 470, and 480 are well suited to the systems and methods taught in co-pending, commonly owned U.S. patent application Ser. No. 10/124,152, filed Apr. 16, 2002, entitled “System and Method for Measuring Transistor Leakage Current with a Ring Oscillator” and incorporated by reference herein.


Typically such dynamic operating indicator circuits will be situated in a variety of locations throughout a microprocessor integrated circuit. A wide variety of factors, including semiconductor process variation across an integrated circuit and other well known circuit layout influences, should be considered to determine where such dynamic operating indicator circuits are placed. Generally, each dynamic operating indicator circuit, e.g., dynamic operating indicator circuit 440, will have an associated dynamic operating indicator, e.g., register 401. The dynamic operating indicator 401 presents a measurement of a current integrated circuit operating characteristic, as measured by a dynamic operating indicator circuit, to microprocessor circuitry and/or software in a straightforward manner. It is to be appreciated that a direct correspondence between dynamic operating indicator circuits and dynamic operating indicators is exemplary, and that other structures to determine a current integrated circuit operating characteristic are well suited to embodiments in accordance with the present invention. For example, register 401 may represent a plurality of dynamic operating indicators. A selector mechanism can be provided to select which dynamic operating indicator is reported in register 401 at a particular time.


Embodiments in accordance with the present invention, systems and methods for closed loop feedback control of integrated circuits, are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.

Claims
  • 1. A method, comprising: measuring an operating indicator of an integrated circuit; andadjusting one or more controllable inputs to said integrated circuit to cause a measured value of said operating indicator to approach a desired value of said operating indicator.
  • 2. The method of claim 1 wherein said one or more controllable inputs comprises an operating voltage of said integrated circuit.
  • 3. The method of claim 1 wherein said one or more controllable inputs comprises a body bias voltage applied to a body well of said integrated circuit.
  • 4. The method of claim 1 wherein said one or more controllable inputs comprises an operating frequency control input.
  • 5. The method of claim 1 wherein said integrated circuit comprises a microprocessor.
  • 6. The method of claim 5 wherein said operating indicator comprises a ring oscillator.
  • 7. The method of claim 6 wherein said measuring comprises counting cycles of said ring oscillator.
  • 8. An integrated circuit comprising: circuitry configured to measure an indicator of a behavior of said integrated circuit; andcircuitry configured to adjust a controllable input to said integrated circuit to cause a measured value of said indicator to approach a desired value of said indicator.
  • 9. The integrated circuit of claim 8 wherein said controllable input comprises an operating voltage of said integrated circuit.
  • 10. The integrated circuit of claim 8 wherein said controllable input comprises a body bias voltage applied to a body well of said integrated circuit.
  • 11. The integrated circuit of claim 8 wherein said controllable input comprises an operating frequency control input.
  • 12. The integrated circuit of claim 8 wherein said indicator indicates a gate delay of said integrated circuit.
  • 13. The integrated circuit of claim 12 wherein said indicator indicates a leakage current of said integrated circuit.
  • 14. The integrated circuit of claim 6 wherein said indicator indicates a behavior of only one type of device from the set of P-FETs and N-FETs.
  • 15. An article of manufacture including a computer readable medium having instructions stored thereon that, if executed by a computing device, cause the computing device to perform operations comprising: measuring an operating indicator of an integrated circuit; andadjusting one or more controllable inputs to said integrated circuit to cause a measured value of said operating indicator to approach a desired value of said operating indicator.
  • 16. The article of manufacture of claim 15 wherein said integrated circuit comprises said computing device.
  • 17. The article of manufacture of claim 15 wherein said one or more controllable inputs comprises an operating voltage of said integrated circuit.
  • 18. The article of manufacture of claim 15 wherein said one or more controllable inputs comprises a body bias voltage applied to a body well of said integrated circuit.
  • 19. The article of manufacture of claim 15 wherein said operating indicator comprises a ring oscillator.
  • 20. The article of manufacture of claim 15 wherein said operating indicator indicates a behavior of only n-type MOSFETs.
RELATED APPLICATIONS

This is a Continuation application of, and claims benefit to, U.S. patent application Ser. No. 12/651,244, now U.S. Pat. No. 8,253,434, filed Dec. 31, 2009, to Koniaris and Burr, which in turn was a Continuation application of, and claimed benefit to, U.S. Pat. No. 7,671,621, filed Feb. 26, 2008, to Koniaris and Burr, which in turn was a Continuation application of, and claimed benefit to, U.S. Pat. No. 7,336,092, filed Jul. 19, 2006, to Koniaris and Burr, which in turn was a continuation patent application of, and claimed benefit to, U.S. Pat. No. 7,180,322, filed on Sep. 30, 2005. All such applications are hereby incorporated herein by reference in their entireties. U.S. Pat. No. 7,180,322 was a continuation in part of, and claimed benefit to, U.S. Pat. No. 6,882,172, entitled “System and Method for Measuring Transistor Leakage Current with a Ring Oscillator” to Suzuki and Burr, which is hereby incorporated herein by reference in its entirety. U.S. Pat. No. 7,180,322 was a continuation in part of, and claimed benefit to, U.S. Pat. No. 6,885,210, entitled “A System and Method for Measuring Transistor Leakage Current with a Ring Oscillator with Backbias Controls” to Suzuki, which is hereby incorporated herein by reference in its entirety. U.S. Pat. No. 7,180,322 was a continuation in part of, and claimed benefit to, U.S. Pat. No. 7,941,675, entitled “Adaptive Power Control” to Burr et al., which is hereby incorporated herein by reference in its entirety.

US Referenced Citations (251)
Number Name Date Kind
4246517 Dakroub Jan 1981 A
4335445 Nercessian Jun 1982 A
4679130 Moscovici Jul 1987 A
4739252 Malaviya et al. Apr 1988 A
4769784 Doluca et al. Sep 1988 A
4794278 Vajdic Dec 1988 A
4798974 Reczek et al. Jan 1989 A
4893228 Orrick et al. Jan 1990 A
4912347 Morris Mar 1990 A
4929621 Manoury et al. May 1990 A
5039877 Chern Aug 1991 A
5086501 DeLuca et al. Feb 1992 A
5103110 Housworth et al. Apr 1992 A
5113088 Yamamoto et al. May 1992 A
5124632 Greaves Jun 1992 A
5167024 Smith et al. Nov 1992 A
5201059 Nguyen Apr 1993 A
5204863 Saint-Joigny et al. Apr 1993 A
5218704 Watts, Jr. et al. Jun 1993 A
5230055 Katz et al. Jul 1993 A
5239652 Seibert et al. Aug 1993 A
5254883 Horowitz et al. Oct 1993 A
5336986 Allman Aug 1994 A
5386135 Nakazato et al. Jan 1995 A
5394026 Yu et al. Feb 1995 A
5406212 Hashinaga et al. Apr 1995 A
5410278 Itoh et al. Apr 1995 A
5422591 Rastegar et al. Jun 1995 A
5422806 Chen et al. Jun 1995 A
5440520 Schutz et al. Aug 1995 A
5447876 Moyer et al. Sep 1995 A
5461266 Koreeda et al. Oct 1995 A
5483434 Seesink Jan 1996 A
5495184 Des Rosiers et al. Feb 1996 A
5502838 Kikinis Mar 1996 A
5506541 Herndon Apr 1996 A
5511203 Wisor et al. Apr 1996 A
5513152 Cabaniss Apr 1996 A
5519309 Smith May 1996 A
5560020 Nakatani et al. Sep 1996 A
5568103 Nakashima et al. Oct 1996 A
5592173 Lau et al. Jan 1997 A
5594360 Wojciechowski Jan 1997 A
5680359 Jeong Oct 1997 A
5682093 Kivela Oct 1997 A
5692204 Rawson et al. Nov 1997 A
5717319 Jokinen Feb 1998 A
5719800 Mittal et al. Feb 1998 A
5727208 Brown Mar 1998 A
5744996 Kotzle et al. Apr 1998 A
5745375 Reinhardt et al. Apr 1998 A
5752011 Thomas et al. May 1998 A
5754869 Holzhammer et al. May 1998 A
5757171 Babcock May 1998 A
5764110 Ishibashi Jun 1998 A
5778237 Yamamoto et al. Jul 1998 A
5781060 Sugawara Jul 1998 A
5812860 Horden et al. Sep 1998 A
5815724 Mates Sep 1998 A
5815725 Feierbach Sep 1998 A
5818290 Tsukada Oct 1998 A
5825674 Jackson Oct 1998 A
5838189 Jeon Nov 1998 A
5842860 Funt Dec 1998 A
5848281 Smalley et al. Dec 1998 A
5884049 Atkinson Mar 1999 A
5894577 MacDonald et al. Apr 1999 A
5900773 Susak May 1999 A
5920226 Mimura Jul 1999 A
5923545 Nguyen Jul 1999 A
5929621 Angelici et al. Jul 1999 A
5933649 Lim et al. Aug 1999 A
5940020 Ho Aug 1999 A
5940785 Georgiou et al. Aug 1999 A
5940786 Steeby Aug 1999 A
5952871 Jeon Sep 1999 A
5974557 Thomas et al. Oct 1999 A
5977763 Loughmiller et al. Nov 1999 A
5986947 Choi et al. Nov 1999 A
5996083 Gupta et al. Nov 1999 A
5996084 Watts Nov 1999 A
5999040 Do et al. Dec 1999 A
6006169 Sandhu et al. Dec 1999 A
6011403 Gillette Jan 2000 A
6018264 Jin Jan 2000 A
6021500 Wang et al. Feb 2000 A
6035407 Gebara et al. Mar 2000 A
6047248 Georgiou et al. Apr 2000 A
6048746 Burr Apr 2000 A
6052022 Lee Apr 2000 A
6078084 Nakamura et al. Jun 2000 A
6078319 Bril et al. Jun 2000 A
6087820 Houghton et al. Jul 2000 A
6087892 Burr Jul 2000 A
6091283 Murgula et al. Jul 2000 A
6100751 De et al. Aug 2000 A
6118306 Orton et al. Sep 2000 A
6119241 Michail et al. Sep 2000 A
6141762 Nicol et al. Oct 2000 A
6157092 Hofmann Dec 2000 A
6172943 Yuzuki Jan 2001 B1
6202104 Ober Mar 2001 B1
6215235 Osamura Apr 2001 B1
6216235 Thomas et al. Apr 2001 B1
6218708 Burr Apr 2001 B1
6226335 Prozorov May 2001 B1
6229379 Okamoto May 2001 B1
6229747 Cho et al. May 2001 B1
6232830 Fournel May 2001 B1
6242936 Ho et al. Jun 2001 B1
6272642 Pole, II et al. Aug 2001 B2
6279048 Fadavi-Ardekani et al. Aug 2001 B1
6281716 Mihara Aug 2001 B1
6303444 Burr Oct 2001 B1
6304824 Bausch et al. Oct 2001 B1
6305407 Selby Oct 2001 B1
6311287 Dischler et al. Oct 2001 B1
6314522 Chu et al. Nov 2001 B1
6320453 Manning Nov 2001 B1
6337593 Mizuno et al. Jan 2002 B1
6345362 Bertin et al. Feb 2002 B1
6345363 Levy-Kendler Feb 2002 B1
6347379 Dai et al. Feb 2002 B1
6370046 Nebrigic et al. Apr 2002 B1
6373323 Kuroda Apr 2002 B2
6373325 Kuriyama Apr 2002 B1
6378081 Hammond Apr 2002 B1
6388432 Uchida May 2002 B2
6407571 Furuya et al. Jun 2002 B1
6415388 Browning et al. Jul 2002 B1
6422746 Weiss et al. Jul 2002 B1
6424203 Bayadroun Jul 2002 B1
6424217 Kwong Jul 2002 B1
6425086 Clark et al. Jul 2002 B1
6426641 Koch et al. Jul 2002 B1
6427211 Watts, Jr. Jul 2002 B2
6442746 James et al. Aug 2002 B1
6447246 Abe et al. Sep 2002 B1
6457134 Lemke et al. Sep 2002 B1
6457135 Cooper Sep 2002 B1
6466077 Miyazaki et al. Oct 2002 B1
6469573 Kanda et al. Oct 2002 B2
6476632 La Rosa et al. Nov 2002 B1
6477654 Dean et al. Nov 2002 B1
6486729 Imamiya Nov 2002 B2
6487668 Thomas et al. Nov 2002 B2
6489224 Burr Dec 2002 B1
6489796 Tomishima Dec 2002 B2
6496027 Sher et al. Dec 2002 B1
6496057 Wada et al. Dec 2002 B2
6510400 Moriyama Jan 2003 B1
6510525 Nookala et al. Jan 2003 B1
6513124 Furuichi et al. Jan 2003 B1
6515903 Le et al. Feb 2003 B1
6518828 Seo et al. Feb 2003 B2
6519706 Ogoro Feb 2003 B1
6529421 Marr et al. Mar 2003 B1
6531912 Katou Mar 2003 B2
6563371 Buckley, III et al. May 2003 B2
6570371 Volk May 2003 B1
6574577 Stapleton et al. Jun 2003 B2
6574739 Kung et al. Jun 2003 B1
6600346 Macaluso Jul 2003 B1
6617656 Lee et al. Sep 2003 B2
6642774 Li Nov 2003 B1
6657504 Deal et al. Dec 2003 B1
6675360 Cantone et al. Jan 2004 B1
6677643 Iwamoto et al. Jan 2004 B2
6700434 Fujii et al. Mar 2004 B2
6731221 Dioshongh et al. May 2004 B1
6737909 Jaussi et al. May 2004 B2
6741118 Uchikoba et al. May 2004 B2
6774705 Miyazaki et al. Aug 2004 B2
6784722 Tang et al. Aug 2004 B2
6791146 Lai et al. Sep 2004 B2
6791212 Pulvirenti et al. Sep 2004 B2
6792379 Ando Sep 2004 B2
6803633 Mergens et al. Oct 2004 B2
6809968 Marr et al. Oct 2004 B2
6815971 Wang et al. Nov 2004 B2
6865116 Kim et al. Mar 2005 B2
6882172 Suzuki et al. Apr 2005 B1
6885210 Suzuki Apr 2005 B1
6889331 Soerensen et al. May 2005 B2
6906582 Kase et al. Jun 2005 B2
6917240 Trafton et al. Jul 2005 B2
6922783 Knee et al. Jul 2005 B2
6927620 Senda Aug 2005 B2
6936898 Pelham et al. Aug 2005 B2
6967522 Chandrakasan et al. Nov 2005 B2
6986068 Togawa Jan 2006 B2
6992508 Chow Jan 2006 B2
7012461 Chen et al. Mar 2006 B1
7030681 Yamazaki et al. Apr 2006 B2
7100061 Halepete et al. Aug 2006 B2
7112978 Koniaris et al. Sep 2006 B1
7119604 Chih Oct 2006 B2
7120804 Tschanz et al. Oct 2006 B2
7129745 Lewis et al. Oct 2006 B2
7180322 Koniaris et al. Feb 2007 B1
7228242 Read et al. Jun 2007 B2
7334198 Ditzel et al. Feb 2008 B2
7336090 Koniaris et al. Feb 2008 B1
7336092 Koniaris et al. Feb 2008 B1
7348827 Rahim et al. Mar 2008 B2
7362165 Chen Apr 2008 B1
7363176 Patel et al. Apr 2008 B2
7439730 Desplats et al. Oct 2008 B2
7562233 Sheng et al. Jul 2009 B1
7626409 Koniaris et al. Dec 2009 B1
7671621 Koniaris et al. Mar 2010 B2
8040149 Koniaris et al. Oct 2011 B2
20010028577 Sung et al. Oct 2001 A1
20020002689 Yeh Jan 2002 A1
20020011650 Nishizawa et al. Jan 2002 A1
20020026597 Dai et al. Feb 2002 A1
20020029352 Borkar et al. Mar 2002 A1
20020032829 Dalrymple Mar 2002 A1
20020067638 Kobayashi et al. Jun 2002 A1
20020073348 Tani Jun 2002 A1
20020083356 Dai Jun 2002 A1
20020087219 Dai Jul 2002 A1
20020087896 Cline et al. Jul 2002 A1
20020116650 Halepete et al. Aug 2002 A1
20020130701 Kleveland Sep 2002 A1
20020138778 Cole et al. Sep 2002 A1
20020140494 Thomas et al. Oct 2002 A1
20020178390 Lee Nov 2002 A1
20020194509 Plante et al. Dec 2002 A1
20030006590 Aoki et al. Jan 2003 A1
20030036876 Fuller, III et al. Feb 2003 A1
20030065960 Rusu et al. Apr 2003 A1
20030071657 Soerensen et al. Apr 2003 A1
20030074591 McClendon et al. Apr 2003 A1
20030098736 Uckikoba et al. May 2003 A1
20030189465 Abadeer et al. Oct 2003 A1
20040025061 Lawrence Feb 2004 A1
20040073821 Naveh et al. Apr 2004 A1
20040103330 Bonnett May 2004 A1
20040108881 Bokui et al. Jun 2004 A1
20040123170 Tschanz et al. Jun 2004 A1
20040128631 Ditzel et al. Jul 2004 A1
20040246044 Myono et al. Dec 2004 A1
20050225376 Kin Law Oct 2005 A1
20060074576 Patel et al. Apr 2006 A1
20070229054 Dobberpuhl et al. Oct 2007 A1
20070283176 Tobias et al. Dec 2007 A1
20070296440 Takamiya et al. Dec 2007 A1
20080143372 Koniaris et al. Jun 2008 A1
20100060306 Koniaris et al. Mar 2010 A1
20120001651 Koniaris et al. Jan 2012 A1
Foreign Referenced Citations (7)
Number Date Country
0381021 Aug 1990 EP
0474963 Mar 1992 EP
0501655 Sep 1992 EP
0978781 Feb 2000 EP
1398639 Mar 2004 EP
09-185589 Jul 1997 JP
0127728 Apr 2001 WO
Non-Patent Literature Citations (7)
Entry
Oner et al., “A compact Monitoring Circuit for Real-Time On-Chip Diagnosis of Hot-Carrier Induced Degradation” Microelectronic test structures. Proceedings, IEEE International Conference in Monterey, CA. Mar. 17, 1997-Mar. 20, 1997, pp. 72-76.
Computer Software, Wikipedia; “http://en.wikipedia.org/wiki/Software”; retrieved on May 2, 2007.
“High-Speed, Digitally Adjusted Stepdown Controllers for Notebook CPUS”, Maxim Manual, Jul. 2000, pp. 1-28.
Desai, et al.; “Sizing of Clock Distribution Networks for High Performance CPU Chips”; Digital Equipment Corporation, Hudson, MA, Jun. 1996, pp. 389-394.
Baker, K., et al,; “SHMOO Plotting: The Black Art of IC Testing”; IEEE Design & Test of Computers, IEEE vol. 14, No. 3; July 1, 1997, pp. 90-97, XP000793305 ISSN: 0740-7475 (the whole document).
“Wafer Burn-In Isolation Circuit”; IBM Technical Disclosure Bulletin; IBM Corp, New York, US, vol. 32, No. 6B, Nov. 1, 1989, pp. 442-443; XP00073858 ISSN: 0018-8689 (the Whole Document).
“LTC 1736 Product”, Linear Technology Manual, Jan. 1999, pp. 1-28.
Related Publications (1)
Number Date Country
20120319721 A1 Dec 2012 US
Continuations (4)
Number Date Country
Parent 12651244 Dec 2009 US
Child 13587827 US
Parent 12037784 Feb 2008 US
Child 12651244 US
Parent 11490356 Jul 2006 US
Child 12037784 US
Parent 10956207 Sep 2004 US
Child 11490356 US