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Not Applicable
The present invention relates to integrated circuits, and more particularly, to an integrated bandgap reference circuit operative to generate an output voltage that is adapted not to vary with temperature.
Bandgap reference voltage generators (alternatively referred to as bandgap reference circuits) are used in a wide variety of electronic circuits, such as wireless communications devices, memory devices, voltage regulators, etc. A bandgap reference circuit often supplies an output voltage that is relatively immune to changes in input voltage or temperature.
A bandgap reference circuit is typically adapted to use the temperature coefficients associated with physical properties of the semiconductor devices disposed therein to generate a nearly temperature-independent reference voltage. A bandgap reference circuit operates on the principle of compensating the negative temperature coefficient of VBE—which is the base-emitter voltage of a bipolar transistor—with the positive temperature coefficient of the thermal voltage VT. In its most basic form, the VBE voltage is added to a scaled VT voltage using a temperature-independent scale factor K to supply the reference voltage Vref, as shown below:
Vref=VBE+K*VT (1)
Because voltage signals VBE and VT exhibit opposite-polarity temperature drifts, parameter K may be selected such that voltage Vref is nearly independent. As is known to those skilled in the art, thermal voltage VT is equal to kT/q, where, where k is Boltzmann's constant, T is the absolute temperature in degrees Kelvin, and q is the electron charge.
In addition to being temperature independent, a bandgap reference circuit is ideally also adapted to supply a substantially stable and unchanging output reference voltage despite variations in the input voltage levels received by or the capacitive loading applied to the bandgap circuit. Accordingly, an ideal bandgap reference circuit output is also immune to ripples or noise that is typically present in the power source supplying voltage to the bandgap reference circuit. However, most bandgap reference circuits exhibit non-ideal characteristics. One measure of the ability of a bandgap reference circuit to suppress or reject such supply ripple or noise voltages is referred to as the power supply ripple rejection (PSRR).
The growth in demand for battery-operated portable electronic devices, such as wireless communications devices and personal digital assistance devices, has brought to the fore need to develop low voltage, low power systems. For instance, many portable wireless systems are being designed to operate using batteries that supply, for example, 1.3 volts. Designing a bandgap reference circuit adapted to operate at such low voltages poses a challenging task.
In a publication entitled “A Sub-1-V ppm/° C. CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device”, IEEE Journal of Solid State Circuits, Vol. 37, No. 4, April 2002, pp. 526-530, authors Leung et al. propose a sub-1V bandgap reference voltage formed using a standard CMOS process and that dispenses with the need for low threshold voltage devices (such as those shown in
The sub-1V bandgap reference circuit 10 includes a single loop and a single operational amplifier 12 that receives input voltages from node N1 and N2. Current I is generated by the closed-loop circuitry formed by operational amplifier 12, transistors Q1, Q2, and resistors R1, R2A1, R2B1, R2A2 and R2B2. Current I has the following magnitude:
I=VEB/R2+VT*ln N/R1 (2)
where N is the ratio of the emitter areas of transistors Q1 and Q2, VT is the thermal voltage and where:
R2=R2A1+R2A2=R2B1+R2B2 (3)
Transistors M1, M2 and M2 form a current mirror. Therefore current I flowing through resistor R3 is equal to the current that also flows through transistor M1 or M2. The reference voltage Vref generated by the bandgap reference circuit 10 is as follows:
Vref=(R3/R2)*[VEB2+(R2R*ln N/R1)*VT (4)
Parameter N is selected such that voltage Vref is nearly temperature-independent. As is seen from the above, bandgap reference circuit 10 includes single closed-loop circuitry that causes the same current I to flow through output transistor M3. Therefore, if another output stage (not shown—but similar to that formed by transistor M3 and resistor R3) is disposed between supply voltage Vdd and the ground terminal, it will generate an output voltage with the same nearly zero temperature coefficient as that of Vref.
There may be instances where at least two reference voltages each with a different temperature coefficient may be required. For example, to compensate for a positive temperature drift of a voltage-controlled oscillator, it may be desired to generate an output reference voltage that has a negative, non-zero temperature coefficient. Two different bandgap reference circuits 10 (i.e., with different physical parameters) would be required to generate two reference voltage that have different temperature coefficients., thereby increasing cost.
There continues to be a need for a bandgap reference circuit that is scalable and is thus adapted to generate multiple output reference voltages with each output reference voltage having a different temperature coefficient.
A bandgap reference voltage generator, in accordance with the present invention, includes a first closed-loop circuit having a voltage-gain stage and adapted to generate a first current with a positive temperature coefficient, and a second closed-loop circuit also having a voltage-gain stage and adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator further includes an output stage adapted to sum any multiple of the first current to any multiple of the second current and to pass this current through an output resistor to generate an output voltage across the output resistor. The multiples are so selected as to cause the voltage across the output resistor to have a nearly zero temperature coefficient.
In some embodiments of the present invention, each of the first and second voltage-gain stages is an operational amplifier. In these embodiments, the positive and negative input terminals of the first operational amplifier are respectively coupled to nodes that receive the first current and mirrored replica of the first current. Similarly, the positive and negative input terminals of the second operational amplifier are respectively coupled to nodes that receive the second current and mirrored replica of the second current. Each of the first and second operational amplifiers provides an inverting voltage gain (i.e., as the voltage at the positive input terminal increases, the output voltage decreases and vice versa).
The first closed-loop circuit further includes, in part, a first bipolar transistor and a second bipolar transistor whose emitter are is N times the emitter area of the first bipolar transistor. The collector and base terminals of both the first and second bipolar transistors are coupled to the ground terminal. The positive input terminal of the first operational amplifier is coupled to the emitter terminal of the first bipolar transistor. The negative input terminal of the first operational amplifier is coupled to a first terminal of a resistor whose second terminal is coupled to the emitter terminal of the second bipolar transistor. Because the currents flowing through both the first and second bipolar transistors have the same magnitude and because the emitter area of the second bipolar transistor is N times the emitter area of the first bipolar transistor, and further because the voltage across the positive and negative input terminals of the first operational amplifier is nearly zero, the first current has a positive temperature coefficient.
The second closed-loop circuit further includes, in part, a bipolar transistor and a resistor. The collector and base terminals of this bipolar transistors are coupled to the ground terminal. The positive input terminal of the second operational amplifier is coupled to the emitter terminal of this bipolar transistor. The negative input terminal of the first operational amplifier is coupled to a first terminal of a resistor whose second terminal is coupled to the ground terminal. Because the currents flowing through both the first and second bipolar transistors have the same magnitude, and further because the voltage across the positive and negative input terminals of the first operational amplifier is nearly zero, the second current has a negative temperature coefficient.
The bandgap reference voltage generator is adapted to include any number of output stages. Each output stage may be further scaled to generate different multiples of the first and second currents thus to generate a reference voltage with a temperature coefficient different from those of the other stages. For example, via selection of multiples of the first and second currents flowing through a second output stage, the second output stage may be scaled to generate a reference output voltage with a positive temperature coefficient. Similarly, via selection of the multiples of the first and second currents flowing through a third output stage, the third output stage may be scaled to generate a reference output voltage with a negative temperature coefficient.
A bandgap reference voltage generator, in accordance with the present invention, includes, in part, first closed-loop circuitry adapted to generate a first current with a positive temperature coefficient, and second closed-loop circuitry adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator is further adapted to includes a multitude of output stage. Each output stage is further adapted to sum any selected multiple of the first current to any selected multiple of the second current to generate an output voltage that has either a nearly zero, or a positive or a negative temperature coefficient. For example, the first output stage may be adapted to generate a reference output voltage that has a nearly zero temperature coefficient. Similarly, the second output stage may be adapted to generate a reference output voltage that has a negative temperature coefficient.
The output voltage generated by operational amplifier 102 is applied to the gate terminals of PMOS transistors 106, 108, 114 and 118. Similarly, the output voltage generated by operational amplifier 104 is applied to the gate terminals of PMOS transistors 110, 112, 116 and 120. The drain terminals of PMOS transistors 106 and 108 are respectively applied to positive input terminals A and negative input terminal B of operational amplifier 102. Similarly, the drain terminals of PMOS transistors 110 and 112 are respectively applied to positive input terminal C and negative input terminal D of operational amplifier 104. Each of operational amplifiers 102, 104 provides an inverting voltage gain and is well known in the art.
Input terminal A of operational amplifier 102 is coupled to the emitter terminal of bipolar transistor 130 and the drain terminal of PMOS transistor 106. The base and collector terminals of PNP transistor 130 receive the supply voltage Vss (i.e., are coupled to the ground terminal). Input terminal B of operational amplifier 102 is coupled to a first terminal of resistor 122 and the drain terminal of PMOS transistor 108. A second terminal of resistor 122 is coupled to the emitter terminal of bipolar transistor 132. The base and collector terminals of bipolar transistor 132 receive supply voltage Vss.
Input terminal C of operational amplifier 104 is coupled to the emitter terminal of bipolar transistor 134 and the drain terminal of PMOS transistor 110. The base and collector terminals of PNP transistor 134 receive supply voltage Vss. Input terminal D of operational amplifier 104 is coupled to a first terminal of resistor 124 and the drain terminal of PMOS transistor 112. A second terminal of resistor 124 receives supply voltage Vss.
The drain terminals of PMOS transistors 114, 116 are coupled to a first terminal of resistor 126 at node E. A second terminal of resistor 126 receives supply voltage Vss. Similarly, the drain terminals of PMOS transistors 118, 120 are coupled to a first terminal of resistor 128 at node F. A second terminal of resistor 128 receives supply voltage Vss. The source terminal of each of PMOS transistors 106, 108, 110,112, 114, 116,118, 120 is coupled to supply voltage Vdd.
Operational amplifier 102 in combination with PMOS transistors 106, 108, resistor 122 and bipolar PNP transistors (hereinafter PNP transistors) 130, 132 form closed-loop 150. Operational amplifier 102 disposed in closed-loop 150 is a voltage gain stage and thus provides a voltage gain in closed-loop 150. Similarly, operational amplifier 104 in combination with PMOS transistors 110, 112, resistor 124 and PNP transistor 134 form closed-loop 160. Operational amplifier 104 disposed in closed-loop 150 is a voltage gain stage and thus provides a voltage gain in closed-loop 160.
Because the gate-to-source voltage of PMOS transistors 106 and 108 is the same, the same current I1 flows through both PMOS transistors 106 and 108. As is known to those skilled in the art, the voltages at input terminals A and B of Operational amplifier (hereinafter alternatively referred to as op amp) 102 are substantially the same. Therefore, because the voltage at node A is one VBE above the ground potential, the voltage at node A is also one VBE above the ground potential. PNP transistor 132 is so adapted as to have an emitter area that is N times the emitter are of PNP transistor 130. Accordingly, because the emitter area of PNP transistor 132 is N times the emitter area of transistor 130 and because the same current flows through PNP transistors 130 and 132, and further, because nodes A and B have substantially the same voltage, current I1 that flows through each of PMOS transistors 106 and 108 is defined by the following equation:
I1=VT*ln N/R122 (5)
where R122 is the resistance of resistor 122.
Therefore, as seen from equation (5), current I1 has a positive temperature coefficient. Because the gate-to-source voltage of PMOS transistors 110 and 112 is the same, the same current I2 flows through both PMOS transistors 110, 112. The voltages at input terminals A and B of operational amplifier 104 are substantially the same. Therefore, because the voltage at node C is one VBE above the ground potential, the voltage at node D is also one VBE above the ground potential. Because the base-emitter voltage, i.e., the VBE, of a bipolar transistor has a negative temperature coefficient, current I2 that flows through each of PMOS transistors 110 and 112 also has a negative temperature coefficient and is defined by the following equation:
I2=VBE/R124 (6)
where R124 is the resistance of resistor 124.
As seen from the above, bandgap reference circuit 100, in accordance with the present invention, generates two independent currents: current I1 that has a positive temperature coefficient and current I2 that has a negative temperature coefficient. As described further below, currents I1 and I2 may be independently scaled and then combined at various output stages of bandgap reference circuit 100 to provide reference voltages with different temperature coefficient.
The exemplary embodiment of bandgap reference circuit 100 is shown as having two output stages. PMOS transistors 114, 116, together with resistor 126 form output stage 170. PMOS transistors 118, 120, together with resistor 128 form output stage 180. It is understood, however, that other embodiments of the bandgap reference circuit, in accordance with the present invention, may have more output stages. Furthermore, exemplary embodiment of bandgap reference circuit 100 is shown as having two closed loops 150 and 160 adapted to generate two independent currents. It is understood, however, that other embodiments of the bandgap reference circuit, in accordance with the present invention, may have more than two closed loops and thus may be adapted to generate more than two independent currents.
PMOS transistor 114 is adapted to have a channel-width to channel length (i.e., W/L) ratio that is K1 times larger than that of PMOS transistor 106. Accordingly, current I3 flowing through PMOS transistor 114 is K1 times greater than current I1. Similarly, PMOS transistor 116 is adapted to have a W/L ratio that is K2 times larger than that of PMOS transistor 110. Accordingly, current I4 flowing through PMOS transistor 116 is K2 times greater than current I2. Current Iref1 flowing through resistor 126 of output stage 170 is the sum of currents I3 and I4 and is defined by the following equation:
Iref1=K1*(VT ln(N)/R122)+K2*(VBE/R124) (7)
Therefore, voltage Vref1 developed across resistor 126 (i.e., between nodes E and the Vss) and that is a first voltage reference generated by bandgap reference circuit 100 is defined by the following equation:
Vref1=(KT*(VT*ln(N)/R122)+K2*(VBE/R124))*R126 (8)
where R126 is the resistance of resistor 126.
As is known to those skilled in the art, resistors 122, 124 and 126 have similar temperature coefficients. Therefore, any drift in the voltage reference Vref1 caused by variations in the resistances of resistors 122, 124 due to the temperature is offset by corresponding variations in the resistance of resistors 126. The temperature coefficients of base-to-emitter voltage VBE and thermal voltage VT are also known. For example, voltage VBE typically has a temperature coefficient of −2 mv/C° and voltage VT is equal to KT/q . Therefore, equation (9) enables parameters K1 and K2 to be selected such that the temperature coefficient of reference voltage Vref1 is nearly zero.
As described further above, there may be instances where a voltage reference generated by a bandgap reference circuit is desired to have a non-zero temperature coefficient. For example, to compensate for, e.g., a negative temperature coefficient of a voltage-controlled oscillator, it may be desired to supply a reference voltage having a positive temperature coefficient. In accordance with the present invention, bandgap reference circuit 100 is adapted to generate different reference output voltages each with a different temperature coefficient. For example, as described below, bandgap reference circuit 100 is adapted to generate output reference voltage Vref2 that has a positive temperature coefficient.
PMOS transistor 118 is adapted to have a W/L ratio that is K3 times larger than that of PMOS transistor 106. Accordingly, current I5 flowing through PMOS transistor 118 is K3 times greater than current I1. Similarly, PMOS transistor 120 is adapted to have a W/L ratio that is K4 times larger than that of PMOS transistor 110. Accordingly, current I6 flowing through PMOS transistor 116 is K4 times greater than current I2 flowing through transistor 110. Current Iref2 flowing through resistor 128 of output stage 180 is the sum of currents I5 and I6 and is defined by the following equation:
Iref2=K3*(VT*ln(N)/R122)+K4*(VBE/R124) (9)
Therefore, voltage Vref2 developed across resistors 128 (i.e., between nodes F and the Vss) ands that is a second voltage reference generated by bandgap reference circuit 100 is defined by the following equation:
Vref2=(K3*(VT*ln(N)/R122)+K4*(VBE/R124))*R128 (10)
where R128 is the resistance of resistor 128.
In accordance with equation (10) parameters K3 and K4 may be selected so that the temperature coefficient of reference voltage Vref2 has a certain non-zero positive value, independent of the temperature coefficient of voltage Vref1. By coupling another output stage (not shown but similar to output stages 170 and 180) to bandgap reference circuit 100 of
Therefore, bandgap reference circuit 100, in accordance with the present invention, enables the temperature coefficients of each of its reference output voltages to be selectively varied through selection of the ratios of the W/L of PMOS transistors of its associated output stage. Moreover, the temperature coefficient of each one of the reference voltages generated by bandgap reference circuit 100 may be selected independently of the temperature coefficient of the other reference voltages generated by bandgap reference circuit 100.
The above embodiment of the present invention re illustrative and not limitative. The invention is not limited by the type of the operational amplifier, transistor, resistor, etc. disposed in the bandgap reference circuit. The invention is not limited by number of closed-loop circuits that generate currents with either positive or negative temperature coefficients. Nor is the invention limited by the number of output stages each of which may generate an output voltage having a temperature coefficient different from those of the others. Other additions, subtractions or modification are obvious in view of the present invention and are intended to fall within the scope of the appended claims.
Number | Name | Date | Kind |
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5666046 | Mietus | Sep 1997 | A |
6489835 | Yu et al. | Dec 2002 | B1 |
6563371 | Buckley et al. | May 2003 | B1 |
20020014914 | Perque et al. | Feb 2002 | A1 |
Number | Date | Country | |
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20040155700 A1 | Aug 2004 | US |