The present invention relates to a rectifier circuit, and more particularly, to a CMOS full-wave rectifier circuit.
Generally, rectifiers are used for the conversion of AC to DC voltage. A conventional full-wave rectifier that includes a diode bridge 105 is shown in
u2(t)=|u1(t)|−2uD, if |u1(t)|≧2uD, and (1a)
u2(t)=0, if |u1(t)|<2uD, (1b)
where uD denotes the voltage drop across one diode. As a general disadvantage, the voltage drop across load 107 is not the full magnitude of the input voltage difference |u1(t)|, but diminished by 2uD, i.e., by two diode voltage drops (typically, 1.4V). For low power applications, the diode voltages may significantly contribute to the overall power consumption of the circuit.
The diode bridge shown in
A rectifier and method for rectification includes a bridge that is advantageously implemented using switches as opposed to diodes. The switches may be, without limitation, MOS transistors. Such a rectifier may be used, for example, in a wide variety of applications, such as medical or automotive applications.
In accordance with an embodiment of the invention there is provided a rectifier circuit which includes first and second input terminals for receiving a rectangular wave input voltage, and first and second output terminals for providing a rectified dc output voltage. A first switch is coupled between the first input terminal and a first node, the first node being coupled to the first output terminal. A second switch is coupled between the second input terminal and the first node. A third switch is coupled between the first input terminal and a second node, the second node being coupled to the second output terminal. A fourth switch is coupled between the second input terminal and to the second node. The first switch and fourth switch are gated on when the input voltage is of a first polarity; and the second switch and the third switch are gated on when the input voltage is of a second polarity opposite the first polarity so as to provide an output voltage having a magnitude substantially equal to the magnitude of the input voltage.
In accordance with related embodiments of the invention, the first switch, the second switch, the third switch, and the fourth switch may be MOS transistors. For example, the first switch and the second switch may be PMOS transistors, and the third switch and fourth switch may be NMOS transistors. The first switch and the fourth switch may be gated by one of the first input terminal and the second input terminal, and the second switch and the third switch may be gated by the other of the one of the first input terminal and the second input terminal. A parallel load combination of a resistance and a capacitance may be coupled to the rectifier circuit between the first and second output terminals. Or a resistive load may be coupled to the rectifier circuit between the first and second output terminals without a discrete parallel capacitor. Both the load and the rectifier circuit may be integrated on a single chip. The circuit may be used to ensure a desired supply voltage polarity.
In accordance with another embodiment of the invention, a polarity protection circuit includes the rectifier circuit of the above-described embodiments. In another embodiment, an implanted medical device, such as a retinal implant or a cochlear implant, includes the rectifier circuit of the above-described embodiments. In accordance with still another embodiment of the invention, a chip includes both the rectifier circuit of the above-described embodiments and a parallel load combination of a resistance and a capacitance coupled between the first and second output terminals. Or the load may be a resistive load without a discrete parallel capacitor. The load may include a signal processor.
In accordance with yet another embodiment of the invention, a method of rectifying is presented. The method includes applying a rectangular input signal between a first input terminal and a second input terminal. A first switch is coupled between the first input terminal and a first node, and a second switch is coupled between the second input terminal and the first node. The first node is coupled to a first output terminal. A third switch is coupled between the first input terminal and a second node, and a fourth switch is coupled between the second input terminal and the second node. The second node is coupled to a second output terminal. The first switch and fourth switch are gated on when the input signal is of a first polarity; while the second switch and the third switch are gated on when the input signal is of a second polarity opposite the first polarity so that the first and second output terminals provide a rectified dc voltage having a magnitude substantially equal to the magnitude of the input voltage.
In accordance with related embodiments of the invention, the first switch, the second switch, the third switch, and the fourth switch may be MOS transistors. The first switch and the second switch may be PMOS transistors, and the third switch and fourth switch may be NMOS transistors. The first switch and the fourth switch may be gated by one of the first input terminal and the second input terminal, and the second switch and the third switch may be gated by the other of the one of the first input terminal and the second input terminal. The method may further comprise coupling a parallel load combination of a resistance and a capacitance between the first and second output terminals. Or the method may further comprise coupling a resistive load between the first and second output terminals without a discrete parallel capacitor. In a further embodiment, the input signal may be disconnected from the input terminals for a period of time after the switches are gated on.
In illustrative embodiments, a rectifier includes a bridge that is implemented using switches. The switches may be, for example, MOS transistors. Details of illustrative embodiments are discussed below.
As shown in
The gates of the transistors may be directly connected to the input voltage rails. Assuming a purely resistive load 207, and an ideal switching performance of the transistors, the following conditions are fulfilled:
u2(t)=|u1(t)|, if |u1(t)|≧uTHR, and (2a)
u2(t)=0, if |u1(t)|<uTHR, (2b)
whereby voltage uTHR denotes a MOS-threshold voltage, which here is assumed to be equal for both, PMOS and NMOS transistors. For u1(t)≧uTHR, transistors 201 and 202 are switched on (low impedance), whereas transistor 203 and 204 are switched off (high impedance), and vice versa for u1 (t)≦−uTHR, transistors 203 and 204 are switched on, and transistors 201 and 202 are switched off. Thus, for the special case of an ohmic load, the CMOS-bridge of
For the implementation of bridge
Assuming a sinusoidal input voltage, the CMOS-bridge 205 in
While
Moreover, for the circuit shown in
The CMOS-bridge in the above-described embodiments may advantageously be used in a wide variety of applications. For example, the CMOS-bridge may be used to provide rectification and/or to ensure a desired supply voltage polarity, in diverse fields such as, without limitation, the automotive or medical fields. For example, a chip containing such a CMOS bridge may be part of an implantable medical device such as a retinal implant system or a cochlear implant system. Embodiments may also include using such a circuit as the basis for a polarity protection circuit which allows for arbitrary connecting of the inputs to a dc source, independently of the polarity.
Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the true scope of the invention.
This application claims priority from U.S. Provisional Patent Application 60/697,624, filed Jul. 8, 2005, the contents of which are incorporated herein by reference.
Number | Date | Country | |
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60697624 | Jul 2005 | US |