This application is based upon and claiming the benefit of priority from the prior Japanese Patent Application No. 2004-194271, filed in Jun. 30, 2004, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to a CMOS image sensor. More specifically, it relates to a voltage control circuit generating a control voltage of a switch element for controlling the supply of a reset voltage to the photoelectric conversion element of each pixel circuit included in the CMOS image sensor and a voltage switch circuit used in this voltage control circuit.
2. Description of the Related Art
The CMOS (Complementary metal-oxide semiconductor) image sensor comprises a pixel part in which pixel circuits for taking an image for one pixel are arranged in a matrix form and outputs image signals for one page by sequentially selecting outputs of the respective pixel circuits using vertical and horizontal scanning shift registers. In each pixel circuit, after a photoelectric conversion element such as a photo diode, etc. is shortened at a predetermined reset voltage each time an image is taken, a charging voltage of the photoelectric conversion element drops in accordance with an exposure amount by opening the short-circuit to a reset voltage. Therefore, an image can be taken by obtaining the drop amount of the charging voltage of each pixel. At this time, as publicly known, a CMOS switch element for controlling the short of a reset voltage for a photoelectric conversion element is either ON or is set to a conduction state. Then, kTC noise which is obtained using an equation (kT/C) is generated at a timing when a node of the photoelectric conversion element is opened from the short condition to a predetermined reset voltage. Here, k is a Boltzman constant, T is an absolute temperature and C is the full capacity of photoelectric conversion elements. The applicant discloses a CMOS image sensor capable of reducing kTC noise, considering the above-mentioned point (Japanese laid-open patent publication 2003-234959, which is called patent literature 1 hereafter.). In this CMOS image sensor, in a pixel circuit, an ON resistance when the CMOS switch element is ON or a conduction resistance is appropriately increased by controlling a gate potential of the CMOS switch element during a reset period of the photoelectric conversion. Thus, the cutoff frequency of a low-pass filter which consists of the ON resistance of a CMOS switch element and the parasitic capacitance generated at a cathode of the photoelectric conversion element is lowered. Therefore, the kTC noise component equal to or higher than the cutoff frequency can be reduced.
However, an ON resistance of the CMOS switch element is a finite value while this element is being shorted up to a reset level. Therefore, a voltage at the time of resetting a photoelectric conversion element such as a photo diode, etc., is slightly deviated from the assigned predetermined reset voltage. The reset noise generated by the deviation in the elements is added to the kTC noise. Therefore, picture quality can be improved by reducing the reset noise generated by the deviation from such a reset voltage and the kTC noise.
The present invention aims at offering a CMOS image sensor for reducing kTC noise and reset noise generated by the deviation from a reset voltage.
Furthermore, the present invention aims at offering a voltage control circuit for assigning a control voltage to reduce kTC noise and reset noise generated by the deviation from a reset voltage for a CMOS switch element for controlling the supply of a reset voltage to the photoelectric conversion element of a pixel circuit in a CMOS image sensor and a voltage switch circuit for realizing this voltage control circuit.
In one aspect, the present invention offers a CMOS image sensor in which each pixel circuit of an active pixel sensor array includes a photoelectric conversion element for converting input light into electricity and a switch transistor for controlling the supply of a reset voltage for resetting the photoelectric conversion element to a predetermined voltage, to the photoelectric conversion element. The CMOS image sensor comprises a control circuit for assigning a control signal applied to a control electrode of the switch transistor. In the first part of a reset period of the photoelectric conversion element, the control circuit outputs a first voltage so as to make an ON resistance of the switch transistor sufficiently smaller than an electric source voltage of the CMOS image sensor.
In another aspect, the present invention offers a control circuit for assigning a control signal applied to the control electrode of a switch transistor in a CMOS image sensor in which each pixel circuit of an active pixel sensor array includes a photoelectric conversion element for converting input light into electricity and a reset transistor for controlling the supply of a reset voltage for resetting the photoelectric conversion element to a predetermined voltage, to the photoelectric conversion element. This control circuit comprises a first conductor for receiving a first voltage much higher than an electric source voltage of the CMOS image sensor and a low voltage generation circuit for generating a second voltage lower than an electric source of the CMOS image sensor. Furthermore, this control circuit comprises a switch circuit for outputting a first voltage to make an ON resistance sufficiently small in the first part of a reset period of the photoelectric conversion element and for outputting a second voltage in the latter part of a reset period of the photoelectric conversion element.
In another aspect, the present invention offers a voltage switch circuit that is inserted between a first conductor for receiving a relatively high voltage and a second conductor for receiving a relatively low second voltage and that outputs either the first voltage or the second voltage. This voltage switch circuit comprises a unit for preventing a drop in voltage of the first voltage from occurring in the second conductor in the case where the first voltage is switched to the second voltage.
According to the present invention, in the first part of a reset period, a photoelectric conversion element is securely reset by sufficiently reducing the ON resistance of a reset transistor or a switch transistor for controlling the supply of a reset voltage of the photoelectric conversion element so that the photoelectric conversion element is securely reset. Consequently, reset noise generated by the deviation from a reset voltage can be reduced. In the latter part of a reset period, by increasing an ON resistance of the CMOS switch element, the cutoff frequency of a low-pass filter that is generated by an ON resistance of both the CMOS image sensor and the parasitic capacitance generated at a cathode of the photoelectric conversion element is lowered. Therefore, the kTC noise component corresponding to a frequency which is equal to or higher than the cutoff frequency can be reduced.
The following is the detailed explanation of the present invention in reference to the preferred embodiments and attached drawings. In these drawings, like reference numerals refer to the like elements.
Before the explanation of a CMOS image sensor of the present invention, the CMOS image sensor described in the patent literature 1 is explained at first.
In
As shown in
Furthermore, the CMOS image sensor comprises a vertical scan shift register/voltage control circuit 20 for implementing the designation of the pixel circuit 11 in a vertical direction or the voltage control of a reset signal, an amplifier/noise cancel circuit 30 for implementing the amplification and noise-reduction of image signals outputted from the pixel circuit 11 in each row and a horizontal scan shift register 40 for designating outputs from the pixel circuit 11 in a horizontal direction using a row selection transistor M41. In addition, an amplifier 41a is connected to an output bus L41 for receiving an output signal from each row selection transistor M41. In
At first, the basic operation of the pixel circuit 11 is explained. Firstly, a reset signal RST is supplied from the voltage control circuit 21 via a reset signal line L11. When the switch transistor M11 becomes ON at a predetermined timing, the photoelectric conversion element D11 is charged at a reset potential VR as an initial voltage. Then, when the reset signal RTS is made OFF, an electric charge is accumulated in the photoelectric conversion element D11 in accordance with the externally inputted incident radiation. Accordingly, the potential on a cathode side of the photoelectric conversion element D11 drops. At that time, the transistor for amplification M12 functions as a source follower amplifier. That is, this transistor amplifies an electric current to increase a drive capability at the subsequent stage and at the same time, it outputs a voltage lower than the potential on a cathode side of the photoelectric conversion element D11 by about the threshold value of the MOS-FET.
In this way, when the accumulation of a signal electric charge starts and the column selection signal SLCT is inputted into a gate electrode of the column selection transistor M13 from a column selection signal line L12 after a predetermined time elapses, an output voltage of the transistor for amplification M12 is outputted to a row selection signal line L14 as an image signal. Then, the reset signal RTS turns the switch transistor M11 ON and the signal electric charge accumulated on the photoelectric conversion element D11 is reset.
In the thus-configured pixel circuit 11, kTC noise is generated by inputting the reset signal RST and a signal voltage depending on the accumulated electric charge in the photoelectric conversion element D11 is overlapped with a component of the above-mentioned kTC noise.
As shown in
However, since an ON resistance of the switch transistor M11 is a finite value, a voltage obtained at the time of resetting the photoelectric conversion element D11 is slightly deviated from a predetermined reset voltage VR so that reset noise generated by the variation in elements is added. Therefore, it is preferable that a resistance obtained when the transistor M11 is ON (Ron in
As a method of decreasing the ON resistance Ron of the transistor M11, there is a method of changing the characteristic of the transistor M11 itself so as to decrease the ON resistance Ron without changing circuit conditions. However, the change of the characteristic causes the increase of the mounting area of the transistor M11. Accordingly, the pixel size increases and it makes difficult to get higher resolution.
As another method of decreasing an ON resistance Ron of the transistor M11, there is a method of increasing a gate voltage of the switch transistor M11 without changing the characteristic of the transistor M11. For example,
The present invention is invented to solve this problem.
A voltage control circuit 21b of
In this way, in the CMOS image sensor 2 of the present invention, the transistor M2 is ON after the high voltage HV (7V in this example) completely drops so that the voltage of the connection node of the transistors M1 and M2 is not applied to the low voltage generation circuit 200 during a drop period of the high-voltage HV. Therefore, the output HV of the high voltage generation circuit 22 can be set sufficiently high so as to sufficiently decrease an ON resistance Ron of the switch transistor M1. Thus, according to the present invention, in the first part of a reset period, reset noise can be reduced by sufficiently decreasing an ON resistance of the switch transistor M11 for controlling the supply of a reset voltage of the photoelectric conversion element D11 and by securely resetting the photoelectric conversion element D11.
In addition, in the latter part of a reset period between T2 and T3, a kTC noise component in respect of a frequency higher than the set cutoff frequency can be reduced by increasing an ON resistance Ron of the CMOS switch M11 and by lowering the set cutoff frequency of a low-pass filter generated by both the ON resistance Ron of the CMOS switch element M11 and parasitic capacitance generated at a cathode of the photoelectric conversion element D11.
The voltage switch circuit 100 is not limited to the above-mentioned use example and it can be used for a variety in uses as a circuit for outputting a voltage of either a high voltage generation circuit or a low voltage generation circuit.
The above-mentioned explanation only referrers to preferred embodiments in order to explain the present invention. Therefore, a person skilled in the art can easily make various changes or modifications according to the technical concepts or principles of the present invention.
For example, a pixel circuit is not limited to
In the above-mentioned example, 7V is used as a high voltage HV for a reset voltage. The high voltage is not limited to 7V and an appropriate high voltage can be used. Similarly, the output LV of the low voltage generation circuit is set to 1.8V and 0V in the preferred embodiment but an appropriate voltage can be used other than these voltages.
In the above-mentioned preferred embodiment, the voltage control circuit 21b is provided with a series circuit of transistors M3 and M4 as a circuit for grounding the connection node of the transistors M1 and M2 but operations can be implemented without this series circuit. Without this ground series circuit (M3+M4), the aim of the present invention can be sufficiently achieved by turning the control voltage G2 of the switch transistor M2 of the low voltage generation circuit 200 to logic 1 at the timing T2′ when the high voltage HV completely drops as shown in
Furthermore, instead of M4, another low voltage generation circuit can be used.
Meanwhile, the order of M3 and M4 can be reversed.
Number | Date | Country | Kind |
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2004-194271 | Jun 2004 | JP | national |