Patent Application
20200099878
This disclosure relates generally to semiconductor image sensors, and in particular but not exclusively, relates to CMOS image sensors with multiple stage transfer gates.
Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as medical, automobile and other applications. The typical global shutter complementary metal oxide semiconductor (CMOS) image sensor is operated as follows: image charges accumulated in a photodiode from incident photons are transferred from the photodiode to a storage node, and then, subsequently to a floating diffusion node for global shutter read Out. The amount of generated image charges is proportional to the intensity of the image light. The generated image charges may be used to produce an image representing the external scene.
In order to accomplish the electric charge transfer from one node to another node, the nodes are frequently designed such that during operation, the node to which the charge is to be transferred (i.e., the destination node such as a floating diffusion node) has a greater electric potential than the node from which the electric charge is to be transferred (i.e., the source node such as photodiode node). In order to fully transfer electric charge from one node to another, the destination node may need to have an electric potential that is greater than the electric potential of the source node by an amount equal to or exceeding the amount of charge to be transferred. In other words, the destination node may need to have sufficient full well capacity to hold the electric charge from the source node without sharing the electric charge back with the source node when the barrier between the nodes is removed.
In order to achieve full electric charge transfer between a plurality of nodes, several solutions are used in the image sensor industry. The first solution is to increase the electric potential for successive nodes, with the increase in electric potential between each successive node generally equaling or exceeding the full well capacity for the pixel. However, this solution typically requires higher power supply voltages to be provided to the image sensor. The higher power supply voltage may result in higher power consumption, may require specialized processes to manufacture, and/or may require mitigation of electrostatic discharge issues. The second solution is to reduce the conversion gain between nodes. However, this solution may result in more noise and less sensitivity in operation of the image sensor. The third solution is to include additional nodes in image sensor pixels—for example, an image sensor formed by having two or more silicon chips stacked together. However, this solution may require additional contacts and storage nodes for charge to be transferred between the stacked silicon chips. The additional nodes exacerbate the need to increase the electric potential of subsequent storage nodes.
Non-limiting and non-exhaustive examples of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.
Examples of an apparatus and method for an image sensor with multiple stage transfer gates are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, one skilled in the relevant art will recognize that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in details in order to avoid obscuring certain aspects.
Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.
Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meanings.
In one example, after the image sensor photodiode/pixel in pixel array 104 has acquired its image data or image charge, the image data is readout by readout circuitry 101 and then transferred to functional logic 102. In various examples, readout circuitry 101 may include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or otherwise. Function logic 102 may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 101 may read out a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously.
In one example, control circuitry 103 is coupled to pixel array 104 to control operation of the plurality of photodiodes in pixel array 104. For example, control circuitry 103 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 104 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows. In another example, image acquisition is synchronized with lighting effects such as a flash.
In one example, imaging system 100 may be included in a digital camera, cell phone, laptop computer, automobile or the like. Additionally, imaging system 100 may be coupled to other pieces of hardware such as a processor (general purpose or otherwise), memory elements, output (USB port, wireless transmitter, HDMI port, etc.), lighting/flash, electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and/or display. Other pieces of hardware may deliver instructions to imaging system 100, extract image data from imaging system 100, or manipulate image data supplied by imaging system 100.
It should be noted that the term “photodiode” as used herein, is meant to encompass substantially any type of photon or light detecting component, such as a hole-based photodiode, a photo-gate or other photo-sensitive region. It should also be noted that different types of semiconductor substrates with different types of doping may also be used in different embodiments, and the two charge storage nodes 301 and 305 may be either n-doped regions in a p-type substrate or a p-well of a semiconductor substrate.
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Meanwhile, the second transfer electric potential of the second transfer region 303 between the first transfer region 302 and the third transfer region 304 is also increased such that the second transfer electric potential is not lower than the first transfer electric potential. As one example, the second transfer electric potential is approximately the same as the first transfer electric potential. As another example, the second transfer electric potential is higher than the first transfer electric potential. Consequently, electrons continue to transfer from the first transfer region 302 to the second transfer region 303. After electrons “fall” into the second transfer region 303, the first transfer electric potential of the first transfer region 302 is decreased such that the decreased first transfer electric potential is less than the first charge storage electric potential of the first charge storage node 301 (
In order to continue transfer the electrons, the third transfer electric potential of the third transfer region 304 proximate the second charge storage node 305 is also increased at proximately the same time or after the first transfer electric potential is decreased such that the third transfer electric potential is also not lower than the second transfer electric potential and moreover not higher than the second charge storage electric potential. As a result, electrons continue to transfer from the second transfer region 303 to the third transfer region 304 (
After electrons “fall” into the third transfer region 304, the second transfer electric potential of the second transfer region 303 is decreased such that the decreased second transfer electric potential is approximately the same as or lower than the decreased first transfer electric potential of the first transfer region 302 (
After electrons “fall” into the second charge storage node 305, the third transfer electric potential of the third transfer region 304 is decreased such that the decreased third transfer electric potential is less than the first charge storage electric potential of the first charge storage node 301 as well (
As an example, the transfer electric potential of each transfer region could be configured by varying the applied voltage as the charge transfer signal at each of the input electrodes for each of the transfer regions. During charge transfer, a plurality of pulses are provided to the input electrodes in order to transfer charges in sequence from the first charge storage node 301 to the second charge storage node 305 as described in previous paragraphs. The sequence of charge transfer does not necessarily have to be limited to the same sequence described in previous paragraphs. As one example, at the beginning of a new charge transfer cycle, the first transfer electric potential, the second transfer electric potential and the third transfer electric potential may be increased at substantially the same time (
The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be constructed in accordance with established doctrines of claim interpretation.
