Patent Application
20070063738
Complementary metal-oxide-semiconductor (CMOS) is a process technology that uses p-type and n-type channel devices on the same integrated circuit. Most CMOS circuits contain equal numbers of n and p type transistors. Certain types of CMOS circuits, including complementary CMOS gates (and buffers consisting of series inverters), are inherently power-inefficient because of crossover current that is wasted during switching. For example, in a complementary CMOS gate, one or more inputs connect to a p-channel field effect transistor (PFET) and to an n-channel field effect transistor (NFET). When an input switches low or high causing the output to transition, one FET turns on before the other FET turns off. This latency can generate a large short-circuit current (e.g., from VDD to ground) through the two partially-on FET paths, which is known as crossover current. Crossover current power can range from about 5% to about 15% or more of the total CMOS gate switching power, depending generally on input edge rate.
Each of the respective predriver logic paths 18 and 20 can be implemented as a gate configured for performing a logic function on the one or more INPUT signals. For purposes of consistency, the circuit 10 and similarly configured circuits may be referred to herein as a pseudo-push-pull CMOS logic gate. As used herein, the terms “gate” and “logic gate” are intended to encompass any type of logic element or combination of logic elements (or other circuit means) that is configured or arranged to implement a function on one or inputs. For example, a gate can correspond to a buffer that is configured to pass an input of one or more bits to an output of the buffer (i.e., implementing a unary transfer function). Alternatively, a gate can be configured to implement Boolean logic functions, such as including, but not limited to AND, OR, exclusive-OR (XOR), and combinations thereof. Thus, these and other types of logic gates can be further combined to implement more complex logic functions on the one or more input signals provided at 16.
The predriver logic paths 18 and 20 drive the output stage 14 according to the logic function implemented by the predriver logic. As an example, the first and second predriver logic paths 18 and 20 can be configured as logically identical paths. By “logically-identical,” it is meant that the each of the paths is configured with an arrangement of complementary devices arranged to perform the same logic function along the respective paths.
As a further example, each of the predriver logic paths 18 and 20 is configured as a CMOS gate that includes at least one p-channel field effect transistor (PFET) and at least one n-channel field effect transistor (NFET). The particular number and arrangement of PFET and NFET devices in each of the predriver logic 18 and 20 will vary upon the desired logic function being performed. For ease of fabrication and simplicity of design, although not by necessity, the same number and type of devices (e.g., one or more p-channel field effect transistors and n-channel field effect transistors) can be used in each of the respective paths 18 and 20. The predriver logic paths 18 and 20 thus may correspond to means for performing a logic function (e.g., inverting logic) on the one or more input signals provided at 16 and for providing corresponding logic signals at respective inputs of the output stage 14.
While each of the predriver logic paths 18 and 20 are logically identical, the predriver logic paths are configured so that the one or more input signals propagate in a speed-skewed manner through the respective paths to the output stage 14. Stated differently, PFET and NFET devices in the predriver logic paths 18 and 20 are varied so that the rise/fall delays the predriver logic are not equal, so that there is differential delay between transitions at the respective outputs of the predriver logic paths. The non-equal rise/fall delays can be achieved, for example, by configuring the predriver logic paths 18 and 20 so as to have different PFET to NFET width ratios. For example, the PFET to NFET width ratio of the predriver logic path 18 (which drives the PMOS component 22) can be greater than the PFET to NFET width ratio of the other predriver logic path 20 (which drives the NMOS component 24). As another example, the PFET to NFET width ratio of the predriver logic path 18 is skewed to be greater than 2:1 and the PFET to NFET width ratio of the other predriver logic path 20 is skewed to be less than 2:1. Other variations of PFET to NFET width ratios can also be utilized in the input stage 12.
By way of example, such a configuration enables the PMOS component 22 to be turned off more quickly than the NMOS component 24 is turned on when the outputs from the predriver logic 18 and 20 transition from logic low to logic high. Similarly, when the outputs from the predriver logic 18 and 20 transition from logic high to logic low, the NMOS component 24 to be turned off more quickly than the PMOS component 22 is turned on. The differential delay the transition at the outputs of the predriver logic paths 18 and 20 may be approximately the same (or it may be different) depending on whether the transition at the outputs from is from low to high or high to low. This skewed switching relationship temporarily induces a small voltage differential between the inputs of the PMOS component 22 and the NMOS component 24. It will be appreciated that even a small voltage difference at the inputs of the PMOS component 22 and the NMOS component 24 is sufficient to reduce crossover current significantly because the overlap between on conditions for the PMOS component 22 and the NMOS component 24 are reduced accordingly.
While this approach modifies the trip point of one or both of the predriver logic 18 and 20, it does not significantly increase the overall gate delay. The reduced crossover current further improves the circuit gain, which sufficiently reduces the delay so as to substantially compensate for the change in the trip point. Additionally, since the total driver load perceived by the input stage 12 remains substantially unchanged relative to a traditional CMOS gate, the total predriver area of the circuit 10 will be nearly identical to the traditional gate, except for being split into the separate predriver logic paths 18 and 20 for driving separate input nodes of the output stage. As a result, an IC incorporating pseudo-push-pull CMOS gate circuitry, such as the type shown and described in
The input stage 52 includes a pair of predriver logic paths 60 and 62, each of which is connected to drive a node 64 and 66 at respective inputs of the output stage 54 based on the INPUT signal. Each of the predriver paths 60 and 62 can be logically identical. In the example of
The output stage 54 is configured as a push-pull CMOS output driver that inverts the signals provided at 64 and 66 to generate the OUTPUT signal. The output stage 54 includes a PFET 70 connected in series with an NFET 72 between VDD and electrical ground. With the circuit 50 configured as a buffer (implementing a unary transfer function), OUTPUT=INPUT.
The predriver logic paths 60 and 62 are speed-skewed relative to each other so that a transition of the INPUT signal provided at 56 results in delay in the corresponding transition between the output signals at the respective nodes 64 and 66. By way of example, when the INPUT signal switches from high to low, the PFET 70 is turned off more quickly than the NFET 72 is turned on. Conversely, when the INPUT signal switches from low to high, the NFET 72 is turned off more quickly than the PFET 70 is turned on. This switching latency between the output stage FETs induces a small voltage differential between the PFET input 64 and the NFET input 66. This voltage differential between the PFET input 64 and the NFET input 66 is sufficient to mitigate crossover current significantly since the overlapping on state of the PFET 70 and the NFET 72 will be reduced accordingly. For the example of a typical CMOS FET having a gate-to-source threshold voltage (Vt) of about 350 mV, a voltage difference between the PFET and NFET gates of approximately 30-50 mV will significantly reduce crossover current. As an example, a savings in average switching power can range from about 15% to approximately 25%, which may vary depending signal edge rates utilized in the circuit 50. The peak switching current also is reduced, which mitigates on-chip switching noise and provides improved signal integrity.
By way of further example, the PFET to NFET width ratio of the predriver logic path 60 can be greater than the PFET to NFET width ratio of the predriver logic path 62 so as to provide desired speed-skewed paths. For instance, the PFET to NFET width ratio of the predriver logic path 60 can be skewed to be greater than 2:1 (e.g., 3:1) and the PFET to NFET width ratio of the other predriver logic path 62 can be skewed to be less than 2:1 (e.g., 1:1). Other variations in the FET dimensions can also be implemented to speed-skew the respective paths 60 and 62. While, for simplicity of explanation, a single-bit buffer is depicted in
The input stage 102 includes a pair of predriver logic paths 116 and 118. One of the predriver logic paths 116 drives the node 110 and the other predriver logic path 118 drives the other node 112 of the output stage 108. Each of the predriver logic paths 116 and 118 can be logically identical such that, in the example of
By way of example, the predriver logic path 116 includes a pair of PFETs QP1 and QP2 connected in parallel between VDD and the input 110. The inputs 104 and 106 are connected to the gates of QP1 and QP2, respectively. NFETs QN1 and QN2 are connected in series between the node 110 and electrical ground, with the inputs 104 and 106 being connected to drive the respective gates of QN1 and QN2. As a result, the predriver logic path 116 provides an inverted AND function on the inputs to provide the corresponding logic signal (i.e.,
As mentioned above, the predriver logic path 118 is logically identical to the predriver logic path 116. Thus, in the example of
To reduce CMOS switching power, the predriver logic paths 116 and 118 can be skewed so that there is differential delay between the transitions of the logic output signals at the respective nodes 110 and 112. For instance, the skew can cause the PFET QP3 to turn off more quickly than the NFET QN5 is turned on, such as when respective nodes 110 and 112 transition from low to high. Additionally, the skew can cause NFET QN5 to turn off more quickly than the PFET QP3 turns on (i.e., the PFET turns on more slowly) at the occurrence of a high to low transition at the nodes 110 and 112. These switching latencies between the output stage FETs induce a small voltage differential between nodes 110 and 112, which mitigates crossover current significantly. The skew can be achieved by configuring the PFET to NFET width ratio of the predriver logic path 116 to be greater than the PFET to NFET width ratio of the predriver logic path 118. For example, the PFET to NFET width ratio of the predriver logic path 116 can be skewed to be greater than 2:1 (e.g., 3:1) and the PFET to NFET width ratio of the other predriver logic path 118 can be skewed to be less than 2:1 (e.g., 1:1). Other variations in the FET dimensions can also be implemented to speed-skew the respective logic paths 116 and 118.
The input stage 152 includes a pair of predriver logic paths 166 and 168 electrically connected between the output stage 158 and the respective inputs 154 and 156. One of the predriver logic paths 166 drives the node 160 and the other predriver logic path 168 drives the other node 162 of the output stage 158. Each of the predriver logic paths 166 and 168 can be logically identical such that, in the example of
By way of further example, the predriver logic path 166 includes a pair of PFETs QP6 and QP7 connected in series between VDD and the node 160. The inputs 154 and 156 are connected to the gates of QP6 and QP7, respectively. NFETs QN6 and QN7 are connected in parallel between the node 160 and electrical ground, with the inputs 154 and 156 being connected to drive the respective gates of QN6 and QN7. The predriver logic path 166 thus performs an inverted OR function on the inputs A and B to provide the corresponding logic signal (i.e.,
As mentioned above, the predriver logic path 168 is logically identical to the predriver logic path 166. Thus, in the example of
To reduce CMOS switching power, the predriver logic paths 166 and 168 can be skewed so that there is delay in the transition of the logic output signals at the respective nodes 160 and 162. For instance, the skew can cause the PFET QP8 to turn off more quickly than the NFET QN10 is turned on, such as at the occurrence of a low to high transition at 160 and 162 (e.g., at the gates of QP8 and QN10). Additionally, at an opposing logic transition (e.g., a high to low transition) at 160 and 162, the skew can cause NFET QN10 to turn off more quickly than PFET QP8 turns on. In response to such switching latencies between the output stage FETs, a small voltage differential is induced between nodes 160 and 162, which mitigates crossover current significantly. The skew can be achieved by configuring the PFET to NFET width ratio of the predriver logic path 166 to be greater than the PFET to NFET width ratio of the predriver logic path 168. For example, the PFET to NFET width ratio of the predriver logic path 166 can be skewed to be greater than 2:1 and the PFET to NFET width ratio of the other predriver logic path 168 can be skewed to be less than 2:1, such as described herein. Other variations in the FET dimensions can also be implemented to speed-skew the respective logic paths 166 and 168.
From the foregoing description of various embodiments, those skilled in the art will appreciate that average switching power of various gate designs can be reduced by implementing the gate as a pseudo-push-pull CMOS gate, such as described herein. The use of pseudo-push-pull CMOS gate further can achieve further increases the power savings for IC designs operating with slower edge rates, although the approach is not limited to ICs operating at any particular edge rates.
What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.
