CMOS voltage reference

Abstract

A CMOS reference voltage generating circuit is described that produces a reference voltage by taking the difference between the gate-source voltages of two p-type and n-type CMOS transistors operating in the saturation region, one of the gate-source voltages being multiplied by a gain factor. Different circuits are described for situations where the n- or p-type transistors have the greater temperature dependence.

Description

FIELD OF THE INVENTION

This invention relates to a voltage reference, and in particular to a voltage reference that can be implemented in CMOS technology and with good temperature stability.

BACKGROUND OF THE INVENTION

Being able to provide a voltage reference is important in many analog circuits such as linear regulators and data converters. The specifications of the voltage reference, including the temperature coefficient (TC), line regulation (LR) and noise all directly affect the performance of the circuit in which the voltage reference is incorporated. Common ways of providing a voltage reference include bipolar junction transistors, zener diodes, and JFET or depletion-mode NMOS transistors.

Difficulties arise, however, in implementing conventional voltage reference designs in CMOS technology. CMOS technology is popular in circuit design because of the relatively low fabrication costs and short turn-around periods involved. It is therefore strongly desirable to be able to implement a complete circuit, including any necessary voltage reference in CMOS technology.

PRIOR ART

In an attempt to implement a voltage reference in a CMOS environment it is known to use vertical bipolar junction transistors in p- or n-well and p- or n-MOS transistors operating in the weak inversion region to implement a bandgap reference voltage. An example of such a prior art proposal is shown in FIG. 1 . In this design the voltage reference V ref =V be (of Q 3 ( 1 ))+IR 2 . The base-emitter voltage of Q 3 ( 1 ) has a temperature dependency such that it decreases with temperature, while the current I generated by the current mirror has the property of increasing with temperature and thus IR 2 also increases with temperature. Because the two components of the voltage reference have opposite temperature dependencies, by combining them a temperature independent voltage reference may be obtained. A disadvantage of such designs, however, is that trimming is required in the fabrication process and which substantially increases the fabrication costs.

U.S. Pat. No. 5,434534 (Lucas) describes a voltage reference circuit in which the threshold voltages of a p-type and of a n-type CMOS transistor are summed to provide a relatively temperature stable reference voltage. However this design is not completely satisfactory for a number of reasons. Firstly the temperature dependence of a p-type and an n-type CMOS transistor varies for different technologies and in general the dependence of p-type and n-type CMOS transistors are not the same. Thus summing the two voltages without any weighting cannot always provide a complete temperature compensated reference voltage. Furthermore, the circuit of Lucas sums the threshold voltages of p- and n-type CMOS transistors, which implies that a higher supply voltage is required.

SUMMARY OF THE INVENTION

According to the present invention there is provided a circuit for generating a reference voltage comprising a p-type CMOS transistor and an n-type CMOS transistor, said CMOS transistors being operated in the saturation region, and wherein the reference voltage is obtained from the difference between the gate-source voltage of the p- and n-type CMOS transistors with a gain factor greater than or less than 1 being applied to the gate-source voltage of either the p- or n-type CMOS transistor such that the reference voltage is given by the equation: V ref =k 1 ·V GSn −k 2 ·|V GSp | where either k 1 or k 2 is the gain factor and the other is unity.

It will be understood that depending on the materials used for the two CMOS transistors and their structure, either the p-type or the n-type transistor may have the greater temperature dependence. For applications where the p-type transistor has a greater temperature dependence the general equation may be implemented with either (1) k 1 >1, k 2 =1, or (2) k 1 =1, k 2 <1.

In a first embodiment of the invention (1) is implemented and the gain factor is applied to the gate-source voltage of the n-type transistor. In this embodiment the circuit may implement the equation: $$ V ref = ( 1 + R 1 R 2 ) · V GSn - &LeftBracketingBar; V GSp &RightBracketingBar;

where V ref is the reference voltage, V GSn and V GSp are respectively the gate-source voltages of the n- and p-type CMOS transistors, and R 1 and R 2 are respectively first and second resistors connected respectively between the gate of the n-type transistor and the source of the p-type transistor (R 1 ), and between ground and the gate of the n-type transistor (R 2 ).

In this embodiment the values of R 1 and R 2 are set so as to minimise the temperature coefficient coefficient of the reference voltage circuit. In particular R 1 and R 2 are selected such that $$ R 1 R 2 = β vthp β vthn - 1

where β vthn and β vthp are the temperature coefficients of the threshold voltages of the n- and p-type CMOS transistors respectively. Furthermore, the temperature coefficient of the circuit is minimised by adjusting the transistor size ratio of the CMOS transistors such that $$ ( W L ) p ( W L ) n = μ n ⁢ ( T o ) μ p ⁢ ( T o ) ⁢ ( T r T o ) β μ ⁢   ⁢ p - β μ ⁢   ⁢ n ( 1 + R 1 R 2 ) 2 ⁢ ( 1 2 + β μ ⁢   ⁢ n 2 ⁢ β μ ⁢   ⁢ p ) 2

where

(i) $$ ( W L ) p ⁢   ⁢ and ⁢   ⁢ ( W L ) n

 are the channel width to channel length ratio of p-type and n-type CMOS transistors.

(ii) μ p (T o ) and μ n (T o ) are the mobilities of p-type and n-type CMOS transistors at temperature T o =0° C.

(iii) β μp and β μn are the mobility exponents of p-type and n-type CMOS transistors.

(iv) T r is the reference temperature which is set to have zero temperature coefficient.

In a second embodiment of the invention (2) is implemented and the gain factor is applied to the gate-source voltage of the p-type transistor. In this embodiment the circuit implements the equation $$ V ref = V GSn - ( R 2 R 1 + R 2 ) · &LeftBracketingBar; V GSp &RightBracketingBar;

where V ref is the reference voltage, V GSn and V GSp are respectively the gate-source voltages of the n and p-type CMOS transistors, and R 1 and R 2 are respectively first and second resistors where R 1 is connected between the source of the p-type transistor and the gate of the n-type transistor, and R 2 is connected between the gate of the n-type transistor and the gate of the p-type transistor, and wherein the reference voltage is taken from the junction of the gate and the drain of the p-type transistor. As in the first embodiment of the invention, the temperature dependence of the circuit can be minimised by setting the resistor ratio, and the transistor size ratio.

For applications where the n-type transistor has a greater temperature dependence, the general equation may be implemented with either (3) k 1 <1, k 2 =1, or (4) k 1 =1, k 2 >1.

In a third embodiment of the invention (3) is implemented and the circuit implements the equation $$ V ref = ( R 2 R 1 + R 2 ) · V GSn - &LeftBracketingBar; V GSp &RightBracketingBar; .

In a fourth embodiment of the invention (4) is implemented and the circuit implements the equation $$ V ref = V GSn - ( 1 + R 1 R 2 ) · &LeftBracketingBar; V GSp &RightBracketingBar; .

In both of these embodiments the temperature dependence of the circuit can again be minimised by adjusting the resistor ratio and the transistor size ratio.

In both of these embodiments the temperature dependence of the circuit can again be minimised by adjusting the resistor ratio and the transistor size ratio.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a voltage reference according to the prior art,

FIG. 2 is a circuit diagram of a voltage reference according to a first embodiment of the present invention,

FIG. 3 is a circuit diagram showing the circuit of FIG. 2 in the context of a circuit supplying a bias current,

FIG. 4 is a plot illustrating the temperature coefficient (TC) of the embodiment of FIGS. 2 & 3 ,

FIG. 5 is a plot illustrating the TC line regulation of the embodiment of FIGS. 2 & 3 ,

FIGS. 6 to 8 show the effect on the TC of the voltage reference of the first embodiment with variations in the resistor ratio,

FIG. 9 is a circuit diagram showing a second embodiment of the present invention,

FIG. 10 is a circuit diagram showing a third embodiment of the present invention, and

FIG. 11 is a circuit diagram showing a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention is based on the concept of taking the difference between the gate-source voltages of an n-type and a p-type MOSFET operating in the saturation region. Both n- and p-type MOSFETs have a temperature dependence that is similar in that the gate-source voltage decreases with increasing temperature. However the temperature coefficient may differ from one MOSFET to another and so rather than taking the simple difference between the two gate-source voltages, a gain factor is applied to one or the other of the two gate-source voltages in order to compensate for this difference in temperature coefficient. In this way a temperature independent voltage reference can be obtained.

Four embodiments of the invention will now be described. As will be come clear all the embodiments implement the general equation: V ref =k 1 ·V GSn −k 2 ·|V GSp |. In general terms the temperature dependence of the p-type or the n-type CMOS transistors will be greater than the other. When the temperature dependence of the p-type is stronger, the general equation can be implemented such that either (1) k 1 >1, k 2 =1, or (2) k 1 =1, k 2 <1. Where the temperature dependence of the n-type CMOS transistor is greater than the p-type, then the general equation can be implemented by two further possibilities such that either (3) k 1 <1, k 2 =1, or (4) k 1 =1, k 2 >1.

A first embodiment of the invention is illustrated by the circuit of FIG. 2 . The circuit of this embodiment implements the equation V ref =k 1 ·V GSn −k 2 ·|V GSp | with k 1 >1, k 2 =1. In this embodiment: $$ V ref = ( 1 + R 1 R 2 ) · V GSn - &LeftBracketingBar; V GSp &RightBracketingBar;

In this embodiment the gain factor is applied to the gate-source voltage of the n-type MOSFET (MN) and since this gain factor is always larger than 1 this embodiment is appropriate for circuits where the n- and p-type MOSFETS are such that the p-type MOSFET has a greater temperature coefficient than the n-type.

As can be seen from FIG. 2 the CMOS voltage reference requires a bias current IB, and FIG. 3 shows how the CMOS voltage reference circuit may be applied in a circuit that is adapted to provide such a bias current. The part of the circuit within broken lines corresponds to the voltage reference circuit of FIG. 2 , while the remainder of the circuit is a conventional design that is adapted to feed a bias current into the voltage reference. It will be understood, however that any conventional source of a bias current may be employed. In the circuit of FIG. 3 a bias current of M×IB is created.

In this embodiment the temperature dependence of the voltage reference is given by the equation: $$ ∂ V ref ∂ T = ( 1 + R 1 R 2 ) ⁢ ∂ V GSn ∂ T - ∂ &LeftBracketingBar; V GSp &RightBracketingBar; ∂ T = [ - ( 1 + R 1 R 2 ) ⁢ β vthn + β vthp ] + β μ ⁢   ⁢ p T o ⁢ 2 ⁢ MI B ⁡ ( T o ) μ p ⁡ ( T o ) ⁢ C ox ⁡ ( W L ) p ×   ⁢ ⁢   ⁢ [ &AutoRightMatch; ⁢   ⁢ ( 1 +   ⁢ R 1 R 2 ) ⁢   ⁢ ( 1 2 +   ⁢ β μ ⁢   ⁢ n 2 ⁢ β μ ⁢   ⁢ p ) &AutoRightMatch; ⁢   ⁢ μ p ⁡ ( T o ) ⁢ ( W L ) p μ n ⁡ ( T o ) ⁢ ( W L ) n ⁢   ⁢   ⁢ ( T T o ) β μ ⁢   ⁢ p + β μ ⁢   ⁢ n - 2 2 ⁢   -   ⁢ ( T T o ) β μ ⁢   ⁢ p - 1 ⁢   ]

where

(i) β vthp and β vthn are the temperature coefficients of the threshold voltages of p-type and n-type CMOS transistors.

(ii) $$ ( W L ) p ⁢   ⁢ and ⁢   ⁢ ( W L ) n

 and are the channel width to channel length ratio of p-type and n-type CMOS transistors.

(iii) μ p (T o ) and μ n (T o ) are the mobilities of p-type and n-type CMOS transistors at temperature T o =0° C.

(vi) β μp and β μn are the mobility exponents of p-type and n-type CMOS transistors.

(v) C ox is the capacitance of gate oxide of a CMOS transistor.

(vi) I B (T o ) is the bias current at T o =0° C., and

(vii) M is a multiple factor of the current mirror.

It will thus be seen that the temperature dependence depends on a linear term and a higher-order term. The linear term can be set by appropriately adjusting the resistor ratio such that: $$ R 1 R 2 = β vthp β vthn - 1

while the higher order can be set to zero at room temperature by appropriately adjusting the transistor size ratio such that $$ ( W L ) p ( W L ) n = μ n ⁡ ( T o ) μ p ⁡ ( T o ) ⁢ ( T r T o ) β μ ⁢   ⁢ p - β μ ⁢   ⁢ n ( 1 + R 1 R 2 ) 2 ⁢ ( 1 2 + β μ ⁢   ⁢ n 2 ⁢ β μ ⁢   ⁢ p ) 2

where

(i) $$ ( W L ) P ⁢   ⁢ and ⁢   ⁢ ( W L ) n

 are the channel width to channel length ratio of p-type and n-type CMOS transistors.

(ii) μ p (T o ) and μ n (T o ) are the mobilities of p-type and n-type CMOS transistors at temperature T o =0° C.

(iii) β μp and β μn are the mobility exponents of p-type and n-type CMOS transistors.

The embodiment of FIG. 3 has been implemented by way of an example in an AMS 0.6 μm CMOS process with an occupied chip area of 0.051 mm 2 which is significantly smaller than a conventional bandgap reference. The minimum supply voltage is 1.4 V and this can be reduced further if lower threshold devices are used. The supply current is 7 μA at 100° C.

FIG. 4 shows the reference voltage as a function of temperature at various supply voltages in order that the temperature coefficient can be determined, while FIG. 5 plots the temperature coefficient (at room temperature) as a function of the supply voltage. It will be seen from these figures that a TC of 21 ppm/° C. from 0 to 100°C. is obtained at a supply voltage of 1.4V, while the TC changes from 21 to 50 ppm/°C. when the supply voltage increases from 1.4 to 3V. This increase in TC is due to current matching difficulties of M 3 and M 4 in the bias circuit with a higher supply voltage. A pre-regulated circuit can be added to provide a more stable supply to the voltage reference.

The sensitivity of the voltage reference to variations in the resistor ratio can be tested by introducing an intentional variation into the ratio. The results are shown in FIGS. 6 to 8 which show respectively ratio variations of 2.27%, 4.65% and 7.14%. With a large variation in the resistor ration there is a larger increase in the TC because a complete cancellation of the temperature dependence of the threshold voltages cannot be achieved. In practice, however, variations in the resistor ratio as large as 7.14% seldom occur.

FIG. 9 shows a second embodiment of the invention in which the reference voltage circuit is shown in the area within broken lines, the remainder of the circuit representing a current supply circuit. This circuit is also suitable for a situation in which the temperature dependence of the p-type transistor is greater than that of the n-type transistor. IN particular the circuit of this embodiment implements the general equation V ref =k 1 ·V GSn −k 2 ·|V GSp | with k 1 =1, k 2 <1. In particular, in this embodiment the voltage reference is given by the equation $$ V ref = V GSn - ( R 2 R 1 + R 2 ) · &LeftBracketingBar; V GSp &RightBracketingBar;

In this embodiment therefore the gain factor is applied to the gate-source voltage of the p-type transistor, however in contrast to the embodiment of FIGS. 2 and 3 the gain factor is always smaller than 1.

As with the first embodiment, the temperature coefficient of the linear term can be minimised by setting the resistor ratio with the same equation as in the first embodiment, while the higher order term can be minimised by setting the transistor size ratio as in the first embodiment. It is important to note that in both embodiments the most important parameter in minimising the temperature coefficient is setting the resistor ratio, with the transistor ratio being a refinement.

In both embodiments of the invention a relatively temperature stable reference voltage can be obtained that may readily be implemented in CMOS technology and which does not require extensive trimming. The voltage reference can subsequently be increased or decreased as required by converter circuitry downstream of the reference voltage generating circuit of the present invention.

Two further embodiments will now be described that are suitable for applications where the n-type CMOS transistor has a greater temperature dependence than the p-type transistor.

In the embodiment of FIG. 10 the general equation V ref =k 1 ·V GSn −k 2 ·|V GSp | is implemented with k 1 <1, k 2 =1. In particular in the embodiment of FIG. 10 : $$ V ref = ( R 2 R 1 + R 2 ) · V GSn - &LeftBracketingBar; V GSp &RightBracketingBar; .

In the embodiment of FIG. 11 the general equation V ref =k 1 ·V GSn −k 2 ·|V GSp | is implemented with) k 1 =1, k 2 >1. In particular in the embodiment of FIG. 11 : $$ V ref = V GSn - ( 1 + R 1 R 2 ) · &LeftBracketingBar; V GSp &RightBracketingBar; .

For the embodiments of both FIGS. 10 and 11 , the linear term of the temperature dependence of the reference voltage may be eliminated by appropriately setting the resistor ratio such that $$ R 1 R 2 = β vthn β vthp - 1

where β vthn and β vthp are the temperature coefficients of the threshold voltages of n- and p-type CMOS transistor, respectively.

For the embodiments of both FIGS. 10 and 11 the non-linear term of the temperature dependence of the reference voltage is cancelled by the transistor ratio, which is given by $$ ( W L ) p ( W L ) n = μ n ⁡ ( T o ) μ p ⁡ ( T o ) ⁢ ( 1 + R 1 R 2 ) 2 ⁢ ( T r T o ) β μ ⁢   ⁢ p - β μ ⁢   ⁢ n ( 1 2 + β μ ⁢   ⁢ n 2 ⁢ β μ ⁢   ⁢ p ) 2

(i) $$ ( W L ) P ⁢   ⁢ and ⁢   ⁢ ( W L ) n

 are the channel width to channel length ratio of p-type and n-type CMOS transistors,

(ii) μ p (T o ) and μ n (T o ) are the mobilities of p-type and n-type CMOS transistors at temperature T o =0° C.,

(iii) β μp and β μn are the mobility exponents of p-type and n-type CMOS transistors, and

(iv) T r is the reference temperature, which is set to have zero temperature coefficient.

Claims

1. A circuit for generating a reference voltage comprising a p-type CMOS transistor and an n-type CMOS transistor, said CMOS transistors being operated in the saturation region, and wherein the reference voltage is obtained from the difference between the gate-source voltage of the p- and n-type CMOS transistors with a gain factor greater than or less than 1 being applied to the gate-source voltage of either the p- or n-type CMOS transistor such that the reference voltage is given by the equation: Vref=k1·VGSn−k2·|VGSp| where either k1 or k2 is the gain factor and the other is unity.

2. A reference voltage circuit as claimed in claim 1 wherein the temperature dependence of the p-type transistor is greater than the temperature dependence of the n-type transistor and either (1) k1>1, k2=1, or (2) k1=1, k2<1.

3. A reference voltage circuit as claimed in claim 2 wherein the circuit implements the equation: Vref=(1+R1R2)·VGSn-&LeftBracketingBar;VGSp&RightBracketingBar;where Vref is the reference voltage, VGSn and VGSp are respectively the gate-source voltages of the n- and p-type CMOS transistors, and R1 and R2 are respectively first and second resistors connected respectively between the gate of the n-type transistor and the source of the p-type transistor (R1), and between ground the gate of the n-type transistor (R2).

4. A reference voltage circuit as claimed in claim 3 wherein the values of R1 and R2 are set so as to minimise the temperature coefficient of the reference voltage circuit.

5. A reference voltage circuit as claimed in claim 4 wherein R1 and R2 are selected such that R1R2=βvthpβvthn-1where βvthn and βvthp are the temperature coefficients of the threshold voltages of the n- and p-type CMOS transistors respectively.

6. A reference voltage circuit as claimed in claim 3 wherein the temperature coefficient of the circuit is minimised by adjusting the transistor size ratio of the CMOS transistors such that (WL)p(WL)n=μn⁢(To)μp⁢(To)⁢(TrTo)βμ⁢ ⁢p-βμ⁢ ⁢n(1+R1R2)2⁢(12+βμ⁢ ⁢n2⁢βμ⁢ ⁢p)2where(i) (WL)p⁢ ⁢and⁢ ⁢(WL)n are the channel width to channel length ratio of p-type and n-type CMOS transistors. (ii) μp(To) and μn(To) are the mobilities of p-type and n-type CMOS transistors at temperature To=0° C. (iii) βμp and βμn are the mobility exponents of p-type and n-type CMOS transistors, (iv) Tr is the reference temperature which is set to have zero temperature coefficient.

7. A reference voltage circuit as claimed in claim 2 wherein the circuit implements the equation Vref=VGSn-(R2R1+R2)·&LeftBracketingBar;VGSp&RightBracketingBar;where Vref is the reference voltage, VGSn and VGSp are respectively the gate-source voltages of the n- and p-type CMOS transistors, and R1 and R2 are respectively first and second resistors where R1 is connected between the source of the p-type transistor and the gate of the n-type transistor, and R2 is connected between the gate of the n-type transistor and the gate of the p-type transistor, and wherein the reference voltage is taken from the junction of the gate and the drain of the p-type transistor.

8. A reference voltage circuit as claimed in claim 7 wherein the values of R1 and R2 are set so as to minimise the temperature coefficient of the reference voltage circuit.

9. A reference voltage circuit as claimed in claim 8 wherein R1 and R2 are selected such that R1R2=βvthpβvthn-1where βvthn and βvthp are the temperature coefficients of the threshold voltages of the n- and p-type CMOS transistors respectively.

10. A reference voltage circuit as claimed in claim 7 wherein the temperature coefficient of the circuit is minimised by adjusting the transistor size ratio of the CMOS transistors such that (WL)p(WL)n=μn⁢(To)μp⁢(To)⁢(TrTo)βμ⁢ ⁢p-βμ⁢ ⁢n(1+R1R2)2⁢(12+βμ⁢ ⁢n2⁢βμ⁢ ⁢p)2where(i) (WL)p⁢ ⁢and⁢ ⁢(WL)n are the channel width to channel length ratio of p-type and n-type CMOS transistors. (ii) μp(To) and μn(To) are the mobilities of p-type and n-type CMOS transistors at temperature To=0° C. (v) βμp and βμn are the mobility exponents of p-type and n-type CMOS transistors, (vi) Tr is the reference temperature which is set to have zero temperature coefficient.

11. A reference voltage circuit as claimed in claim 1 wherein the temperature dependence of the n-type transistor is greater than the temperature dependence of the p-type transistor and either (1) k1<1, k2=1, or (2) k1=1, k2>1.

12. A reference voltage circuit as claimed in claim 11 wherein the circuit implements the equation: Vref=(R2R1+R2)·VGSn-&LeftBracketingBar;VGSp&RightBracketingBar;.

13. A reference voltage circuit as claimed in claim 12 wherein the values of R1 and R2 are set so as to minimise the temperature coefficient of the reference voltage circuit.

14. A reference voltage circuit as claimed in claim 13 wherein the temperature coefficient of the circuit is minimised by adjusting the resistor ratio such that R1R2=βvthnβvthp-1where βvthn and βvthp are the temperature coefficients of the threshold voltages of n- and p-type CMOS transistors, respectively.

15. A reference voltage circuit as claimed in claim 12 wherein the temperature coefficient of the circuit is minimised by adjusting the transistor size ratio of the CMOS transistors such that (WL)p(WL)n=μn⁡(To)μp⁡(To)⁢(1+R1R2)2⁢(TrTo)βμ⁢ ⁢p-βμ⁢ ⁢n(12+βμ⁢ ⁢n2⁢βμ⁢ ⁢p)2where(i) (WL)p⁢ ⁢and⁢ ⁢(WL)n are the channel width to channel length ratio of p-type and n-type CMOS transistors, (ii) μp(To) and μn(To) are the mobilities of p-type and n-type CMOS transistors at temperature To=0° C., (iii) βμp and βμn are the mobility exponents of p-type and n-type CMOS transistors, and (iv) Tr is the reference temperature, which is set to have zero temperature coefficient.

16. A voltage reference circuit as claimed in claim 11 wherein said circuit implements the equation Vref=VGSn-(1+R1R2)·&LeftBracketingBar;VGSp&RightBracketingBar;.

17. A reference voltage circuit as claimed in claim 16 wherein the values of R1 and R2 are set so as to minimise the temperature coefficient of the reference voltage circuit.

18. A reference voltage circuit as claimed in claim 17 wherein the temperature coefficient of the circuit is minimised by adjusting the resistor ratio such that R1R2=βvthnβvthp-1where βvthn and βvthp are the temperature coefficients of the threshold voltages of n- and p-type CMOS transistors, respectively.

19. A reference voltage circuit as claimed in claim 16 wherein the temperature coefficient of the circuit is minimised by adjusting the transistor size ratio of the CMOS transistors such that (WL)p(WL)n=μn⁢(To)μp⁢(To)⁢(1+R1R2)2⁢(TrTo)βμ⁢ ⁢p-βμ⁢ ⁢n(12+βμ⁢ ⁢n2⁢ ⁢βμ⁢ ⁢p)2where(i) (WL)p⁢ ⁢and⁢ ⁢(WL)n are the channel width to channel length ratio of p-type and n-type CMOS transistors, (ii) μp(To) and μn(To) are the mobilities of p-type and n-type CMOS transistors at temperature To=0° C., (v) βμp and βμn are the mobility exponents of p-type and n-type CMOS transistors, and (vi) Tr is the reference temperature, which is set to have zero temperature coefficient.