Patent Application
20230320058
The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). FinFETs have been used in a variety of applications, for example, to implement system-on-a-chip (SOC) logic devices and memory devices such as static random-access memory (SRAM), among others. Generally, SOC logic devices and SRAM devices have different design and performance requirements. For instance, as compared to SOC logic devices, SRAM devices require tighter control of short-channel effects (SCEs) (e.g., for Vmin improvement). However, while being necessary to meet power, performance, area, and cost (PPAC) scaling requirements, simultaneous optimization (co-optimization) of the performance and/or design requirements of SOC logic devices and SRAM devices has been challenging. Thus, existing techniques have not proved entirely satisfactory in all respects.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm. Additionally, in some embodiments, the term “source/drain region(s)” may refer to a source or a drain, individually or collectively dependent upon the context.
It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors or fin-type multi-gate transistors referred to herein as FinFET devices. Such a device may include a P-type metal-oxide-semiconductor FinFET device or an N-type metal-oxide-semiconductor FinFET device. The FinFET device may be a dual-gate device, tri-gate device, bulk device, silicon-on-insulator (SOI) device, and/or other configuration. One of ordinary skill may recognize other embodiments of semiconductor devices that may benefit from aspects of the present disclosure. For example, some embodiments as described herein may also be applied to gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (π-gate) devices.
The present disclosure is generally related to semiconductor devices and methods of forming the same. In particular, embodiments of the present disclosure provide a process and/or structure for co-optimization of system-on-a-chip (SOC) logic devices and static random-access memory (SRAM) devices to meet power, performance, area, and cost (PPAC) scaling requirements. In some examples, such co-optimization may be achieved by controlling respective source/drain (S/D) depths for each of the SOC logic devices and SRAM devices, as described in more detail below.
FinFETs have been used in a variety of applications, for example, to implement SOC logic devices and memory devices such as SRAM devices, among others. In at least some existing embodiments, FinFETs used to make SOC logic devices and SRAM devices may have substantially the same contacted poly pitch (CPP) and a similar fin critical dimension (CD). As a result, SOC logic devices and SRAM devices may have comparable source/drain (S/D) depths (e.g., S/D junction depths). However, each of these device types have different design and performance requirements. For instance, as compared to SOC logic devices, SRAM devices require tighter control of short-channel effects (SCEs) (e.g., for Vmin improvement). Thus, while being necessary to meet power, performance, area, and cost (PPAC) scaling requirements, simultaneous optimization (co-optimization) of the performance and/or design requirements of SOC logic devices and SRAM devices has been challenging. Thus, existing techniques have not proved entirely satisfactory in all respects.
Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include structures and methods for the co-optimization of SOC logic devices and SRAM devices. In various embodiments, a semiconductor device may include individual device structures to simultaneously meet the performance and design requirements of each of the SOC logic devices and SRAM devices. As an example, and in accordance with the disclosed embodiments, intentionally different source/drain depths for logic devices (e.g., SOC logic devices) and SRAM devices are provided. In some embodiments, the source/drain depth for SRAM devices may be shallower than the source/drain depth for SOC logic devices, for example, to provide tighter control of SCEs.
In some embodiments, formation of the intentionally different source/drain depths may be accomplished by (i) a 2-step or multi-step S/D recess process using a high-grade photomask (e.g., such as EUV), or by (ii) an implantation-enhanced S/D recess process using at least one low-grade photomask. The implantation-enhanced S/D recess process may be accomplished at a reduced cost using simplified lithography, for example, as compared to the 2-step or multi-step S/D recess process. After the S/D recess process, an epitaxial S/D growth process is performed (e.g., in N-type and P-type regions of both SOC logic devices and SRAM devices) to form respective epitaxial S/D features having different source/drain depths. It is also noted that in various embodiments, the epitaxial S/D features are formed such that a top surface of the epitaxial S/D features is higher than a top surface of a corresponding fin structure to ensure full contact between the epitaxial S/D features and device channels formed within the fin structure. In general, embodiments disclosed herein provide device co-optimization for power, performance, area, cost (PPAC) metrics, circuit optimization by application-aware source/drain design, and possible cost reduction (e.g., using the implantation-enhanced S/D recess process). Regardless of the approach used, embodiments of the present disclosure provide independent optimization of S/D depth for N-type and P-type SOC logic device and SRAM devices. Additional embodiments and advantages are discussed below and/or will be evident to those skilled in the art in possession of this disclosure.
For purposes of the discussion that follows,
Referring to
It is noted that certain aspects of the methods of
The method 200 begins at block 202 where a substrate including a partially fabricated device is provided. Referring to the example of
Each of the N-type and P-type SRAM devices 301N, 301P, and the N-type and P-type SOC logic devices 303N, 303P may be formed within different regions 302A, 302B of the same substrate, such as a silicon substrate. In some cases, the substrate may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate may include various doping configurations depending on design requirements as is known in the art. The substrate may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate may include a compound semiconductor and/or an alloy semiconductor. Further, the substrate may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features.
As shown in
In some embodiments, the number of fins used to form each of the N-type and P-type SRAM devices 301N, 301P, and the N-type and P-type SOC logic devices 303N, 303P, within each of the regions 302A, 302B, may vary. In some cases, the N-type and P-type SRAM devices 301N, 301P formed in the region 302A may each include a single fin, and the N-type and P-type SOC logic devices 303N, 303P formed in the region 302B may each include two fins. However, other embodiments are possible. For instance, in some examples, the N-type and P-type SRAM devices 301N, 301P formed in the region 302A may each alternatively include two fins. Further, in some embodiments, the N-type and P-type SOC logic devices 303N, 303P formed in the region 302B may each include a single fin.
In various embodiments, each of the N-type and P-type SRAM devices 301N, 301P, and the N-type and P-type SOC logic devices 303N, 303P also include gate stacks 316 formed over respective fins 302N, 302P, 304N, 304P within each of the regions 302A, 302B. In an embodiment, the gate stacks 316 are dummy (sacrificial) gate stacks that are subsequently removed and replaced by a final gate stack at a subsequent processing stage. For example, the gate stacks 316 may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG). While the present discussion is directed to a replacement gate (gate-last) process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible (e.g., such as a gate-first process). The portion of the fins 302N, 302P, 304N, 304P underlying their respective gate stacks 316 may be referred to as a channel region of the device. The gate stacks 316 may also define source/drain regions 318 of the fins 302N, 302P, 304N, 304P, for example, which includes the regions of the fins 302N, 302P, 304N, 304P adjacent to the gate stacks 316 and on opposing sides of the channel region.
In some embodiments, the gate stacks 316 include a dielectric layer and an electrode layer formed over the dielectric layer. In some embodiments, the dielectric layer of the gate stacks 316 includes silicon oxide. Alternatively, or additionally, the dielectric layer of the gate stacks 316 may include silicon nitride, a high-K dielectric material or other suitable material. In some embodiments, the electrode layer of the gate stacks 316 may include polycrystalline silicon (polysilicon). In some embodiments, one or more spacer layers 320 may be formed on sidewalls of the gate stacks 316. In some cases, the one or more spacer layers 320 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., with a dielectric constant ‘k’<7), and/or combinations thereof. In some embodiments, the one or more spacer layers 320 include multiple layers, such as main spacer layers, liner layers, and the like.
In various examples, and because each of the SRAM devices and SOC logic devices have substantially the same CPP, the gate stacks 316 in the different regions 302A, 302B may also have substantially the same gate spacings S1. However, in at least some cases, the gate spacings in each of the different regions 302A, 302B may be different. Also, in various embodiments, a width of the gate stacks 316 in the regions 302A, 302B may be substantially the same, or they may be different.
The method 200 proceeds to block 204 where a first photo/etch process for N-type S/D regions is performed. Referring to the example of
In some embodiments, and due to the smaller dimensions of the opening formed in the patterned mask layer 407 to expose the N-type SRAM device 301N, the photomask used in the lithography process may be a high-grade photomask with high resolution, compared to a low-grade photomask that may be used during other photolithography processes and/or in other embodiments, as described below. Accordingly, the lithography system used in the lithography process used to form the patterned mask layer 407 may also be a high-grade lithography system with high resolution. For example, a high-grade photomask and lithography system may be associated with an extreme ultra-violet (EUV) light and an EUV lithography system having a resolution about several nanometers, while a low-grade photomask and lithography system may be associated with a deep ultra-violet (DUV) lithography system having a resolution about tens of nanometers. In another example, a high-grade photomask and lithography system may be associated with a DUV lithography system using argon fluoride (ArF) excimer laser and having a resolution of about 65 nm, while a low-grade photomask and lithography system may be associated with a DUV lithography system using krypton fluoride (KrF) excimer laser and having a resolution of about 130 nm.
Whether or not a hard mask layer is used, and after exposure of the N-type SRAM device 301N, an etching process (e.g., wet etch, dry etch, or combination thereof) is performed to remove portions of the fin 302N in the source/drain region 318 of the N-type SRAM device 301N to form the source/drain recess 402. In some embodiments, the source/drain etching process is a dry etch using an etchant that includes a chlorine-containing gas, a fluorine-containing gas or both, such as Cl2, CCl2F2, SF6, or a combination thereof. After formation of the source/drain recess 402, the patterned mask layer 407 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
As shown in
The method 200 proceeds to block 206 where a second photo/etch process for N-type S/D regions is performed. Referring to the example of
Whether or not a hard mask layer is used, and after exposure of the N-type SOC logic device 303N, an etching process (e.g., wet etch, dry etch, or combination thereof) is performed to remove portions of the fin 304N in the source/drain region 318 of the N-type SOC logic device 303N to form the source/drain recess 502. In some embodiments, the source/drain etching process is a dry etch using an etchant that includes a chlorine-containing gas, a fluorine-containing gas or both, such as Cl2, CCl2F2, SF6, or a combination thereof. After formation of the source/drain recess 502, the patterned mask layer 507 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
As shown in
The method 200 then proceeds to block 208 where N-type source/drain features are formed. Referring to
In some examples, prior to forming the N-type source/drain features 602, 604, a mask layer may be deposited and patterned to form a patterned mask layer 607 having openings which expose the N-type SRAM device 301N and the N-type SOC logic device 303N, while the P-type SRAM device 301P and the P-type SOC logic device 303P remain protected by the patterned mask layer 607. In some embodiments, the mask layer includes a resist layer and/or a hard mask layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other appropriate hard mask layer) such that the patterned mask layer 607 may include a patterned resist layer and/or a patterned hard mask layer. If only a resist layer is used, the deposited resist layer may be patterned (e.g., by exposure and development of the resist layer) to form the patterned mask layer 607. Alternatively, if a hard mask layer is used, a pattern may be initially formed in the resist layer (e.g., by exposure and development), after which the pattern may be transferred to an underlying hard mask layer (e.g., by etching) to form the patterned mask layer 607. In some cases, any remaining portion of the resist layer may be removed after patterning of the hard mask layer (e.g., such as by using an appropriate etchant, solvent, or ashing process). In some embodiments, the openings in the patterned mask layer 607 which expose the N-type SRAM device 301N and the N-type SOC logic device 303N may be formed using a high-grade photomask and a lithography system with high resolution, as discussed above. Whether or not a hard mask layer is used, and after exposure of the N-type SRAM device 301N and the N-type SOC logic device 303N, the N-type source/drain features 602, 604 may be formed. After formation of the N-type source/drain features 602, 604, the patterned mask layer 607 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
In some embodiments, the source/drain features 602, 604 are formed by epitaxially growing a semiconductor material layer in the source/drain regions 318. By way of example, the semiconductor material layer grown to form the source/drain features 602, 604 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain features 602, 604 may be formed by one or more epitaxial (epi) processes. In some embodiments, the source/drain features 602, 604 may be in-situ doped during the epi process. For example, in some embodiments, the source/drain features 602, 604 are doped with an N-type dopant species such as phosphorous, arsenic, antimony, or other suitable dopant species such as carbon. In some examples, the source/drain features 602, 604 may include SiC or Si doped with phosphorous. In some embodiments, the source/drain features 602, 604 are not in-situ doped, and instead an implantation process is performed to dope the source/drain features 602, 604. In various examples, and after formation of the source/drain features 602, 604, an annealing process may be performed (e.g., such as a rapid thermal anneal, laser anneal, or other suitable annealing process). It is noted that in some embodiments, the source/drain features 602, 604 may be epitaxially grown such that they extend above a top surface of their respective fins 302N, 304N, being referred to as raised source/drain features. In accordance with the embodiments disclosed herein, the N-type source/drain features 602, 604 are thus effectively co-optimized for the N-type SRAM device 301N and the N-type SOC logic device 303N.
The method 200 proceeds to block 210 where a first photo/etch process for P-type S/D regions is performed. Referring to the example of
As shown in
The method 200 proceeds to block 212 where a second photo/etch process for P-type S/D regions is performed. Referring to the example of
As shown in
The method 200 then proceeds to block 214 where P-type source/drain features are formed. Referring to
In some examples, prior to forming the P-type source/drain features 902, 904, a mask layer may be deposited and patterned to form a patterned mask layer 907 having openings which expose the P-type SRAM device 301P and the P-type SOC logic device 303P, while the N-type SRAM device 301N and the N-type SOC logic device 303N remain protected by the patterned mask layer 907. In some embodiments, the mask layer includes a resist layer and/or a hard mask layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other appropriate hard mask layer) such that the patterned mask layer 907 may include a patterned resist layer and/or a patterned hard mask layer. If only a resist layer is used, the deposited resist layer may be patterned (e.g., by exposure and development of the resist layer) to form the patterned mask layer 907. Alternatively, if a hard mask layer is used, a pattern may be initially formed in the resist layer (e.g., by exposure and development), after which the pattern may be transferred to an underlying hard mask layer (e.g., by etching) to form the patterned mask layer 907. In some cases, any remaining portion of the resist layer may be removed after patterning of the hard mask layer (e.g., such as by using an appropriate etchant, solvent, or ashing process). In some embodiments, the openings in the patterned mask layer 907 which expose the P-type SRAM device 301P and the P-type SOC logic device 303P may be formed using a high-grade photomask and a lithography system with high resolution, as discussed above. Whether or not a hard mask layer is used, and after exposure of the P-type SRAM device 301P and the P-type SOC logic device 303P, the P-type source/drain features 902, 904 may be formed. After formation of the P-type source/drain features 902, 904, the patterned mask layer 907 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
In some embodiments, the source/drain features 902, 904 are formed by epitaxially growing a semiconductor material layer in the source/drain regions 318. In various embodiments, the semiconductor material layer grown to form the source/drain features 902, 904 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain features 902, 904 may be formed by one or more epitaxial (epi) processes. In some embodiments, the source/drain features 902, 904 may be in-situ doped during the epi process. For example, in some embodiments, the source/drain features 902, 904 are doped with a P-type dopant species such as boron, BF2, or other suitable dopant species such as carbon. In some examples, the source/drain features 902, 904 may include SiGe or Si doped with boron. In some embodiments, the source/drain features 902, 904 are not in-situ doped, and instead an implantation process is performed to dope the source/drain features 902, 904. In various examples, and after formation of the source/drain features 902, 904, an annealing process may be performed (e.g., such as a rapid thermal anneal, laser anneal, or other suitable annealing process). It is noted that in some embodiments, the source/drain features 902, 904 may be epitaxially grown such that they extend above a top surface of their respective fins 302P, 304P, being referred to as raised source/drain features. In accordance with the embodiments disclosed herein, the P-type source/drain features 902, 904 are thus effectively co-optimized for the P-type SRAM device 301P and the P-type SOC logic device 303P.
For purposes of illustration and with reference to
The method 200 then proceeds to block 216 where further processing is performed. For example, after formation of the P-type source/drain features and removal of the patterned mask layer 907 (block 214), a contact etch stop layer (CESL) and an inter-layer dielectric (ILD) layer are formed over the device 300 and a chemical mechanical polishing (CMP) process is performed. In some embodiments, the CMP process may expose a top surface of the gate stacks 316 (e.g., by removing portions of the ILD layer and CESL) overlying the gate stacks 316 and planarize a top surface of the device 300. In addition, the CMP process may remove any hard mask layers overlying the gate stacks 316, if any, to expose the underlying electrode layer of the gate stacks 316, such as a polysilicon electrode layer. In a further embodiment of block 216, the exposed electrode layer of the gate stacks 316 may initially be removed by suitable etching processes, followed by an etching process to remove the dielectric layer of the gate stacks 316 within each of the regions 302A, 302B. In some examples, the etching processes may include a wet etch, a dry etch, or a combination thereof.
After removal of the dummy gates (e.g., the gate stacks 316), and in a further embodiment of block 216, a gate structure is formed over the N-type and P-type devices within each of the regions 302A, 302B. The gate structure may include a high-K/metal gate stack, however other compositions are possible. In some embodiments, the gate structure may form the gate associated with each of the N-type and P-type SRAM devices 301N, 301P and the N-type and P-type SOC logic devices 303N, 303P. In some embodiments, the gate structure includes an interfacial layer (IL) (e.g., such as silicon oxide (SiO2), HfSiO, or silicon oxynitride) and a high-K dielectric layer formed over the IL. In some embodiments, the high-K dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-K dielectric layer may include TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, Al0, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. In various embodiments, the IL and the high-K dielectric layer collectively define a gate dielectric of the gate structure.
In a further embodiment of block 216, a metal gate including a metal layer is formed over the gate dielectric (e.g., over the IL and the high-K dielectric layer). The metal layer may include a metal, metal alloy, or metal silicide. In various examples, the metal layer may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. Additionally, the formation of the gate dielectric/metal gate stack may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials and thereby planarize a top surface of the device 300.
Generally, the semiconductor device 300 may undergo further processing to form various features and regions known in the art. For example, further processing may form various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices (e.g., FinFET devices). In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method 200, and some process steps described above may be modified, replaced, or eliminated in accordance with various embodiments of the method 200.
For example, while the method 200 has been described as first forming the N-type source/drain regions and then the P-type source/drain regions, it will be understood that is some cases the P-type source/drain regions may be formed before the N-type source/drain regions. Further, while the method 200 was described as performed using a two-step photo/etch process (2P2E) for each of an N-type S/D and a P-type S/D for the various device types (e.g., the SRAM and SOC logic devices), other embodiments are possible. For instance, instead of performing first and second photo/etch processes for N-type source/drain regions (blocks 204, 206 of the method 200) and first and second photo/etch processes for P-type source/drain regions (blocks 210, 212 of the method 200), some embodiments may include performing first and second photo/etch processes for only one of the N-type source/drain regions or the P-type source/drain regions, and performing a single photo/etch process for the other of the N-type source/drain regions or the P-type source/drain regions. As a result, in some cases, only one of the N-type source/drain regions or the P-type source/drain regions for the various device types (e.g., the SRAM and SOC logic devices) may have different depths.
For instance, a single photo/etch process (1P1E) can be used to simultaneously form source/drain recesses in source/drain regions of each of the various N-type devices (e.g., the N-type SRAM and SOC logic devices) within which N-type source/drain features are subsequently formed, while a two-step photo/etch process (2P2E) is used for the P-type S/D for the various device types (e.g., the P-type SRAM and SOC logic devices) as described above with reference to blocks 210, 212 of the method 200. In this example, only the P-type source/drain regions of the various device types (e.g., the SRAM and SOC logic devices) may have different depths, while the N-type source/drain regions have substantially the same depth. Alternatively, a single photo/etch process (1P1E) can be used to simultaneously form source/drain recesses in source/drain regions of each of the various P-type devices (e.g., the P-type SRAM and SOC logic devices) within which P-type source/drain features are subsequently formed, while a two-step photo/etch process (2P2E) is used for the N-type S/D for the various device types (e.g., the N-type SRAM and SOC logic devices) as described above with reference to blocks 204, 206 of the method 200. In this example, only the N-type source/drain regions of the various device types (e.g., the SRAM and SOC logic devices) may have different depths, while the P-type source/drain regions have substantially the same depth. While various exemplary modifications to the method 200 have been discussed, it will be understood that the above examples are merely illustrative and not meant to be limiting. Those of skill in the art, having the benefit of the present disclosure, will understand that yet other embodiments and/or modifications are possible, without departing from the scope of this disclosure.
Referring now to
The method 1100 begins at block 1102 where a substrate including a partially fabricated device is provided. Referring to the example of
As in the device 300 discussed above, each of the N-type and P-type SRAM devices 301N, 301P, and the N-type and P-type SOC logic devices 303N, 303P of the device 1200 may be formed within different regions 302A, 302B of the same substrate, such as a silicon substrate or other appropriate substrate, as previously described. The N-type and P-type SRAM devices 301N, 301P include fins 302N, 302P and the N-type and P-type SOC logic devices 303N, 303P include fins 304N, 304P. In various embodiments, the fins 302N, 302P, 304N, 304P may be formed of the same material or a different material as the underlying substrate from which they extend. In addition, STI features may also be formed to isolate each of the fins 302N, 302P, 304N, 304P from neighboring fins. Also, as described above, the number of fins used to form each of the N-type and P-type SRAM devices 301N, 301P, and the N-type and P-type SOC logic devices 303N, 303P, within each of the regions 302A, 302B, may vary.
Each of the N-type and P-type SRAM devices 301N, 301P, and the N-type and P-type SOC logic devices 303N, 303P also include gate stacks 316 formed over respective fins 302N, 302P, 304N, 304P within each of the regions 302A, 302B. The gate stacks 316 may be dummy (sacrificial) gate stacks that are subsequently removed and replaced by a final gate stack at a subsequent processing stage. The gate stacks 316 also define source/drain regions 318 of the fins 302N, 302P, 304N, 304P, for example, which includes the regions of the fins 302N, 302P, 304N, 304P adjacent to the gate stacks 316 and on opposing sides of the channel region. In various embodiments, the gate stacks 316 include a dielectric layer and an electrode layer formed over the dielectric layer, as previously discussed, and one or more spacer layers 320 may be formed on sidewalls of the gate stacks 316. In some cases, after the block 1102, a portion of the one or more spacer layers 320 may remain disposed between the gate stacks 316, over the source/drain regions 318, during a subsequent ion implantation process (block 1104). Alternatively, in some embodiments, a dielectric layer may be separately formed between the gate stacks 316, over the source/drain regions 318, prior to the subsequent ion implantation process.
The method 1100 proceeds to block 1104 where an ion implantation process is performed into a logic device region. Referring to the example of
Whether or not a hard mask layer is used, and after exposure of the N-type SOC logic device 303N and the P-type SOC logic device 303P, an ion implantation process is performed to introduce a dopant species into the source/drain regions 318 of the N-type SOC logic device 303N and the P-type SOC logic device 303P. The dopant species is introduced into the source/drain regions 318 but not into the channels (portions of the fins underlying the gate stacks 316) since the channels remain covered by the gate stacks 316. In some embodiments, the dopant species includes at least one of carbon (C), silicon (Si), germanium (Ge), hydrogen (H), nitrogen (N), fluorine (F), argon (Ar), and a combination thereof. Alternatively, or additionally, the dopant species includes at least one of gallium (Ga), phosphorous (P), arsenic (As), and a combination thereof. In some cases, the implantation process is performed at an angle that is substantially perpendicular to the substrate (e.g., at a tilt angle of about zero degrees), although other implant angles are possible. In some embodiments, the ion implantation process is performed through the portion of the one or more spacer layers 320 or the separately formed dielectric layer, if present, between the gate stacks 316 and over the source/drain regions 318. The purpose of implanting the dopant species into the source/drain regions 318 is to modify the etch rate of the source/drain regions 318 during a subsequent etching process to recess the source/drain regions 318. In the present example, the etch rate of the implanted source/drain regions 318 of the N-type SOC logic device 303N and the P-type SOC logic device 303P is increased. In some cases, the increased etch rate is due to damage to the source/drain regions 318 caused by the implanted dopant ions, which cause structural changes (e.g., such as defect formation) and accordingly increase the etch rate of the implanted regions. In some embodiments, the doping concentration of the implanted dopant species ranges between 1×1019 and 1×1022 (cm3). The corresponding implantation dose ranges between 1×1014 and 1×1016 (cm2). In addition, the ion implantation process includes a bias power ranging between 1K eV and 4K eV to provide the intended damage and etch rate variation. After performing the ion implantation process, the patterned mask layer 1307 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
The method 1100 proceeds to block 1106 where a photo/etch process for N-type S/D regions is performed. Referring to the example of
Whether or not a hard mask layer is used, and after exposure of the N-type SRAM device 301N and the N-type SOC logic device 303N, an etching process (e.g., wet etch, dry etch, or combination thereof) is performed to remove portions of the fins 302N, 304N in the source/drain region 318 of the N-type SRAM device 301N and the N-type SOC logic device 303N to form the source/drain recesses 402, 502. In some embodiments, the source/drain etching process is a dry etch using an etchant that includes a chlorine-containing gas, a fluorine-containing gas or both, such as Cl2, CCl2F2, SF6, or a combination thereof. After formation of the source/drain recess 402, 502, the patterned mask layer 1407 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
As shown in
The method 1100 then proceeds to block 1108 where N-type source/drain features are formed. Referring to
In some examples, prior to forming the N-type source/drain features 602, 604, a mask layer may be deposited and patterned to form a patterned mask layer 1507 having openings which expose the N-type SRAM device 301N and the N-type SOC logic device 303N, while the P-type SRAM device 301P and the P-type SOC logic device 303P remain protected by the patterned mask layer 1507. In some embodiments, the mask layer includes a resist layer and/or a hard mask layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other appropriate hard mask layer) such that the patterned mask layer 1507 may include a patterned resist layer and/or a patterned hard mask layer, as described above. In some embodiments, the openings in the patterned mask layer 1507 which expose the N-type SRAM device 301N and the N-type SOC logic device 303N may be formed using a high-grade photomask and a lithography system with high resolution, as discussed above. Whether or not a hard mask layer is used, and after exposure of the N-type SRAM device 301N and the N-type SOC logic device 303N, the N-type source/drain features 602, 604 may be formed. After formation of the N-type source/drain features 602, 604, the patterned mask layer 1507 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process). In various embodiments, the source/drain features 602, 604 are epitaxially grown and may be substantially the same as described above with reference to block 208 of the method 200. In some cases, the source/drain features 602, 604 may also extend above a top surface of their respective fins 302N, 304N, being referred to as raised source/drain features. In accordance with the embodiments disclosed herein, the N-type source/drain features 602, 604 are thus effectively co-optimized for the N-type SRAM device 301N and the N-type SOC logic device 303N.
The method 1100 proceeds to block 1110 where a photo/etch process for P-type S/D regions is performed. Referring to the example of
As shown in
The method 1100 then proceeds to block 1112 where P-type source/drain features are formed. Referring to
In some examples, prior to forming the P-type source/drain features 902, 904, a mask layer may be deposited and patterned to form a patterned mask layer 1707 having openings which expose the P-type SRAM device 301P and the P-type SOC logic device 303P, while the N-type SRAM device 301N and the N-type SOC logic device 303N remain protected by the patterned mask layer 1707. In some embodiments, the mask layer includes a resist layer and/or a hard mask layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other appropriate hard mask layer) such that the patterned mask layer 1707 may include a patterned resist layer and/or a patterned hard mask layer, as described above. In some embodiments, the openings in the patterned mask layer 1707 which expose the P-type SRAM device 301P and the P-type SOC logic device 303P may be formed using a high-grade photomask and a lithography system with high resolution, as discussed above. Whether or not a hard mask layer is used, and after exposure of the P-type SRAM device 301P and the P-type SOC logic device 303P, the P-type source/drain features 902, 904 may be formed. After formation of the P-type source/drain features 902, 904, the patterned mask layer 1707 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process). In various embodiments, the source/drain features 902, 904 are epitaxially grown and may be substantially the same as described above with reference to block 214 of the method 200. In some cases, the source/drain features 902, 904 may also extend above a top surface of their respective fins 302P, 304P, being referred to as raised source/drain features. In accordance with the embodiments disclosed herein, the P-type source/drain features 902, 904 are thus effectively co-optimized for the P-type SRAM device 301P and the P-type SOC logic device 303P.
The method 1100 then proceeds to block 1114 where further processing is performed, as described above. This may include, for example, formation of a CESL and an ILD layer over the device 1200, followed by a CMP process. The further processing of block 1114 further includes removal of the dummy gates (e.g., the gate stacks 316), and formation of a gate structure over the N-type and P-type devices within each of the regions 302A, 302B. The gate structure may include a high-K/metal gate stack, as discussed above, however other compositions are possible. In various embodiments, the gate structure may form the gate associated with each of the N-type and P-type SRAM devices 301N, 301P and the N-type and P-type SOC logic devices 303N, 303P.
Generally, the semiconductor device 1200 may undergo further processing to form various features and regions known in the art. For example, further processing may form various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices (e.g., FinFET devices). In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method 1100, and some process steps described above may be modified, replaced, or eliminated in accordance with various embodiments of the method 1100.
For example, while the method 1100 has been described as first forming the N-type source/drain regions and then the P-type source/drain regions, it will be understood that is some cases the P-type source/drain regions may be formed before the N-type source/drain regions. Further, while the method 1100 was described as performing an ion implantation process into the source/drain regions 318 of both the N-type SOC logic device 303N and the P-type SOC logic device 303P, other embodiments are possible. For instance, in some embodiments, the ion implantation process may be performed into only one of the source/drain regions 318 of the N-type SOC logic device 303N and the P-type SOC logic device 303P. As a result, the etch rate of the source/drain regions 318 of only one of the N-type SOC logic device 303N and the P-type SOC logic device 303P will be increased. Thus, in this example, only one of the N-type source/drain regions or the P-type source/drain regions for the various device types (e.g., the SRAM and SOC logic devices) may have different depths.
In another embodiment, the ion implantation process of block 1104 may be modified such that the implantation process is performed multiple times, where at least one of the implantations is performed at a non-zero-degree tilt angle. This example is described below with reference to
Referring to the
Referring to the
While various exemplary modifications to the method 1100 have been discussed, it will be understood that the above examples are merely illustrative and not meant to be limiting. Those of skill in the art, having the benefit of the present disclosure, will understand that yet other embodiments and/or modifications are possible, without departing from the scope of this disclosure.
Referring now to
An embodiment of the block 1804 of the method 1800 is described below with reference to
Whether or not a hard mask layer is used, and after exposure of the N-type SRAM device 301N and the P-type SRAM device 301P, an ion implantation process is performed to introduce a dopant species into the source/drain regions 318 of the N-type SRAM device 301N and the P-type SRAM device 301P. The dopant species is introduced into the source/drain regions 318 but not into the channels (portions of the fins underlying the gate stacks 316) since the channels remain covered by the gate stacks 316. In some embodiments, the dopant species includes at least one of boron (B), boron sulfide (BS2), difluoroboron (BF2), boron trifluoride (BF3), and a combination thereof. In some cases, the implantation process is performed at an angle that is substantially perpendicular to the substrate (e.g., at a tilt angle of about zero degrees), although other implant angles are possible. In some embodiments, the ion implantation process is performed through the portion of the one or more spacer layers 320 or the separately formed dielectric layer, if present, between the gate stacks 316 and over the source/drain regions 318. The purpose of implanting the dopant species into the source/drain regions 318 is to modify the etch rate of the source/drain regions 318 during a subsequent etching process to recess the source/drain regions 318 (blocks 1106 and 1110). In the present example, the etch rate of the implanted source/drain regions 318 of the N-type SRAM device 301N and the P-type SRAM device 301P is decreased. In some cases, the decreased etch rate is due to a chemical reaction that occurs between the implanted dopant species and the etchant used to recess the source/drain regions 318 (blocks 1106 and 1110), thereby decreasing the etch rate of the implanted regions. In some embodiments, the doping concentration of the implanted dopant species ranges between 1×1019 and 1×1022 (cm3). The corresponding implantation dose ranges between 1×1014 and 1×1016 (cm2). In addition, the ion implantation process includes a bias power ranging between 1K eV and 4K eV to provide the intended etch rate variation. After performing the ion implantation process, the patterned mask layer 1907 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
Due to the ion implantation process, and the associated decreased etch rate of the source/drain region 318 of the N-type SRAM device 301N, the depth D1 of the source/drain recess 402 of the N-type SRAM device 301N will be less than (shallower than) the depth D2 of the source/drain recess 502 of the N-type SOC logic device 303N, thereby providing tighter control of SCEs for the N-type SRAM device 301N and higher current/performance for the N-type SOC logic device 303N. Similarly, due to the ion implantation process, and the associated decreased etch rate of the source/drain region 318 of the P-type SRAM device 301P, the depth D1 of the source/drain recess 702 of the P-type SRAM device 301P will be less than (shallower than) the depth D2 of the source/drain recess 802 of the P-type SOC logic device 303P, thereby providing tighter control of SCEs for the P-type SRAM device 301P and higher current/performance for the P-type SOC logic device 303P.
It is also noted that while the method 1800 was described as performing an ion implantation process into the source/drain regions 318 of both the N-type SRAM device 301N and the P-type SRAM device 301P, other embodiments are possible. For instance, in some embodiments, the ion implantation process may be performed into only one of the source/drain regions 318 of the N-type SRAM device 301N and the P-type SRAM device 301P. As a result, the etch rate of the source/drain regions 318 of only one of the N-type SRAM device 301N and the P-type SRAM device 301P will be decreased. Thus, in this example, only one of the N-type source/drain regions or the P-type source/drain regions for the various device types (e.g., the SRAM and SOC logic devices) may have different depths. While some exemplary modifications to the method 1800 have been discussed, it will be understood that these examples are merely illustrative and not meant to be limiting. Those of skill in the art, having the benefit of the present disclosure, will understand that yet other embodiments and/or modifications are possible, without departing from the scope of this disclosure.
Referring now to
An embodiment of the block 2504 of the method 2500 is described below with reference to
For purposes of illustration,
Whether or not a hard mask layer is used, and after exposure of the P-type SRAM device 301P, and the N-type and P-type SOC logic devices 303N, 303P, an ion implantation process is performed to introduce a dopant species into the source/drain regions 318 of the P-type SRAM device 301P, and the N-type and P-type SOC logic devices 303N, 303P. The dopant species is introduced into the source/drain regions 318 but not into the channels (portions of the fins underlying the gate stacks 316) since the channels remain covered by the gate stacks 316. In some embodiments, the dopant species includes at least one of carbon (C), silicon (Si), germanium (Ge), hydrogen (H), nitrogen (N), fluorine (F), argon (Ar), and a combination thereof. Alternatively, or additionally, the dopant species includes at least one of gallium (Ga), phosphorous (P), arsenic (As), and a combination thereof. In some cases, the implantation process is performed at an angle that is substantially perpendicular to the substrate (e.g., at a tilt angle of about zero degrees), although other implant angles are possible. In some embodiments, the ion implantation process is performed through the portion of the one or more spacer layers 320 or the separately formed dielectric layer, if present, between the gate stacks 316 and over the source/drain regions 318. The purpose of implanting the dopant species into the source/drain regions 318 is to modify the etch rate of the source/drain regions 318 during a subsequent etching process to recess the source/drain regions 318 (blocks 1106 and 1110). In the present example, the etch rate of the implanted source/drain regions 318 of the P-type SRAM device 301P, and the N-type and P-type SOC logic devices 303N, 303P is increased. In some cases, the increased etch rate is due to damage to the source/drain regions 318 caused by the implanted dopant ions, which cause structural changes (e.g., such as defect formation) and accordingly increase the etch rate of the implanted regions. In some embodiments, the doping concentration of the implanted dopant species ranges between 1×1019 and 1×1022 (cm3). The corresponding implantation dose ranges between 1×1014 and 1×1016 (cm2). In addition, the ion implantation process includes a bias power ranging between 1K eV and 4K eV to provide the intended damage and etch rate variation. After performing the ion implantation process, the patterned mask layer 2607 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
Due to the ion implantation process, and the associated increased etch rate of the source/drain region 318 of the P-type SRAM device 301P, and the N-type and P-type SOC logic devices 303N, 303P, each of the source/drain recesses 502 (of the N-type SOC logic device 303N), 702 (of the P-type SRAM device 301P), and 802 (of the P-type SOC logic device 303P) is etched to the deeper depth D2, described above. Thus, the depth D2 of the source/drain recesses 502, 702, 802 of the P-type SRAM device 301P, and the N-type and P-type SOC logic devices 303N, 303P will be greater than (deeper than) the depth D1 of the source/drain recess 402 of the N-type SRAM device 301N. By way of example,
It is also noted that while the method 2500 was described as implanting a dopant species into the P-type SRAM device 301P (and not the N-type SRAM device 301N), in some cases a dopant species may instead by implanted into the N-type SRAM device 301N (and not the P-type SRAM device 301P). In such an example, only the P-type devices (P-type SRAM device 301P, P-type SOC logic device 303P) will have different depths D1, D2 of the source/drain features 902, 904, respectively, while the N-type devices (N-type SRAM device 301N, N-type SOC logic device 303N) have the same depth D2 of the source/drain features 602, 604. Thus, in this example, the N-type SRAM device 301N would also have the same depth D2 as both of the N-type SOC logic device 303N and the P-type SOC logic device 303P. While some exemplary modifications to the method 2500 have been discussed, it will be understood that these examples are merely illustrative and not meant to be limiting. Those of skill in the art, having the benefit of the present disclosure, will understand that yet other embodiments and/or modifications are possible, without departing from the scope of this disclosure.
With reference to
An embodiment of the block 2904 of the method 2900 is described below with reference to
For purposes of illustration,
Whether or not a hard mask layer is used, and after exposure of the N-type and P-type SRAM-HC devices 301N-2, 301P-2 and the N-type and P-type SOC logic devices 303N, 303P, an ion implantation process is performed to introduce a dopant species into the source/drain regions 318 of the N-type and P-type SRAM-HC devices 301N-2, 301P-2 and the N-type and P-type SOC logic devices 303N, 303P. The dopant species is introduced into the source/drain regions 318 but not into the channels (portions of the fins underlying the gate stacks 316) since the channels remain covered by the gate stacks 316. In some embodiments, the dopant species includes at least one of carbon (C), silicon (Si), germanium (Ge), hydrogen (H), nitrogen (N), fluorine (F), argon (Ar), and a combination thereof. Alternatively, or additionally, the dopant species includes at least one of gallium (Ga), phosphorous (P), arsenic (As), and a combination thereof. In some cases, the implantation process is performed at an angle that is substantially perpendicular to the substrate (e.g., at a tilt angle of about zero degrees), although other implant angles are possible. In some embodiments, the ion implantation process is performed through the portion of the one or more spacer layers 320 or the separately formed dielectric layer, if present, between the gate stacks 316 and over the source/drain regions 318. The purpose of implanting the dopant species into the source/drain regions 318 is to modify the etch rate of the source/drain regions 318 during a subsequent etching process to recess the source/drain regions 318 (blocks 1106 and 1110). In the present example, the etch rate of the implanted source/drain regions 318 of the N-type and P-type SRAM-HC devices 301N-2, 301P-2 and the N-type and P-type SOC logic devices 303N, 303P is increased. In some cases, the increased etch rate is due to damage to the source/drain regions 318 caused by the implanted dopant ions, which cause structural changes (e.g., such as defect formation) and accordingly increase the etch rate of the implanted regions. In some embodiments, the doping concentration of the implanted dopant species ranges between 1×1019 and 1×1022 (cm3). The corresponding implantation dose ranges between 1×1014 and 1×1016 (cm2). In addition, the ion implantation process includes a bias power ranging between 1K eV and 4K eV to provide the intended damage and etch rate variation. After performing the ion implantation process, the patterned mask layer 3007 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
Due to the ion implantation process, and the associated increased etch rate of the source/drain region 318 of the N-type and P-type SRAM-HC devices 301N-2, 301P-2 and the N-type and P-type SOC logic devices 303N, 303P, each of the source/drain recesses of the N-type and P-type SRAM-HC devices 301N-2, 301P-2 and the N-type and P-type SOC logic devices 303N, 303P is etched to the deeper depth D2, described above. Thus, the depth D2 of the source/drain recesses of the N-type and P-type SRAM-HC devices 301N-2, 301P-2 and the N-type and P-type SOC logic devices 303N, 303P will be greater than (deeper than) the depth D1 of the source/drain recesses of the N-type and P-type SRAM-HD devices 301N-1, 301P-1. By way of example,
It is also noted that in some cases, the source/drain features 602-2 formed on adjacent fins 302N-2 of the N-type SRAM-HC device 301N-2 may merge together (e.g., during epitaxial growth), similar to the example discussed above with reference to
Referring to
An embodiment of the block 3304 of the method 3300 is described below with reference to
For purposes of illustration,
Whether or not a hard mask layer is used, and after exposure of the second N-type SRAM-HC device 301HC-N2 and the N-type and P-type SOC logic devices 303N, 303P, an ion implantation process is performed to introduce a dopant species into the source/drain regions 318 of the second N-type SRAM-HC device 301HC-N2 and the N-type and P-type SOC logic devices 303N, 303P. The dopant species is introduced into the source/drain regions 318 but not into the channels (portions of the fins underlying the gate stacks 316) since the channels remain covered by the gate stacks 316. In some embodiments, the dopant species includes at least one of carbon (C), silicon (Si), germanium (Ge), hydrogen (H), nitrogen (N), fluorine (F), argon (Ar), and a combination thereof. Alternatively, or additionally, the dopant species includes at least one of gallium (Ga), phosphorous (P), arsenic (As), and a combination thereof. In some cases, the implantation process is performed at an angle that is substantially perpendicular to the substrate (e.g., at a tilt angle of about zero degrees), although other implant angles are possible. In some embodiments, the ion implantation process is performed through the portion of the one or more spacer layers 320 or the separately formed dielectric layer, if present, between the gate stacks 316 and over the source/drain regions 318. The purpose of implanting the dopant species into the source/drain regions 318 is to modify the etch rate of the source/drain regions 318 during a subsequent etching process to recess the source/drain regions 318 (blocks 1106 and 1110). In the present example, the etch rate of the implanted source/drain regions 318 of the second N-type SRAM-HC device 301HC-N2 and the N-type and P-type SOC logic devices 303N, 303P is increased. In some cases, the increased etch rate is due to damage to the source/drain regions 318 caused by the implanted dopant ions, which cause structural changes (e.g., such as defect formation) and accordingly increase the etch rate of the implanted regions. In some embodiments, the doping concentration of the implanted dopant species ranges between 1×1019 and 1×1022 (cm3). The corresponding implantation dose ranges between 1×1014 and 1×1016 (cm2). In addition, the ion implantation process includes a bias power ranging between 1K eV and 4K eV to provide the intended damage and etch rate variation. After performing the ion implantation process, the patterned mask layer 3407 is removed (e.g., such as by using an appropriate etchant, solvent, or ashing process).
Due to the ion implantation process, and the associated increased etch rate of the source/drain region 318 of the second N-type SRAM-HC device 301HC-N2 and the N-type and P-type SOC logic devices 303N, 303P, each of the source/drain recesses of the second N-type SRAM-HC device 301HC-N2 and the N-type and P-type SOC logic devices 303N, 303P is etched to the deeper depth D2, described above. Thus, the depth D2 of the source/drain recesses of the second N-type SRAM-HC device 301HC-N2 and the N-type and P-type SOC logic devices 303N, 303P will be greater than (deeper than) the depth D1 of the source/drain recesses of the first N-type SRAM-HC device 301HC-N1 and the P-type SRAM-HC device 301HC-P. By way of example,
It is also noted that in various embodiments, one or both of the source/drain features 602HC-N1 formed on adjacent fins 302HC-N1 of the first N-type SRAM-HC device 301HC-N1 and the source/drain features 602HC-N2 formed on adjacent fins 302HC-N2 of the second N-type SRAM-HC device 301HC-N2 may merge together (e.g., during epitaxial growth), similar to the example discussed above with reference to
Thus, the various embodiments described herein offer several advantages over the existing art. It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments, and other embodiments may offer different advantages. For example, embodiments discussed herein include structures and methods for the co-optimization of SOC logic devices and SRAM devices. In various embodiments, a semiconductor device may include individual device structures to simultaneously meet the performance and design requirements of each of the SOC logic devices and SRAM devices. As an example, and in accordance with the disclosed embodiments, intentionally different source/drain depths for logic devices (e.g., SOC logic devices) and SRAM devices are provided. In some embodiments, the source/drain depth for SRAM devices may be shallower than the source/drain depth for SOC logic devices, for example, to provide tighter control of SCEs. In some embodiments, formation of the intentionally different source/drain depths may be accomplished by (i) a 2-step or multi-step S/D recess process using a high-grade photomask (e.g., such as EUV), or by (ii) an implantation-enhanced S/D recess process using at least one low-grade photomask. The implantation-enhanced S/D recess process may be accomplished at a reduced cost using simplified lithography, for example, as compared to the 2-step or multi-step S/D recess process. After the S/D recess process, an epitaxial S/D growth process is performed (e.g., in N-type and P-type regions of both SOC logic devices and SRAM devices) to form respective epitaxial S/D features having different source/drain depths. Regardless of the approach used, embodiments of the present disclosure provide independent optimization of S/D depth for N-type and P-type SOC logic device and SRAM devices. Additional embodiments and advantages are discussed below and/or will be evident to those skilled in the art in possession of this disclosure.
Thus, one of the embodiments of the present disclosure described a method that includes performing an ion implantation process into a first device region of a substrate. In some embodiments, the method further includes performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in the first device region and a second source/drain recess for a second device in a second device region different than the first device region. In various examples, a first depth of the first source/drain recess is greater than a second depth of the second source/drain recess.
In another of the embodiments, discussed is a method that includes performing an ion implantation process into a memory device region or a logic device region to modify an etch rate of one of a first source/drain region within the memory device region or a second source/drain region within the logic device region. In some embodiments, the method further includes simultaneously etching the first source/drain region to form a first source/drain recess for a first memory device and the second source/drain region to form a second source/drain recess for a first logic device. In some examples, the method further includes forming a first source/drain feature within the first source/drain recess and a second source/drain feature within the second source/drain recess. In various embodiments, a first depth of the first source/drain feature is different than a second depth of the second source/drain feature.
In yet another of the embodiments, discussed is a semiconductor device having a substrate including a first device region and a second device region. In some embodiments, the semiconductor device further includes a first gate structure disposed in the first device region and a second gate structure disposed in the second device region. In some examples, the semiconductor device further includes a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure. In some cases, a first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level. In some embodiments, a first bottom surface of the first source/drain feature is a first distance away from the first top surface, and a second bottom surface of the second source/drain feature is a second distance away from the second top surface. In some cases, the second distance is greater than the first distance.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/362,498, filed Apr. 5, 2022, the entirety of which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 63362498 | Apr 2022 | US |
