Patent Application
20060188659
This invention relates to stacked memory cell manufacture and, in particular, to metal-based filling of interconnect features of stacked memory cells such as vias, trenches, contact openings, and through-holes.
Memory circuits such as dynamic random access memory (DRAM) devices are generally composed of memory cells where data are stored. Data are stored in capacitors, which hold data as an electrical charge. Memory cells are typically arranged in an array.
DRAM devices typically come in two types, trenched capacitor type and stacked capacitor type. Trench type cells are manufactured by forming the capacitor in the side wall of a trench formed in a semiconductor substrate. Stacked capacitor type cells, on the other hand, are manufactured by stacking electrode layers above the substrate to form the capacitor. Stacked capacitors stand high to achieve sufficient storage of charge. As device geometries miniaturize, contact aspect ratios, i.e., the ratio of via contact depth to via contact diameter, have increased as a result of increasing stacked capacitor height. Stacked capacitor cells are also known to those skilled in the art as stacked memory cells or devices.
Stacked memory applications typically do not require the level of electrical conductivity of logic operations, i.e., integrated circuits. Therefore, less electrically conductive plug metallization may be used for filling stacked memory vias instead of a more conductive material, such as Cu. Tungsten is an exemplary plug metallization because its electrical conductivity, while not as great as that of Cu, is sufficient for memory applications. Further, because of its refractory nature, W does not diffuse into the Si wafer or low k dielectric layer. Therefore, a diffusion-preventing barrier layer between the Si or dielectric material and the W metallization is not necessary.
Tungsten metal-filling into vias and trenches has been achieved by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In general, metal filling by blanket vapor deposition is expensive and time-consuming, as it involves multiple processing steps. The metal deposited overburdens the interconnect feature and therefore needs to be patterned and etched, followed by resist removal. Some degree of misalignment is expected with lithographic patterning. Further, vapor deposition may fill metal into and pinch off the top of a high aspect ratio via or trench, resulting in voids within the stacked memory interconnect.
Removal of overburden may occur by chemical mechanical polishing (CMP). CMP is performed on a substrate following via formation to, for example, remove unwanted W overburden deposited during the deposition process and thereby planarize the surface. This CMP can cause traces of W to be embedded or smeared onto the dielectric material. These traces of W, if not removed, can contaminate the dielectric. An etchant is therefore employed in a pretreatment composition to either remove these traces of W, undercut the dielectric on which they reside, or both.
The use of Co as a plug metallization in stacked memory devices is an attractive alternative to the use of W. In stacked memory applications, Co performs better electrically than W. Also, Co is of a sufficient refractory nature to impede diffusion into the dielectric layer. Cobalt can be applied by methods other than CVD.
Catalyst-initiated electroless Co deposition has been discussed in, for example, U.S. Pat. No. 6,232,227. Metallization of high aspect ratio interconnect features by catalyst-initiated electroless Co deposition is disadvantageous in that Co begins to grow on every surface which contains the catalyst. Catalyst seeding, such as in palladium seeding, occurs non-selectively with respect to the Si or dielectric surface. Therefore, Pd seeds will occur on the bottom of the interconnect feature, as well as the side walls and the wafer surface. Application of the metal onto the diffusion layer surface located at the bottom of the via is difficult to achieve without collateral application of the metal to the side walls of the via and to the wafer surface. Thus, immersion of the wafer substrate into a Co solution results in growth of Co on the side walls of the via and on the wafer surface. This results in two disadvantages. First, Co must be removed from the surface of the device by a subsequent planarization or etching step. Second, Co growth on the side walls of the via can result in a pinching shut of the via, thereby creating voids in the interconnect structure.
Therefore, a process is needed which can fill high aspect ratio interconnect features in a stacked capacitor device which does not cause metallization to pinch off the feature opening and result in voids within the interconnect feature. Further, a process and composition are needed to selectively deposit Co metallization onto the bottom of a high aspect interconnect feature in a stacked capacitor device and fill in the feature from the bottom to the top, without collateral growth on the sides of the interconnect, or on surface of the device. Finally, a composition is needed which auto-catalyzes the deposition of conductive Co and Co alloys onto a source/drain region of a high aspect interconnect feature in a stacked memory device.
Briefly, therefore, the invention is directed a method for electrolessly filling a stacked memory cell interconnect feature, the method comprising contacting the stacked memory cell interconnect-feature with an electroless deposition composition comprising a source of Co ions and a reducing agent, wherein the stacked memory interconnect feature has an electrically conducting bottom and a height-to-width aspect ratio of at least about 2, whereby a portion of the Co ions are reduced to Co metal on the electrically conducting bottom, and bottom-up filling of the stacked memory interconnect feature is achieved by continued reduction of Co ions.
In another aspect, the invention is directed to an electroless deposition composition for electrolessly depositing Co in a high aspect ratio stacked memory cell interconnect feature. The composition comprises water, a source of Co ions, a complexing agent, a buffering agent, a borane-based reducing agent component, and a hypophosphite reducing agent component. The borane-based reducing agent component is selected from the group consisting of an alkali metal borohydride, dimethylamine borane, diethylamine borane, morpholine borane, and mixtures thereof. The hypophosphite reducing agent component is selected from the group consisting of an alkali metal hypophosphite, ammonium hypophosphite, hypophosphorous acid, and mixtures thereof. The borane-based reducing agent component concentration and the hypophosphite reducing agent component concentration are selected to yield a concentration ratio of borane-based reducing agent component concentration in g/L to hypophosphite reducing agent component concentration in g/L which is less than about 0.5.
According to the present invention, metallization is filled into an interconnect feature in a stacked memory device; for example, Co or an alloy thereof is filled into a high aspect ratio via or trench of a stacked memory cell. The interconnect feature includes a bottom, side walls, and a top opening. The height of the sides walls and diameter of the opening are such that the via has a high aspect ratio. As a general proposition, the ratio of the height of the walls to the diameter of the opening is greater than 5. In another embodiment, the aspect ratio is at least 10. In one such embodiment of the invention, the aspect ratio is at least about 18.
The bottom of via 14 is electrically conductive material in that it is a contact of, for example, W, layered W—WN, or layered WSi2-polysilicon. The bottom of via 24 is electrically conductive material in that it is a drain of, for example, doped Si. In other embodiments, the device drain is composed of TiN or Ru. The metal for filling the interconnect is Co-based, such as Co metal, or an alloy thereof, including, but not limited to Co—B—P, Co—W—B—P, Co—W—B, and Co—B. The electrically conductive material at the bottom of the vias 14 and 24 provides conductivity as required for bottom-up, electroless, self-initiated superfilling in accordance with the invention as described hereinbelow.
The interconnect filling involves initiation of deposition on the bottom of the interconnect, and then bottom-up filling from the bottom to the top of the interconnect. The filling is “bottom up” in that it occurs primarily in the direction from the bottom of the interconnect to the top, and there is no substantial side wall deposition. Filling is initiated by depositing the Co-based material by a borane-chemistry electroless deposition process employing an alkylamine borane compound such as dimethylamine borane (DMAB), diethylamine borane (DEAB), or morpholine borane as a reducing agent. These borane-based reducing agents render W catalytic to Co deposition. The process is therefore self-initiating on the W via bottom, so Co, Pd, or other seeding operation is excluded. This is in contrast to electroless processes based on non-borane chemistry, such as employing hypophosphite or other non-borane reducing agents, which do not render W catalytic to Co deposition. The non-borane processes, if used to deposit Co directly on a W via, require Co seeding or another activation mechanism. Other materials which are rendered catalytic by borane chemistry include Cu, Co, Pt, Mo, Au, and Pd, however, Au is preferably rendered catalytic with hydrazine.
A substantial advantage of selection of the foregoing materials is that Co-based growth is initiated from the bottom of the via. In performing the method of the invention, metallization fills from the bottom of the interconnect feature upwardly toward the opening. This filling method avoids both problems of collateral side deposition, which may pinch closed the opening of the via, and of surface deposition, which requires a planarization step, such as CMP.
Electroless plating baths for electroless plating of Co and alloys thereof in accordance with this invention comprise a source of deposition ions, a reducing agent, a complexing agent, and a surfactant. The bath is buffered within a certain pH range. Optionally, the bath may also comprise surfactants, a source of refractory ions, and stabilizers. The bath is formulated such that it self initiates onto the drain substrate material, such as W. Baths which self-initiate onto Cu substrates such as in capping applications may or may not self initiate Co deposition onto W. The baths also differ from Co capping applications in that it is critical to deposit an alloy with good conductivity—typically high Co, because the interconnect is intended to carry current; which is in contrast to Co deposition in capping applications.
For the deposition of a Co-based alloy, the bath comprises a source of Co ions, which are introduced into the solution as an inorganic Co salt such as chloride, sulfate, or other suitable inorganic salt, or a Co complex with an organic carboxylic acid such as Co acetate, citrate, lactate, succinate, propionate, hydroxyacetate, EDTA or others.
In one embodiment, the inorganic Co salt is Co(OH)2. The hydroxyl group has a lower molecular weight than the other anions in typical Co salts. The Co(OH)2 salt results in a simpler plating bath because hydroxyl ions are already present in an aqueous solution. Therefore, no additional anions, such as the halides, are introduced into the electroless bath, so the risk of contamination by such anions is avoided.
In one embodiment, the Co salt or complex is added to provide about 0.5 g/L to about 60 g/L of Co2+ to yield a Co-based alloy of high Co metal content.
A reducing agent is employed which is a borane-based reducing agent component alone or in combination with a hypophosphite reducing agent component. In CoB systems, where a borane-based reducing agent is used alone, the Co alloy has a higher Co content. However, when a combination of reducing agents is used, both the bath stability and the filling of the via or trench feature is improved. The reducing agent is discussed more fully below.
The bath further contains one or more complexing agents and buffering agents. The bath typically contains a pH buffer to stabilize the pH in the desired range. In one embodiment, the desired pH range is between about 7.5 and about 10.0. In one embodiment, it is between about 8.8 and about 10. These pH ranges provide a mildly alkaline electroplating bath. If the pH is not stabilized, unintentional, undesirable, and unanticipated changes in deposition rate and deposit chemistry can occur. Exemplary buffers include, for example, borates, tetra- and pentaborates, phosphates, acetates, glycolates, lactates, ammonia, and pyrophosphate. For basic pH adjustment, ammonium, TMAH, NaOH, KOH, or mixtures thereof are employed. Sulfuric, hydrochloric, and citric acids are used for acidic pH adjustment, with the acid selection made to correlate to the anion of the Co source. In one embodiment, the pH buffer level is on the order of between about 0 g/L and about 50 g/L.
A complexing agent is included in the bath to help keep the Co ions in solution and modify the plating potential of the bath needed for initiation of deposition. The complexing agents used in the bath are selected from among citric acid, malic acid, ethylenediamine, glycine, propionic, succinic, and lactic acids, diethylamine (DEA), tetraethylamine hydroxide (TEAH), and ammonium salts such as ammonium chloride, ammonium sulfate, ammonium hydroxide, pyrophosphate, and mixtures thereof. In one embodiment, the complexing agent concentration is selected such that the molar ratio between the complexing agent and Co is between about 2:1 and about 4:1, generally. In another embodiment, the ratio is about 9:1 to about 10:1. Depending on the complexing agent molecular weight, the level of complexing agent may be on the order of between about 5 g/L and about 250 g/L.
Surfactants may be added to promote wetting of the metal interconnect surface and enhance the deposition. The surfactant serves to reduce defects by enhancing a uniform and dense interconnect fill, thereby improving morphology and topography of the deposit. It can also help refine the grain size, which also yields a more uniform deposit. Exemplary anionic surfactants include alkyl phosphonates, alkyl ether phosphates, alkyl sulfates, alkyl ether sulfates, alkyl sulfonates, alkyl ether sulfonates, carboxylic acid ethers, carboxylic acid esters, alkyl aryl sulfonates, and sulfosuccinates. Exemplary non-ionic surfactants include alkoxylated alcohols, ethoxy/propoxy (EO/PO) block copolymers, alkoxylated fatty acids, glycol and glycerol esters, with polyethylene glycols, and polypropylene glycol/polyethylene glycol currently preferred. In one embodiment, the level of surfactant is on the order of between about 0.01 g/L and about 5 g/L.
If desired, the plating bath may also include a refractory metal ion, such as tungsten and/or molybdenum. Exemplary sources of W ions are tetramethylammonium tungstate, phosphotungstate, silicotungstate, tungstic acid, tungsten oxide, and mixtures thereof. For example, one preferred deposition bath contains between about 1 g/L and about 15 g/L of tungstic acid. Other sources of refractory metal include ammonium molybdate and/or molybdenum oxide. In one embodiment, the source of refractory ions is substantially free of alkali metals, which, if present, could contaminate the deposit.
A stabilizer may be incorporated into the electroless Co deposition bath. The use of a stabilizer can help prevent spontaneous decomposition of the bath. Exemplary stabilizers include, for example, Pb, Bi, Sn, Sb, IO3, MoO3, AsO3, azoles such as imidazole and derivatives. The stabilizer level is on the order of between about 0 and about 500 ppm. For example, for Pb+2 from about 5 to about 20 ppm has been shown to be effective. For MoO4−2, about 10 to about 300 ppm has been shown to be effective. Maleic acid is particularly advantageous in some applications because it does not add additional metal ions into the deposition bath, which could contaminate the deposit.
Other additives, as are conventionally known in the art such as rate promoters and brighteners may also be added. In some embodiments, especially for semiconductor applications, the bath is substantially free of Na and other alkali metal ions.
The reducing agent contains a borane-based component such as an alkali metal borohydride, dimethylamine borane (DMAB), diethylamine borane (DEAB), and morpholine borane. Elemental boron from the borane-based reducing agent component becomes part of the plated alloy. A reaction mechanism explaining this phenomenon with respect to borohydride is shown:
2Co2++2BH4−+4H2O=2Co0+B0+3B(OH)4−+3H++(9/2)H2
According to the reaction mechanism, the plating solution requires 2 moles of BH4− to reduce 2 moles of Co2+ into the Co alloy. To ensure that a sufficient concentration of reducing agent is present in the plating bath, in one embodiment, dimethylamine borane is added in an initial concentration of about 0.5 g/L to about 16 g/L, for example about 3 g/L. One preferred embodiment employs between about 3 g/L and about 9 g/L of DMAB.
In one embodiment of the invention, the reducing agent also includes a phosphorus-based reducing agent component, such as hypophosphite. When hypophosphite is included, the deposited alloy contains phosphorus. The reaction mechanism proposed to explain this phenomenon is shown:
Co2++4H2PO2−+H2O=Co0+3H2PO3−+H++P0+(3/2)H2
According to the reaction mechanism, the plating solution requires four moles of H2PO2− to reduce 1 mole of Co2+ into the Co alloy. The molar ratio of Co ions to hypophosphite ions in the plating solution is selected to be between about 0.1 and about 1. To ensure that a sufficient concentration of hypophosphite is present in the plating bath, in one embodiment, the hypophosphite salt, which may be an alkali metal hypophosphite, ammonium hypophosphite, or hypophosphorous acid is added in an initial concentration of about 20 g/L to about 30 g/L. In one embodiment, about 23 g/L to about 26 g/L of ammonium hypophosphite is added.
Hypophosphite reduces Co ions spontaneously only upon a limited number of substrates, including: Co, Ni, Rh, Pd, and Pt. Not included in this list is W, a particular metal of interest for its use as a drain/source in high aspect ratio interconnect features in stacked memory cells. For hypophosphite reduction of Co ions over a W substrate, the W surface may be activated by PVD or CVD Cu or Co, or Pd seeding. According to the present invention, the W surface is treated with a strong reducing agent, such as DMAB, to activate the surface for hypophosphite reduction.
In the embodiment of the invention with both borane-based and hypophosphite components in the reducing agent, a concentration ratio of a concentration of the borane-based reducing agent in grams/liter to a concentration of the hypophosphite reducing agent in grams/liter is less than about 0.5 at initial contact of the interconnect feature with the electroless deposition bath. In one embodiment, the concentration ratio is less than about 0.2 at initial contact of the interconnect feature with the electroless deposition bath. The ratio is chosen to affect the initiation and growth rate, the plating potential, and the properties of the plated alloy. For example, the ratio is chosen such that Co deposition occurs auto-catalytically on the surface of the source/drain in a stacked memory device. Moreover, because conductivity is a desired characteristic of the Co plug, the ratio of reducing agents is chosen to minimize to co-deposition of B or P. In one embodiment, a reducing agent system employs about 9 g/L DMAB reducing agent in a mixture with about 23 g/L hypophosphite reducing agent. The borane-based reducing agent initiates electroless deposition of Co2+ ions into Co metal onto the W or other metal-based drain surface. After initiation redox chemistry occurs, both reducing agents proceed to reduce Co2+ ions onto the Co surface to fill in a high aspect ratio feature of the stacked memory device.
In performing the method of the invention, surface pretreatment is performed which employs an organic or inorganic acid or basic cleaner for removing tungsten oxides from the metal interconnect feature. This cleaner preferably removes all the oxide, for example tungsten oxide, without removing substantial amounts of the metallization in the interconnects. Unless removed, the oxides can interfere with not only initiation but also adhesion of the metallization to the substrate and can detract from electrical conductivity. Cleaners of this type typically contain an etching agent such as a weak solution of an acid with less than 10 wt % in water of a strong mineral acid such as HF, HNO3, or H2SO4 or a weak organic or carboxylic acid such as citric or malonic acid. Such cleaners also include a surfactant to help wet the surface, such as Rhodafac RE620 (Rhone-Poulenc).
Typical basic cleaners contain TMAH with addition of hydroxylamine, MEA, TEAH, EDA (ethylenediamine), DTA (diethylenetriamine), or NH4OH at pH range of 9 to 12. Basic cleaning is preferred as it does not etch the side wall and cleans the oxides effectively.
On a fresh W surface, the pretreatment step is optional because the bath solution can clean the thin tungsten oxide layer at the working pH. Optionally, cationic organic compounds may be added to the pretreatment solution to protect the side wall from etching during the plating process.
As noted above, deposition of a Co-based interconnect is performed by electroless deposition employing borane chemistry. This exposure may comprise dip, flood immersion, spray, or other manner of exposing the stacked memory cell to a deposition bath, with the provision that the manner of exposure adequately achieve the objectives of depositing Co-based metallization of the desired depth and integrity into an interconnect.
Self-initiating electroless Co deposition is achieved when the borane-based reducing agent contacts the conducting surface. In particular, at certain deposition conditions, e.g. pH and temperature, the borane-based reducing agents are oxidized at the catalytic W surface, or doped Si surface as the case may be, thereby releasing electrons onto the surface. The released electrons subsequently are taken up by the Co2+ ions thereby reducing the Co2+ ions to Co metal.
This initial oxidation/reduction reaction can only be achieved at a sufficiently conducting surface such as the W surface at the via bottom. Substrates other than W may be dictated by factors germane to the device or to the drain itself which are not specifically germane to the via filling process of the invention, which substrates are nonetheless compatible therewith. Provided the drain material is at least as noble as W, the invention is applicable. The Co-based deposit does not initiate on the via side walls as the side walls are composed of a dielectric material; rather, the deposit is only initiated at the via bottom. Once an initial Co deposit is formed on the via bottom, the hypophosphite reducing agent and borane-based reducing agent interact with the Co deposit, thereby releasing electrons for further reduction of Co2+ ions to Co metal. This oxidation/reduction reaction continues and the Co deposit fills from the bottom of the via.
The process is substantially self-aligning in that the Co is deposited essentially only on the via bottom, such that the process is maskless because there is no need to mask areas other than the interconnect. Moreover, there is no need to subsequently remove substantial amounts of stray Co deposition from the dielectric.
The side walls of the vias have a dielectric surface in that they are defined by a bore in the bulk dielectric such as 12 in
In performing the invention, one of the criteria in selecting the electroless deposition composition is a desire to obtain a Co-based fill which has high conductivity. The desired conductivity is characterized by a resistivity which is, for example, preferably less than about 50 micro ohm-cm. This is in contrast to Co-based Cu-capping applications, where resistivity on the order of 60 to 80 micro ohm-cm is acceptable. With one approach, the desired conductivity is achieved by selection of bath chemistry to deposit a Co-based fill which is on the order of at least about 90 atomic % Co. To the extent the Co-based fill is diluted by bath components such as B and/or P from the reducing agents, this reduces conductivity. Accordingly, a balance is struck between a high enough reducing agent concentration to achieve acceptable deposition rates, and a low enough reducing agent concentration to yield the desired Co concentration in the deposit. If a bath characterized by a relatively higher deposition rate is employed, and a resistivity greater than about 50 micro ohm-cm in the deposit results, the resistivity can be reduced to an acceptable level by heat treatment or post annealing.
The invention is further illustrated by the following working examples.
Within the above guidelines, electroless baths having the following compositions were prepared for self-initiated Co deposition:
CoCl2 6H2O25 g/L
Citric acid 50 g/L
NH4Cl15 g/L
DMAB9 g/L
Ammonium hypophosphite 26 g/L
This bath was prepared at room temperature. The components were added according to the following steps:
1. Preparation of Solution A:
2. Preparation of Solution B:
3. Combine Solution A and Solution B and dilute to make 1 L.
4. Filter to remove any solids.
Baths were prepared according to the following lists of components to achieve other Co alloys. In each example, the bath was prepared according to the procedure outlined above, with the additional step of adding buffer (e.g., boric acid) as indicated to solutions A and B.
CoCl2 6H2O43 g/L
Citric acid 43 g/L
Boric acid 14 g/L
DMAB9 g/L
Ammonium hypophosphite 26 g/L
CoCl2 6H2O21 g/L
Malic acid 64 g/L
Boric acid 14 g/L
DMAB16 g/L
Hypophosphorous acid 26 g/L
CoCl2 6H2O22 g/L
Citric acid 22 g/L
Boric acid 8 g/L
Tungstic acid 4 g/L
DMAB3 g/L
Hypophosphorous acid 23 g/L
CoCl2 6H2O45 g/L
Citric acid 45 g/L
Boric acid 15 g/L
Tungstic acid 4 g/L
DMAB 3 g/L
Ammonium hypophosphite 23 g/L
CoCl2 6H2O45 g/L
Citric acid 45 g/L
Boric acid 15 g/L
Tungstic acid 4 g/L
DMAB 9 g/L
Hypophosphorous acid 26 g/L
CoCl2 6H2O25 g/L
Citric acid 70 g/L
NH4Cl45 g/L
DMAB10 g/L
COSO4 7H2O29 g/L
Citric acid 76 g/L
NH4Cl48 g/L
DMAB5 g/L
CoCl2 6H2O30 g/L
Citric acid 25 g/L
Boric acid 10 g/L
Tungstic acid 1 g/L
DMAB 2 g/L
CoCl2 6H2O23 g/L
Citric acid 45 g/L
NH4Cl15 g/L
Tungstic acid 4 g/L
DMAB 9 g/L
Co(OH) 25 g/L
Citric Acid 20 g/L
NH4Cl2 g/L
Tungstic acid 0.4 g/L
DMAB 0.6 g/L
Hypophosphorous Acid 6 g/L
Co(OH)23 g/L
Citric Acid 20 g/L
Pyrophosphorous Acid 10 g/L
Tungstic acid 0.4 g/L
Boric Acid 5 g/L
DMAB 0.4 g/L
Hypophosphorous Acid 4 g/L
According to the invention, interconnect substrates comprising a W bottom and SiO2 side walls were pre-cleaned to remove tungsten oxide from the conductive surface of the via interconnect feature using 5% TMAH.
The substrate was then rinsed and immersed in the Co alloy electroless bath at a temperature of 60-95° C. for 10 minutes to 2 hours. Filling occurred at an approximate rate of about 100 Angstroms/minute up to about 3000 angstroms/minute. The filled via was free of voids.
With reference to the following table, several substrates were filled with different Co alloys. For each fill, the alloy composition and approximate fill rate are shown. The alloy resistivity was between about 26 and about 80 micro ohm-cm.
Examples 5 through 8, 11, and 12 yielded acceptable resistivity of about 50 micro ohm-cm or less. Examples 2, 4, 5, and 6 had an acceptable deposition rate because of their relatively higher Co content as compared to examples 9, 11, and 12; and because of their relatively low concentration of complexing agent to metal ratio and high concentration of reducing agent.
An interconnect substrate was immersed in the electroless bath of Example 6 at a pH of 9.8 and a temperature of 75° C. for 10 minutes.
In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained.
When introducing elements of the present invention or the preferred embodiment(s) thereof, the articles “a”, “an”, “the” and “said” are intended to mean that there are one or more of the elements. For example, that the foregoing description and following claims refer to “an” interconnect means that there are one or more such interconnects. The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.
As various changes could be made in the above without departing from the scope of the invention, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.
