Claims
- 1. A compression amplifier comprising a first transistor biased as an amplifier where the voltage gain is determined by emitter current which is inversely proportional to the base voltage, whereby any decrease in base voltage causes an increase in voltage gain, said first transistor being coupled through a second transistor connected as an emitter follower directly to a peak-to-peak detector circuit adapted to produce a decreasing voltage when the average peak-to-peak amplitude of the signal at the collector of said first transistor is greater than a threshold determined by said detector circuit and to produce an increasing voltage when the average peak-to-peak amplitude of the signal at said collector is less than a threshold determined by said detector circuit, said detector circuit being coupled to the base of first transistor whereby the voltage gain of said first transistor is caused to adjust itself such that the peak-to-peak amplitude of the signal reproduced at the collector of said first transistor is substantially determined solely by the characteristics of said detector circuit.
- 2. The compression amplifier of claim 1 wherein said detector circuit is a voltage doubler.
Parent Case Info
This is a division of co-pending application Ser. No. 496,450, filed Aug. 12, 1974, now U.S. Pat. No. 3,936,617.
US Referenced Citations (3)
Divisions (1)
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Number |
Date |
Country |
Parent |
496450 |
Aug 1974 |
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